/[linux-patches]/genpatches-2.6/tags/2.6.13-4/2105_skge-1.0.patch
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Contents of /genpatches-2.6/tags/2.6.13-4/2105_skge-1.0.patch

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Revision 168 - (show annotations) (download)
Sun Sep 18 11:19:29 2005 UTC (8 years, 9 months ago) by dsd
File size: 12443 byte(s)
2.6.13-4 release
1 --- linux-2.6.13/drivers/net/skge.c.orig 2005-08-29 00:41:01.000000000 +0100
2 +++ linux-2.6.13/drivers/net/skge.c 2005-09-02 11:50:08.000000000 +0100
3 @@ -42,7 +42,7 @@
4 #include "skge.h"
5
6 #define DRV_NAME "skge"
7 -#define DRV_VERSION "0.8"
8 +#define DRV_VERSION "1.0"
9 #define PFX DRV_NAME " "
10
11 #define DEFAULT_TX_RING_SIZE 128
12 @@ -79,8 +79,8 @@ static const struct pci_device_id skge_i
13 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
14 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
15 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
16 - { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1032) },
17 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
18 + { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
19 { 0 }
20 };
21 MODULE_DEVICE_TABLE(pci, skge_id_table);
22 @@ -189,7 +189,7 @@ static u32 skge_supported_modes(const st
23 {
24 u32 supported;
25
26 - if (iscopper(hw)) {
27 + if (hw->copper) {
28 supported = SUPPORTED_10baseT_Half
29 | SUPPORTED_10baseT_Full
30 | SUPPORTED_100baseT_Half
31 @@ -222,7 +222,7 @@ static int skge_get_settings(struct net_
32 ecmd->transceiver = XCVR_INTERNAL;
33 ecmd->supported = skge_supported_modes(hw);
34
35 - if (iscopper(hw)) {
36 + if (hw->copper) {
37 ecmd->port = PORT_TP;
38 ecmd->phy_address = hw->phy_addr;
39 } else
40 @@ -669,7 +669,7 @@ static void skge_led(struct skge_port *s
41 PHY_M_LED_BLINK_RT(BLINK_84MS) |
42 PHY_M_LEDC_TX_CTRL |
43 PHY_M_LEDC_DP_CTRL);
44 -
45 +
46 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
47 PHY_M_LED_MO_RX(MO_LED_OFF) |
48 (skge->speed == SPEED_100 ?
49 @@ -876,6 +876,9 @@ static int skge_rx_fill(struct skge_port
50
51 static void skge_link_up(struct skge_port *skge)
52 {
53 + skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
54 + LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
55 +
56 netif_carrier_on(skge->netdev);
57 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
58 netif_wake_queue(skge->netdev);
59 @@ -894,6 +897,7 @@ static void skge_link_up(struct skge_por
60
61 static void skge_link_down(struct skge_port *skge)
62 {
63 + skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
64 netif_carrier_off(skge->netdev);
65 netif_stop_queue(skge->netdev);
66
67 @@ -983,6 +987,8 @@ static void genesis_reset(struct skge_hw
68 {
69 const u8 zero[8] = { 0 };
70
71 + skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
72 +
73 /* reset the statistics module */
74 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
75 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
76 @@ -1017,8 +1023,6 @@ static void bcom_check_link(struct skge_
77 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
78 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
79
80 - pr_debug("bcom_check_link status=0x%x\n", status);
81 -
82 if ((status & PHY_ST_LSYNC) == 0) {
83 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
84 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
85 @@ -1102,8 +1106,6 @@ static void bcom_phy_init(struct skge_po
86 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
87 };
88
89 - pr_debug("bcom_phy_init\n");
90 -
91 /* read Id from external PHY (all have the same address) */
92 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
93
94 @@ -1461,7 +1463,6 @@ static void genesis_link_up(struct skge_
95 u16 cmd;
96 u32 mode, msk;
97
98 - pr_debug("genesis_link_up\n");
99 cmd = xm_read16(hw, port, XM_MMU_CMD);
100
101 /*
102 @@ -1574,7 +1575,6 @@ static void yukon_init(struct skge_hw *h
103 struct skge_port *skge = netdev_priv(hw->dev[port]);
104 u16 ctrl, ct1000, adv;
105
106 - pr_debug("yukon_init\n");
107 if (skge->autoneg == AUTONEG_ENABLE) {
108 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
109
110 @@ -1599,7 +1599,7 @@ static void yukon_init(struct skge_hw *h
111 adv = PHY_AN_CSMA;
112
113 if (skge->autoneg == AUTONEG_ENABLE) {
114 - if (iscopper(hw)) {
115 + if (hw->copper) {
116 if (skge->advertising & ADVERTISED_1000baseT_Full)
117 ct1000 |= PHY_M_1000C_AFD;
118 if (skge->advertising & ADVERTISED_1000baseT_Half)
119 @@ -1691,7 +1691,7 @@ static void yukon_mac_init(struct skge_h
120 /* Set hardware config mode */
121 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
122 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
123 - reg |= iscopper(hw) ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
124 + reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
125
126 /* Clear GMC reset */
127 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
128 @@ -1725,7 +1725,7 @@ static void yukon_mac_init(struct skge_h
129 }
130
131 gma_write16(hw, port, GM_GP_CTRL, reg);
132 - skge_read16(hw, GMAC_IRQ_SRC);
133 + skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
134
135 yukon_init(hw, port);
136
137 @@ -1780,7 +1780,12 @@ static void yukon_mac_init(struct skge_h
138 reg &= ~GMF_RX_F_FL_ON;
139 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
140 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
141 - skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
142 + /*
143 + * because Pause Packet Truncation in GMAC is not working
144 + * we have to increase the Flush Threshold to 64 bytes
145 + * in order to flush pause packets in Rx FIFO on Yukon-1
146 + */
147 + skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
148
149 /* Configure Tx MAC FIFO */
150 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
151 @@ -1864,10 +1869,8 @@ static void yukon_link_up(struct skge_po
152 int port = skge->port;
153 u16 reg;
154
155 - pr_debug("yukon_link_up\n");
156 -
157 /* Enable Transmit FIFO Underrun */
158 - skge_write8(hw, GMAC_IRQ_MSK, GMAC_DEF_MSK);
159 + skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
160
161 reg = gma_read16(hw, port, GM_GP_CTRL);
162 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
163 @@ -1887,7 +1890,6 @@ static void yukon_link_down(struct skge_
164 int port = skge->port;
165 u16 ctrl;
166
167 - pr_debug("yukon_link_down\n");
168 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
169
170 ctrl = gma_read16(hw, port, GM_GP_CTRL);
171 @@ -2103,7 +2105,6 @@ static int skge_up(struct net_device *de
172 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
173 skge_led(skge, LED_MODE_ON);
174
175 - pr_debug("skge_up completed\n");
176 return 0;
177
178 free_rx_ring:
179 @@ -2358,8 +2359,6 @@ static void genesis_set_multicast(struct
180 u32 mode;
181 u8 filter[8];
182
183 - pr_debug("genesis_set_multicast flags=%x count=%d\n", dev->flags, dev->mc_count);
184 -
185 mode = xm_read32(hw, port, XM_MODE);
186 mode |= XM_MD_ENA_HASH;
187 if (dev->flags & IFF_PROMISC)
188 @@ -2521,8 +2520,6 @@ static int skge_poll(struct net_device *
189 unsigned int to_do = min(dev->quota, *budget);
190 unsigned int work_done = 0;
191
192 - pr_debug("skge_poll\n");
193 -
194 for (e = ring->to_clean; work_done < to_do; e = e->next) {
195 struct skge_rx_desc *rd = e->desc;
196 struct sk_buff *skb;
197 @@ -2663,25 +2660,13 @@ static void skge_error_irq(struct skge_h
198 if (hw->chip_id == CHIP_ID_GENESIS) {
199 /* clear xmac errors */
200 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
201 - skge_write16(hw, SK_REG(0, RX_MFF_CTRL1), MFF_CLR_INSTAT);
202 + skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
203 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
204 - skge_write16(hw, SK_REG(0, RX_MFF_CTRL2), MFF_CLR_INSTAT);
205 + skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
206 } else {
207 /* Timestamp (unused) overflow */
208 if (hwstatus & IS_IRQ_TIST_OV)
209 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
210 -
211 - if (hwstatus & IS_IRQ_SENSOR) {
212 - /* no sensors on 32-bit Yukon */
213 - if (!(skge_read16(hw, B0_CTST) & CS_BUS_SLOT_SZ)) {
214 - printk(KERN_ERR PFX "ignoring bogus sensor interrups\n");
215 - skge_write32(hw, B0_HWE_IMSK,
216 - IS_ERR_MSK & ~IS_IRQ_SENSOR);
217 - } else
218 - printk(KERN_WARNING PFX "sensor interrupt\n");
219 - }
220 -
221 -
222 }
223
224 if (hwstatus & IS_RAM_RD_PAR) {
225 @@ -2712,9 +2697,10 @@ static void skge_error_irq(struct skge_h
226
227 skge_pci_clear(hw);
228
229 + /* if error still set then just ignore it */
230 hwstatus = skge_read32(hw, B0_HWE_ISRC);
231 if (hwstatus & IS_IRQ_STAT) {
232 - printk(KERN_WARNING PFX "IRQ status %x: still set ignoring hardware errors\n",
233 + pr_debug("IRQ status %x: still set ignoring hardware errors\n",
234 hwstatus);
235 hw->intr_mask &= ~IS_HW_ERR;
236 }
237 @@ -2876,7 +2862,7 @@ static const char *skge_board_name(const
238 static int skge_reset(struct skge_hw *hw)
239 {
240 u16 ctst;
241 - u8 t8, mac_cfg;
242 + u8 t8, mac_cfg, pmd_type, phy_type;
243 int i;
244
245 ctst = skge_read16(hw, B0_CTST);
246 @@ -2895,18 +2881,19 @@ static int skge_reset(struct skge_hw *hw
247 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
248
249 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
250 - hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
251 - hw->pmd_type = skge_read8(hw, B2_PMD_TYP);
252 + phy_type = skge_read8(hw, B2_E_1) & 0xf;
253 + pmd_type = skge_read8(hw, B2_PMD_TYP);
254 + hw->copper = (pmd_type == 'T' || pmd_type == '1');
255
256 switch (hw->chip_id) {
257 case CHIP_ID_GENESIS:
258 - switch (hw->phy_type) {
259 + switch (phy_type) {
260 case SK_PHY_BCOM:
261 hw->phy_addr = PHY_ADDR_BCOM;
262 break;
263 default:
264 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
265 - pci_name(hw->pdev), hw->phy_type);
266 + pci_name(hw->pdev), phy_type);
267 return -EOPNOTSUPP;
268 }
269 break;
270 @@ -2914,13 +2901,10 @@ static int skge_reset(struct skge_hw *hw
271 case CHIP_ID_YUKON:
272 case CHIP_ID_YUKON_LITE:
273 case CHIP_ID_YUKON_LP:
274 - if (hw->phy_type < SK_PHY_MARV_COPPER && hw->pmd_type != 'S')
275 - hw->phy_type = SK_PHY_MARV_COPPER;
276 + if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
277 + hw->copper = 1;
278
279 hw->phy_addr = PHY_ADDR_MARV;
280 - if (!iscopper(hw))
281 - hw->phy_type = SK_PHY_MARV_FIBER;
282 -
283 break;
284
285 default:
286 @@ -2948,12 +2932,20 @@ static int skge_reset(struct skge_hw *hw
287 else
288 hw->ram_size = t8 * 4096;
289
290 + hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
291 if (hw->chip_id == CHIP_ID_GENESIS)
292 genesis_init(hw);
293 else {
294 /* switch power to VCC (WA for VAUX problem) */
295 skge_write8(hw, B0_POWER_CTRL,
296 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
297 + /* avoid boards with stuck Hardware error bits */
298 + if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
299 + (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
300 + printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
301 + hw->intr_mask &= ~IS_HW_ERR;
302 + }
303 +
304 for (i = 0; i < hw->ports; i++) {
305 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
306 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
307 @@ -2994,12 +2986,8 @@ static int skge_reset(struct skge_hw *hw
308 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
309 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
310
311 - hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
312 skge_write32(hw, B0_IMSK, hw->intr_mask);
313
314 - if (hw->chip_id != CHIP_ID_GENESIS)
315 - skge_write8(hw, GMAC_IRQ_MSK, 0);
316 -
317 spin_lock_bh(&hw->phy_lock);
318 for (i = 0; i < hw->ports; i++) {
319 if (hw->chip_id == CHIP_ID_GENESIS)
320 --- linux-2.6.13/drivers/net/skge.h.orig 2005-08-29 00:41:01.000000000 +0100
321 +++ linux-2.6.13/drivers/net/skge.h 2005-09-02 11:50:08.000000000 +0100
322 @@ -214,8 +214,6 @@ enum {
323
324 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
325 enum {
326 - IS_ERR_MSK = 0x00003fff,/* All Error bits */
327 -
328 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
329 IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
330 IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
331 @@ -230,6 +228,12 @@ enum {
332 IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
333 IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
334 IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
335 +
336 + IS_ERR_MSK = IS_IRQ_MST_ERR | IS_IRQ_STAT
337 + | IS_NO_STAT_M1 | IS_NO_STAT_M2
338 + | IS_RAM_RD_PAR | IS_RAM_WR_PAR
339 + | IS_M1_PAR_ERR | IS_M2_PAR_ERR
340 + | IS_R1_PAR_ERR | IS_R2_PAR_ERR,
341 };
342
343 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
344 @@ -2004,7 +2008,7 @@ enum {
345 GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */
346 GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
347
348 -#define GMAC_DEF_MSK (GM_IS_TX_CO_OV | GM_IS_RX_CO_OV | GM_IS_TX_FF_UR)
349 +#define GMAC_DEF_MSK (GM_IS_RX_FF_OR | GM_IS_TX_FF_UR)
350
351 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
352 /* Bits 15.. 2: reserved */
353 @@ -2456,24 +2460,17 @@ struct skge_hw {
354
355 u8 chip_id;
356 u8 chip_rev;
357 - u8 phy_type;
358 - u8 pmd_type;
359 - u16 phy_addr;
360 + u8 copper;
361 u8 ports;
362
363 u32 ram_size;
364 u32 ram_offset;
365 + u16 phy_addr;
366
367 struct tasklet_struct ext_tasklet;
368 spinlock_t phy_lock;
369 };
370
371 -
372 -static inline int iscopper(const struct skge_hw *hw)
373 -{
374 - return (hw->pmd_type == 'T');
375 -}
376 -
377 enum {
378 FLOW_MODE_NONE = 0, /* No Flow-Control */
379 FLOW_MODE_LOC_SEND = 1, /* Local station sends PAUSE */

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