/[linux-patches]/genpatches-2.6/tags/2.6.15-2/4100_sky2-0.12.patch
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Contents of /genpatches-2.6/tags/2.6.15-2/4100_sky2-0.12.patch

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Revision 259 - (show annotations) (download)
Wed Jan 11 21:46:01 2006 UTC (8 years, 3 months ago) by dsd
File size: 168437 byte(s)
2.6.15-2 release
1 Version 0.12 of sky2
2
3 --- linux-2.6.15/drivers/net/sky2.c 1970-01-01 01:00:00.000000000 +0100
4 +++ linux-dsd/drivers/net/sky2.c 2006-01-11 21:23:15.000000000 +0000
5 @@ -0,0 +1,3283 @@
6 +/*
7 + * New driver for Marvell Yukon 2 chipset.
8 + * Based on earlier sk98lin, and skge driver.
9 + *
10 + * This driver intentionally does not support all the features
11 + * of the original driver such as link fail-over and link management because
12 + * those should be done at higher levels.
13 + *
14 + * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
15 + *
16 + * This program is free software; you can redistribute it and/or modify
17 + * it under the terms of the GNU General Public License as published by
18 + * the Free Software Foundation; either version 2 of the License, or
19 + * (at your option) any later version.
20 + *
21 + * This program is distributed in the hope that it will be useful,
22 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 + * GNU General Public License for more details.
25 + *
26 + * You should have received a copy of the GNU General Public License
27 + * along with this program; if not, write to the Free Software
28 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 + */
30 +
31 +/*
32 + * TOTEST
33 + * - speed setting
34 + * - suspend/resume
35 + */
36 +
37 +#include <linux/config.h>
38 +#include <linux/crc32.h>
39 +#include <linux/kernel.h>
40 +#include <linux/version.h>
41 +#include <linux/module.h>
42 +#include <linux/netdevice.h>
43 +#include <linux/dma-mapping.h>
44 +#include <linux/etherdevice.h>
45 +#include <linux/ethtool.h>
46 +#include <linux/pci.h>
47 +#include <linux/ip.h>
48 +#include <linux/tcp.h>
49 +#include <linux/in.h>
50 +#include <linux/delay.h>
51 +#include <linux/workqueue.h>
52 +#include <linux/if_vlan.h>
53 +#include <linux/prefetch.h>
54 +#include <linux/mii.h>
55 +
56 +#include <asm/irq.h>
57 +
58 +#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
59 +#define SKY2_VLAN_TAG_USED 1
60 +#endif
61 +
62 +#include "sky2.h"
63 +
64 +#define DRV_NAME "sky2"
65 +#define DRV_VERSION "0.12"
66 +#define PFX DRV_NAME " "
67 +
68 +/*
69 + * The Yukon II chipset takes 64 bit command blocks (called list elements)
70 + * that are organized into three (receive, transmit, status) different rings
71 + * similar to Tigon3. A transmit can require several elements;
72 + * a receive requires one (or two if using 64 bit dma).
73 + */
74 +
75 +#define is_ec_a1(hw) \
76 + unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
77 + (hw)->chip_rev == CHIP_REV_YU_EC_A1)
78 +
79 +#define RX_LE_SIZE 512
80 +#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
81 +#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
82 +#define RX_DEF_PENDING RX_MAX_PENDING
83 +#define RX_SKB_ALIGN 8
84 +
85 +#define TX_RING_SIZE 512
86 +#define TX_DEF_PENDING (TX_RING_SIZE - 1)
87 +#define TX_MIN_PENDING 64
88 +#define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
89 +
90 +#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
91 +#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
92 +#define ETH_JUMBO_MTU 9000
93 +#define TX_WATCHDOG (5 * HZ)
94 +#define NAPI_WEIGHT 64
95 +#define PHY_RETRIES 1000
96 +
97 +static const u32 default_msg =
98 + NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
99 + | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
100 + | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_INTR;
101 +
102 +static int debug = -1; /* defaults above */
103 +module_param(debug, int, 0);
104 +MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
105 +
106 +static int copybreak __read_mostly = 256;
107 +module_param(copybreak, int, 0);
108 +MODULE_PARM_DESC(copybreak, "Receive copy threshold");
109 +
110 +static const struct pci_device_id sky2_id_table[] = {
111 + { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
112 + { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
113 + { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
114 + { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
115 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
116 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
117 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
118 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
119 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
120 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
121 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
122 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
123 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
124 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
125 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
126 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
127 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
128 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
129 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
130 + { 0 }
131 +};
132 +
133 +MODULE_DEVICE_TABLE(pci, sky2_id_table);
134 +
135 +/* Avoid conditionals by using array */
136 +static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
137 +static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
138 +
139 +/* This driver supports yukon2 chipset only */
140 +static const char *yukon2_name[] = {
141 + "XL", /* 0xb3 */
142 + "EC Ultra", /* 0xb4 */
143 + "UNKNOWN", /* 0xb5 */
144 + "EC", /* 0xb6 */
145 + "FE", /* 0xb7 */
146 +};
147 +
148 +/* Access to external PHY */
149 +static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
150 +{
151 + int i;
152 +
153 + gma_write16(hw, port, GM_SMI_DATA, val);
154 + gma_write16(hw, port, GM_SMI_CTRL,
155 + GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
156 +
157 + for (i = 0; i < PHY_RETRIES; i++) {
158 + if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
159 + return 0;
160 + udelay(1);
161 + }
162 +
163 + printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
164 + return -ETIMEDOUT;
165 +}
166 +
167 +static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
168 +{
169 + int i;
170 +
171 + gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
172 + | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
173 +
174 + for (i = 0; i < PHY_RETRIES; i++) {
175 + if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
176 + *val = gma_read16(hw, port, GM_SMI_DATA);
177 + return 0;
178 + }
179 +
180 + udelay(1);
181 + }
182 +
183 + return -ETIMEDOUT;
184 +}
185 +
186 +static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
187 +{
188 + u16 v;
189 +
190 + if (__gm_phy_read(hw, port, reg, &v) != 0)
191 + printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
192 + return v;
193 +}
194 +
195 +static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
196 +{
197 + u16 power_control;
198 + u32 reg1;
199 + int vaux;
200 + int ret = 0;
201 +
202 + pr_debug("sky2_set_power_state %d\n", state);
203 + sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
204 +
205 + pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control);
206 + vaux = (sky2_read8(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
207 + (power_control & PCI_PM_CAP_PME_D3cold);
208 +
209 + pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control);
210 +
211 + power_control |= PCI_PM_CTRL_PME_STATUS;
212 + power_control &= ~(PCI_PM_CTRL_STATE_MASK);
213 +
214 + switch (state) {
215 + case PCI_D0:
216 + /* switch power to VCC (WA for VAUX problem) */
217 + sky2_write8(hw, B0_POWER_CTRL,
218 + PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
219 +
220 + /* disable Core Clock Division, */
221 + sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
222 +
223 + if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
224 + /* enable bits are inverted */
225 + sky2_write8(hw, B2_Y2_CLK_GATE,
226 + Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
227 + Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
228 + Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
229 + else
230 + sky2_write8(hw, B2_Y2_CLK_GATE, 0);
231 +
232 + /* Turn off phy power saving */
233 + pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
234 + reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
235 +
236 + /* looks like this XL is back asswards .. */
237 + if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
238 + reg1 |= PCI_Y2_PHY1_COMA;
239 + if (hw->ports > 1)
240 + reg1 |= PCI_Y2_PHY2_COMA;
241 + }
242 + pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
243 + break;
244 +
245 + case PCI_D3hot:
246 + case PCI_D3cold:
247 + /* Turn on phy power saving */
248 + pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
249 + if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
250 + reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
251 + else
252 + reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
253 + pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
254 +
255 + if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
256 + sky2_write8(hw, B2_Y2_CLK_GATE, 0);
257 + else
258 + /* enable bits are inverted */
259 + sky2_write8(hw, B2_Y2_CLK_GATE,
260 + Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
261 + Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
262 + Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
263 +
264 + /* switch power to VAUX */
265 + if (vaux && state != PCI_D3cold)
266 + sky2_write8(hw, B0_POWER_CTRL,
267 + (PC_VAUX_ENA | PC_VCC_ENA |
268 + PC_VAUX_ON | PC_VCC_OFF));
269 + break;
270 + default:
271 + printk(KERN_ERR PFX "Unknown power state %d\n", state);
272 + ret = -1;
273 + }
274 +
275 + pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control);
276 + sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
277 + return ret;
278 +}
279 +
280 +static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
281 +{
282 + u16 reg;
283 +
284 + /* disable all GMAC IRQ's */
285 + sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
286 + /* disable PHY IRQs */
287 + gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
288 +
289 + gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
290 + gma_write16(hw, port, GM_MC_ADDR_H2, 0);
291 + gma_write16(hw, port, GM_MC_ADDR_H3, 0);
292 + gma_write16(hw, port, GM_MC_ADDR_H4, 0);
293 +
294 + reg = gma_read16(hw, port, GM_RX_CTRL);
295 + reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
296 + gma_write16(hw, port, GM_RX_CTRL, reg);
297 +}
298 +
299 +static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
300 +{
301 + struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
302 + u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
303 +
304 + if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
305 + u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
306 +
307 + ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
308 + PHY_M_EC_MAC_S_MSK);
309 + ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
310 +
311 + if (hw->chip_id == CHIP_ID_YUKON_EC)
312 + ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
313 + else
314 + ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
315 +
316 + gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
317 + }
318 +
319 + ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
320 + if (hw->copper) {
321 + if (hw->chip_id == CHIP_ID_YUKON_FE) {
322 + /* enable automatic crossover */
323 + ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
324 + } else {
325 + /* disable energy detect */
326 + ctrl &= ~PHY_M_PC_EN_DET_MSK;
327 +
328 + /* enable automatic crossover */
329 + ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
330 +
331 + if (sky2->autoneg == AUTONEG_ENABLE &&
332 + hw->chip_id == CHIP_ID_YUKON_XL) {
333 + ctrl &= ~PHY_M_PC_DSC_MSK;
334 + ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
335 + }
336 + }
337 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
338 + } else {
339 + /* workaround for deviation #4.88 (CRC errors) */
340 + /* disable Automatic Crossover */
341 +
342 + ctrl &= ~PHY_M_PC_MDIX_MSK;
343 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
344 +
345 + if (hw->chip_id == CHIP_ID_YUKON_XL) {
346 + /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
347 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
348 + ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
349 + ctrl &= ~PHY_M_MAC_MD_MSK;
350 + ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
351 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
352 +
353 + /* select page 1 to access Fiber registers */
354 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
355 + }
356 + }
357 +
358 + ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
359 + if (sky2->autoneg == AUTONEG_DISABLE)
360 + ctrl &= ~PHY_CT_ANE;
361 + else
362 + ctrl |= PHY_CT_ANE;
363 +
364 + ctrl |= PHY_CT_RESET;
365 + gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
366 +
367 + ctrl = 0;
368 + ct1000 = 0;
369 + adv = PHY_AN_CSMA;
370 +
371 + if (sky2->autoneg == AUTONEG_ENABLE) {
372 + if (hw->copper) {
373 + if (sky2->advertising & ADVERTISED_1000baseT_Full)
374 + ct1000 |= PHY_M_1000C_AFD;
375 + if (sky2->advertising & ADVERTISED_1000baseT_Half)
376 + ct1000 |= PHY_M_1000C_AHD;
377 + if (sky2->advertising & ADVERTISED_100baseT_Full)
378 + adv |= PHY_M_AN_100_FD;
379 + if (sky2->advertising & ADVERTISED_100baseT_Half)
380 + adv |= PHY_M_AN_100_HD;
381 + if (sky2->advertising & ADVERTISED_10baseT_Full)
382 + adv |= PHY_M_AN_10_FD;
383 + if (sky2->advertising & ADVERTISED_10baseT_Half)
384 + adv |= PHY_M_AN_10_HD;
385 + } else /* special defines for FIBER (88E1011S only) */
386 + adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
387 +
388 + /* Set Flow-control capabilities */
389 + if (sky2->tx_pause && sky2->rx_pause)
390 + adv |= PHY_AN_PAUSE_CAP; /* symmetric */
391 + else if (sky2->rx_pause && !sky2->tx_pause)
392 + adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
393 + else if (!sky2->rx_pause && sky2->tx_pause)
394 + adv |= PHY_AN_PAUSE_ASYM; /* local */
395 +
396 + /* Restart Auto-negotiation */
397 + ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
398 + } else {
399 + /* forced speed/duplex settings */
400 + ct1000 = PHY_M_1000C_MSE;
401 +
402 + if (sky2->duplex == DUPLEX_FULL)
403 + ctrl |= PHY_CT_DUP_MD;
404 +
405 + switch (sky2->speed) {
406 + case SPEED_1000:
407 + ctrl |= PHY_CT_SP1000;
408 + break;
409 + case SPEED_100:
410 + ctrl |= PHY_CT_SP100;
411 + break;
412 + }
413 +
414 + ctrl |= PHY_CT_RESET;
415 + }
416 +
417 + if (hw->chip_id != CHIP_ID_YUKON_FE)
418 + gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
419 +
420 + gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
421 + gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
422 +
423 + /* Setup Phy LED's */
424 + ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
425 + ledover = 0;
426 +
427 + switch (hw->chip_id) {
428 + case CHIP_ID_YUKON_FE:
429 + /* on 88E3082 these bits are at 11..9 (shifted left) */
430 + ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
431 +
432 + ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
433 +
434 + /* delete ACT LED control bits */
435 + ctrl &= ~PHY_M_FELP_LED1_MSK;
436 + /* change ACT LED control to blink mode */
437 + ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
438 + gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
439 + break;
440 +
441 + case CHIP_ID_YUKON_XL:
442 + pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
443 +
444 + /* select page 3 to access LED control register */
445 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
446 +
447 + /* set LED Function Control register */
448 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
449 + PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
450 + PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
451 + PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
452 +
453 + /* set Polarity Control register */
454 + gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
455 + (PHY_M_POLC_LS1_P_MIX(4) |
456 + PHY_M_POLC_IS0_P_MIX(4) |
457 + PHY_M_POLC_LOS_CTRL(2) |
458 + PHY_M_POLC_INIT_CTRL(2) |
459 + PHY_M_POLC_STA1_CTRL(2) |
460 + PHY_M_POLC_STA0_CTRL(2)));
461 +
462 + /* restore page register */
463 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
464 + break;
465 +
466 + default:
467 + /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
468 + ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
469 + /* turn off the Rx LED (LED_RX) */
470 + ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
471 + }
472 +
473 + gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
474 +
475 + if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
476 + /* turn on 100 Mbps LED (LED_LINK100) */
477 + ledover |= PHY_M_LED_MO_100(MO_LED_ON);
478 + }
479 +
480 + if (ledover)
481 + gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
482 +
483 + /* Enable phy interrupt on auto-negotiation complete (or link up) */
484 + if (sky2->autoneg == AUTONEG_ENABLE)
485 + gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
486 + else
487 + gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
488 +}
489 +
490 +/* Force a renegotiation */
491 +static void sky2_phy_reinit(struct sky2_port *sky2)
492 +{
493 + down(&sky2->phy_sema);
494 + sky2_phy_init(sky2->hw, sky2->port);
495 + up(&sky2->phy_sema);
496 +}
497 +
498 +static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
499 +{
500 + struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
501 + u16 reg;
502 + int i;
503 + const u8 *addr = hw->dev[port]->dev_addr;
504 +
505 + sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
506 + sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
507 +
508 + sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
509 +
510 + if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
511 + /* WA DEV_472 -- looks like crossed wires on port 2 */
512 + /* clear GMAC 1 Control reset */
513 + sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
514 + do {
515 + sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
516 + sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
517 + } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
518 + gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
519 + gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
520 + }
521 +
522 + if (sky2->autoneg == AUTONEG_DISABLE) {
523 + reg = gma_read16(hw, port, GM_GP_CTRL);
524 + reg |= GM_GPCR_AU_ALL_DIS;
525 + gma_write16(hw, port, GM_GP_CTRL, reg);
526 + gma_read16(hw, port, GM_GP_CTRL);
527 +
528 + switch (sky2->speed) {
529 + case SPEED_1000:
530 + reg |= GM_GPCR_SPEED_1000;
531 + /* fallthru */
532 + case SPEED_100:
533 + reg |= GM_GPCR_SPEED_100;
534 + }
535 +
536 + if (sky2->duplex == DUPLEX_FULL)
537 + reg |= GM_GPCR_DUP_FULL;
538 + } else
539 + reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
540 +
541 + if (!sky2->tx_pause && !sky2->rx_pause) {
542 + sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
543 + reg |=
544 + GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
545 + } else if (sky2->tx_pause && !sky2->rx_pause) {
546 + /* disable Rx flow-control */
547 + reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
548 + }
549 +
550 + gma_write16(hw, port, GM_GP_CTRL, reg);
551 +
552 + sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
553 +
554 + down(&sky2->phy_sema);
555 + sky2_phy_init(hw, port);
556 + up(&sky2->phy_sema);
557 +
558 + /* MIB clear */
559 + reg = gma_read16(hw, port, GM_PHY_ADDR);
560 + gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
561 +
562 + for (i = 0; i < GM_MIB_CNT_SIZE; i++)
563 + gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
564 + gma_write16(hw, port, GM_PHY_ADDR, reg);
565 +
566 + /* transmit control */
567 + gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
568 +
569 + /* receive control reg: unicast + multicast + no FCS */
570 + gma_write16(hw, port, GM_RX_CTRL,
571 + GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
572 +
573 + /* transmit flow control */
574 + gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
575 +
576 + /* transmit parameter */
577 + gma_write16(hw, port, GM_TX_PARAM,
578 + TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
579 + TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
580 + TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
581 + TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
582 +
583 + /* serial mode register */
584 + reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
585 + GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
586 +
587 + if (hw->dev[port]->mtu > ETH_DATA_LEN)
588 + reg |= GM_SMOD_JUMBO_ENA;
589 +
590 + gma_write16(hw, port, GM_SERIAL_MODE, reg);
591 +
592 + /* virtual address for data */
593 + gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
594 +
595 + /* physical address: used for pause frames */
596 + gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
597 +
598 + /* ignore counter overflows */
599 + gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
600 + gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
601 + gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
602 +
603 + /* Configure Rx MAC FIFO */
604 + sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
605 + sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
606 + GMF_RX_CTRL_DEF);
607 +
608 + /* Flush Rx MAC FIFO on any flow control or error */
609 + sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
610 +
611 + /* Set threshold to 0xa (64 bytes)
612 + * ASF disabled so no need to do WA dev #4.30
613 + */
614 + sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
615 +
616 + /* Configure Tx MAC FIFO */
617 + sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
618 + sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
619 +
620 + if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
621 + sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
622 + sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
623 + if (hw->dev[port]->mtu > ETH_DATA_LEN) {
624 + /* set Tx GMAC FIFO Almost Empty Threshold */
625 + sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
626 + /* Disable Store & Forward mode for TX */
627 + sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
628 + }
629 + }
630 +
631 +}
632 +
633 +static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, size_t len)
634 +{
635 + u32 end;
636 +
637 + start /= 8;
638 + len /= 8;
639 + end = start + len - 1;
640 +
641 + sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
642 + sky2_write32(hw, RB_ADDR(q, RB_START), start);
643 + sky2_write32(hw, RB_ADDR(q, RB_END), end);
644 + sky2_write32(hw, RB_ADDR(q, RB_WP), start);
645 + sky2_write32(hw, RB_ADDR(q, RB_RP), start);
646 +
647 + if (q == Q_R1 || q == Q_R2) {
648 + u32 rxup, rxlo;
649 +
650 + rxlo = len/2;
651 + rxup = rxlo + len/4;
652 +
653 + /* Set thresholds on receive queue's */
654 + sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), rxup);
655 + sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), rxlo);
656 + } else {
657 + /* Enable store & forward on Tx queue's because
658 + * Tx FIFO is only 1K on Yukon
659 + */
660 + sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
661 + }
662 +
663 + sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
664 + sky2_read8(hw, RB_ADDR(q, RB_CTRL));
665 +}
666 +
667 +/* Setup Bus Memory Interface */
668 +static void sky2_qset(struct sky2_hw *hw, u16 q)
669 +{
670 + sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
671 + sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
672 + sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
673 + sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
674 +}
675 +
676 +/* Setup prefetch unit registers. This is the interface between
677 + * hardware and driver list elements
678 + */
679 +static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
680 + u64 addr, u32 last)
681 +{
682 + sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
683 + sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
684 + sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
685 + sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
686 + sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
687 + sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
688 +
689 + sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
690 +}
691 +
692 +static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
693 +{
694 + struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
695 +
696 + sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
697 + return le;
698 +}
699 +
700 +/*
701 + * This is a workaround code taken from SysKonnect sk98lin driver
702 + * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
703 + */
704 +static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q,
705 + u16 idx, u16 *last, u16 size)
706 +{
707 + if (is_ec_a1(hw) && idx < *last) {
708 + u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
709 +
710 + if (hwget == 0) {
711 + /* Start prefetching again */
712 + sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
713 + goto setnew;
714 + }
715 +
716 + if (hwget == size - 1) {
717 + /* set watermark to one list element */
718 + sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
719 +
720 + /* set put index to first list element */
721 + sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
722 + } else /* have hardware go to end of list */
723 + sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
724 + size - 1);
725 + } else {
726 +setnew:
727 + sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
728 + }
729 + *last = idx;
730 +}
731 +
732 +
733 +static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
734 +{
735 + struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
736 + sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
737 + return le;
738 +}
739 +
740 +/* Return high part of DMA address (could be 32 or 64 bit) */
741 +static inline u32 high32(dma_addr_t a)
742 +{
743 + return (a >> 16) >> 16;
744 +}
745 +
746 +/* Build description to hardware about buffer */
747 +static inline void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
748 +{
749 + struct sky2_rx_le *le;
750 + u32 hi = high32(map);
751 + u16 len = sky2->rx_bufsize;
752 +
753 + if (sky2->rx_addr64 != hi) {
754 + le = sky2_next_rx(sky2);
755 + le->addr = cpu_to_le32(hi);
756 + le->ctrl = 0;
757 + le->opcode = OP_ADDR64 | HW_OWNER;
758 + sky2->rx_addr64 = high32(map + len);
759 + }
760 +
761 + le = sky2_next_rx(sky2);
762 + le->addr = cpu_to_le32((u32) map);
763 + le->length = cpu_to_le16(len);
764 + le->ctrl = 0;
765 + le->opcode = OP_PACKET | HW_OWNER;
766 +}
767 +
768 +
769 +/* Tell chip where to start receive checksum.
770 + * Actually has two checksums, but set both same to avoid possible byte
771 + * order problems.
772 + */
773 +static void rx_set_checksum(struct sky2_port *sky2)
774 +{
775 + struct sky2_rx_le *le;
776 +
777 + le = sky2_next_rx(sky2);
778 + le->addr = (ETH_HLEN << 16) | ETH_HLEN;
779 + le->ctrl = 0;
780 + le->opcode = OP_TCPSTART | HW_OWNER;
781 +
782 + sky2_write32(sky2->hw,
783 + Q_ADDR(rxqaddr[sky2->port], Q_CSR),
784 + sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
785 +
786 +}
787 +
788 +/*
789 + * The RX Stop command will not work for Yukon-2 if the BMU does not
790 + * reach the end of packet and since we can't make sure that we have
791 + * incoming data, we must reset the BMU while it is not doing a DMA
792 + * transfer. Since it is possible that the RX path is still active,
793 + * the RX RAM buffer will be stopped first, so any possible incoming
794 + * data will not trigger a DMA. After the RAM buffer is stopped, the
795 + * BMU is polled until any DMA in progress is ended and only then it
796 + * will be reset.
797 + */
798 +static void sky2_rx_stop(struct sky2_port *sky2)
799 +{
800 + struct sky2_hw *hw = sky2->hw;
801 + unsigned rxq = rxqaddr[sky2->port];
802 + int i;
803 +
804 + /* disable the RAM Buffer receive queue */
805 + sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
806 +
807 + for (i = 0; i < 0xffff; i++)
808 + if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
809 + == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
810 + goto stopped;
811 +
812 + printk(KERN_WARNING PFX "%s: receiver stop failed\n",
813 + sky2->netdev->name);
814 +stopped:
815 + sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
816 +
817 + /* reset the Rx prefetch unit */
818 + sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
819 +}
820 +
821 +/* Clean out receive buffer area, assumes receiver hardware stopped */
822 +static void sky2_rx_clean(struct sky2_port *sky2)
823 +{
824 + unsigned i;
825 +
826 + memset(sky2->rx_le, 0, RX_LE_BYTES);
827 + for (i = 0; i < sky2->rx_pending; i++) {
828 + struct ring_info *re = sky2->rx_ring + i;
829 +
830 + if (re->skb) {
831 + pci_unmap_single(sky2->hw->pdev,
832 + re->mapaddr, sky2->rx_bufsize,
833 + PCI_DMA_FROMDEVICE);
834 + kfree_skb(re->skb);
835 + re->skb = NULL;
836 + }
837 + }
838 +}
839 +
840 +/* Basic MII support */
841 +static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
842 +{
843 + struct mii_ioctl_data *data = if_mii(ifr);
844 + struct sky2_port *sky2 = netdev_priv(dev);
845 + struct sky2_hw *hw = sky2->hw;
846 + int err = -EOPNOTSUPP;
847 +
848 + if (!netif_running(dev))
849 + return -ENODEV; /* Phy still in reset */
850 +
851 + switch(cmd) {
852 + case SIOCGMIIPHY:
853 + data->phy_id = PHY_ADDR_MARV;
854 +
855 + /* fallthru */
856 + case SIOCGMIIREG: {
857 + u16 val = 0;
858 +
859 + down(&sky2->phy_sema);
860 + err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
861 + up(&sky2->phy_sema);
862 +
863 + data->val_out = val;
864 + break;
865 + }
866 +
867 + case SIOCSMIIREG:
868 + if (!capable(CAP_NET_ADMIN))
869 + return -EPERM;
870 +
871 + down(&sky2->phy_sema);
872 + err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
873 + data->val_in);
874 + up(&sky2->phy_sema);
875 + break;
876 + }
877 + return err;
878 +}
879 +
880 +#ifdef SKY2_VLAN_TAG_USED
881 +static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
882 +{
883 + struct sky2_port *sky2 = netdev_priv(dev);
884 + struct sky2_hw *hw = sky2->hw;
885 + u16 port = sky2->port;
886 +
887 + spin_lock(&sky2->tx_lock);
888 +
889 + sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
890 + sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
891 + sky2->vlgrp = grp;
892 +
893 + spin_unlock(&sky2->tx_lock);
894 +}
895 +
896 +static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
897 +{
898 + struct sky2_port *sky2 = netdev_priv(dev);
899 + struct sky2_hw *hw = sky2->hw;
900 + u16 port = sky2->port;
901 +
902 + spin_lock(&sky2->tx_lock);
903 +
904 + sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
905 + sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
906 + if (sky2->vlgrp)
907 + sky2->vlgrp->vlan_devices[vid] = NULL;
908 +
909 + spin_unlock(&sky2->tx_lock);
910 +}
911 +#endif
912 +
913 +/*
914 + * It appears the hardware has a bug in the FIFO logic that
915 + * cause it to hang if the FIFO gets overrun and the receive buffer
916 + * is not aligned. ALso alloc_skb() won't align properly if slab
917 + * debugging is enabled.
918 + */
919 +static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
920 +{
921 + struct sk_buff *skb;
922 +
923 + skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
924 + if (likely(skb)) {
925 + unsigned long p = (unsigned long) skb->data;
926 + skb_reserve(skb,
927 + ((p + RX_SKB_ALIGN - 1) & ~(RX_SKB_ALIGN - 1)) - p);
928 + }
929 +
930 + return skb;
931 +}
932 +
933 +/*
934 + * Allocate and setup receiver buffer pool.
935 + * In case of 64 bit dma, there are 2X as many list elements
936 + * available as ring entries
937 + * and need to reserve one list element so we don't wrap around.
938 + */
939 +static int sky2_rx_start(struct sky2_port *sky2)
940 +{
941 + struct sky2_hw *hw = sky2->hw;
942 + unsigned rxq = rxqaddr[sky2->port];
943 + int i;
944 +
945 + sky2->rx_put = sky2->rx_next = 0;
946 + sky2_qset(hw, rxq);
947 + sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
948 +
949 + rx_set_checksum(sky2);
950 + for (i = 0; i < sky2->rx_pending; i++) {
951 + struct ring_info *re = sky2->rx_ring + i;
952 +
953 + re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
954 + if (!re->skb)
955 + goto nomem;
956 +
957 + re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
958 + sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
959 + sky2_rx_add(sky2, re->mapaddr);
960 + }
961 +
962 + /* Tell chip about available buffers */
963 + sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
964 + sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
965 + return 0;
966 +nomem:
967 + sky2_rx_clean(sky2);
968 + return -ENOMEM;
969 +}
970 +
971 +/* Bring up network interface. */
972 +static int sky2_up(struct net_device *dev)
973 +{
974 + struct sky2_port *sky2 = netdev_priv(dev);
975 + struct sky2_hw *hw = sky2->hw;
976 + unsigned port = sky2->port;
977 + u32 ramsize, rxspace;
978 + int err = -ENOMEM;
979 +
980 + if (netif_msg_ifup(sky2))
981 + printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
982 +
983 + /* must be power of 2 */
984 + sky2->tx_le = pci_alloc_consistent(hw->pdev,
985 + TX_RING_SIZE *
986 + sizeof(struct sky2_tx_le),
987 + &sky2->tx_le_map);
988 + if (!sky2->tx_le)
989 + goto err_out;
990 +
991 + sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
992 + GFP_KERNEL);
993 + if (!sky2->tx_ring)
994 + goto err_out;
995 + sky2->tx_prod = sky2->tx_cons = 0;
996 +
997 + sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
998 + &sky2->rx_le_map);
999 + if (!sky2->rx_le)
1000 + goto err_out;
1001 + memset(sky2->rx_le, 0, RX_LE_BYTES);
1002 +
1003 + sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
1004 + GFP_KERNEL);
1005 + if (!sky2->rx_ring)
1006 + goto err_out;
1007 +
1008 + sky2_mac_init(hw, port);
1009 +
1010 + /* Configure RAM buffers */
1011 + if (hw->chip_id == CHIP_ID_YUKON_FE ||
1012 + (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == 2))
1013 + ramsize = 4096;
1014 + else {
1015 + u8 e0 = sky2_read8(hw, B2_E_0);
1016 + ramsize = (e0 == 0) ? (128 * 1024) : (e0 * 4096);
1017 + }
1018 +
1019 + /* 2/3 for Rx */
1020 + rxspace = (2 * ramsize) / 3;
1021 + sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1022 + sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1023 +
1024 + /* Make sure SyncQ is disabled */
1025 + sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1026 + RB_RST_SET);
1027 +
1028 + sky2_qset(hw, txqaddr[port]);
1029 + if (hw->chip_id == CHIP_ID_YUKON_EC_U)
1030 + sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1031 +
1032 +
1033 + sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1034 + TX_RING_SIZE - 1);
1035 +
1036 + err = sky2_rx_start(sky2);
1037 + if (err)
1038 + goto err_out;
1039 +
1040 + /* Enable interrupts from phy/mac for port */
1041 + hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1042 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
1043 + return 0;
1044 +
1045 +err_out:
1046 + if (sky2->rx_le) {
1047 + pci_free_consistent(hw->pdev, RX_LE_BYTES,
1048 + sky2->rx_le, sky2->rx_le_map);
1049 + sky2->rx_le = NULL;
1050 + }
1051 + if (sky2->tx_le) {
1052 + pci_free_consistent(hw->pdev,
1053 + TX_RING_SIZE * sizeof(struct sky2_tx_le),
1054 + sky2->tx_le, sky2->tx_le_map);
1055 + sky2->tx_le = NULL;
1056 + }
1057 + kfree(sky2->tx_ring);
1058 + kfree(sky2->rx_ring);
1059 +
1060 + sky2->tx_ring = NULL;
1061 + sky2->rx_ring = NULL;
1062 + return err;
1063 +}
1064 +
1065 +/* Modular subtraction in ring */
1066 +static inline int tx_dist(unsigned tail, unsigned head)
1067 +{
1068 + return (head - tail) % TX_RING_SIZE;
1069 +}
1070 +
1071 +/* Number of list elements available for next tx */
1072 +static inline int tx_avail(const struct sky2_port *sky2)
1073 +{
1074 + return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1075 +}
1076 +
1077 +/* Estimate of number of transmit list elements required */
1078 +static inline unsigned tx_le_req(const struct sk_buff *skb)
1079 +{
1080 + unsigned count;
1081 +
1082 + count = sizeof(dma_addr_t) / sizeof(u32);
1083 + count += skb_shinfo(skb)->nr_frags * count;
1084 +
1085 + if (skb_shinfo(skb)->tso_size)
1086 + ++count;
1087 +
1088 + if (skb->ip_summed == CHECKSUM_HW)
1089 + ++count;
1090 +
1091 + return count;
1092 +}
1093 +
1094 +/*
1095 + * Put one packet in ring for transmit.
1096 + * A single packet can generate multiple list elements, and
1097 + * the number of ring elements will probably be less than the number
1098 + * of list elements used.
1099 + *
1100 + * No BH disabling for tx_lock here (like tg3)
1101 + */
1102 +static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1103 +{
1104 + struct sky2_port *sky2 = netdev_priv(dev);
1105 + struct sky2_hw *hw = sky2->hw;
1106 + struct sky2_tx_le *le = NULL;
1107 + struct tx_ring_info *re;
1108 + unsigned i, len;
1109 + dma_addr_t mapping;
1110 + u32 addr64;
1111 + u16 mss;
1112 + u8 ctrl;
1113 +
1114 + if (!spin_trylock(&sky2->tx_lock))
1115 + return NETDEV_TX_LOCKED;
1116 +
1117 + if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1118 + /* There is a known but harmless race with lockless tx
1119 + * and netif_stop_queue.
1120 + */
1121 + if (!netif_queue_stopped(dev)) {
1122 + netif_stop_queue(dev);
1123 + printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1124 + dev->name);
1125 + }
1126 + spin_unlock(&sky2->tx_lock);
1127 +
1128 + return NETDEV_TX_BUSY;
1129 + }
1130 +
1131 + if (unlikely(netif_msg_tx_queued(sky2)))
1132 + printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1133 + dev->name, sky2->tx_prod, skb->len);
1134 +
1135 + len = skb_headlen(skb);
1136 + mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1137 + addr64 = high32(mapping);
1138 +
1139 + re = sky2->tx_ring + sky2->tx_prod;
1140 +
1141 + /* Send high bits if changed or crosses boundary */
1142 + if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1143 + le = get_tx_le(sky2);
1144 + le->tx.addr = cpu_to_le32(addr64);
1145 + le->ctrl = 0;
1146 + le->opcode = OP_ADDR64 | HW_OWNER;
1147 + sky2->tx_addr64 = high32(mapping + len);
1148 + }
1149 +
1150 + /* Check for TCP Segmentation Offload */
1151 + mss = skb_shinfo(skb)->tso_size;
1152 + if (mss != 0) {
1153 + /* just drop the packet if non-linear expansion fails */
1154 + if (skb_header_cloned(skb) &&
1155 + pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
1156 + dev_kfree_skb_any(skb);
1157 + goto out_unlock;
1158 + }
1159 +
1160 + mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1161 + mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1162 + mss += ETH_HLEN;
1163 + }
1164 +
1165 + if (mss != sky2->tx_last_mss) {
1166 + le = get_tx_le(sky2);
1167 + le->tx.tso.size = cpu_to_le16(mss);
1168 + le->tx.tso.rsvd = 0;
1169 + le->opcode = OP_LRGLEN | HW_OWNER;
1170 + le->ctrl = 0;
1171 + sky2->tx_last_mss = mss;
1172 + }
1173 +
1174 + ctrl = 0;
1175 +#ifdef SKY2_VLAN_TAG_USED
1176 + /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1177 + if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1178 + if (!le) {
1179 + le = get_tx_le(sky2);
1180 + le->tx.addr = 0;
1181 + le->opcode = OP_VLAN|HW_OWNER;
1182 + le->ctrl = 0;
1183 + } else
1184 + le->opcode |= OP_VLAN;
1185 + le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1186 + ctrl |= INS_VLAN;
1187 + }
1188 +#endif
1189 +
1190 + /* Handle TCP checksum offload */
1191 + if (skb->ip_summed == CHECKSUM_HW) {
1192 + u16 hdr = skb->h.raw - skb->data;
1193 + u16 offset = hdr + skb->csum;
1194 +
1195 + ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1196 + if (skb->nh.iph->protocol == IPPROTO_UDP)
1197 + ctrl |= UDPTCP;
1198 +
1199 + le = get_tx_le(sky2);
1200 + le->tx.csum.start = cpu_to_le16(hdr);
1201 + le->tx.csum.offset = cpu_to_le16(offset);
1202 + le->length = 0; /* initial checksum value */
1203 + le->ctrl = 1; /* one packet */
1204 + le->opcode = OP_TCPLISW | HW_OWNER;
1205 + }
1206 +
1207 + le = get_tx_le(sky2);
1208 + le->tx.addr = cpu_to_le32((u32) mapping);
1209 + le->length = cpu_to_le16(len);
1210 + le->ctrl = ctrl;
1211 + le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1212 +
1213 + /* Record the transmit mapping info */
1214 + re->skb = skb;
1215 + pci_unmap_addr_set(re, mapaddr, mapping);
1216 +
1217 + for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1218 + skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1219 + struct tx_ring_info *fre;
1220 +
1221 + mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1222 + frag->size, PCI_DMA_TODEVICE);
1223 + addr64 = (mapping >> 16) >> 16;
1224 + if (addr64 != sky2->tx_addr64) {
1225 + le = get_tx_le(sky2);
1226 + le->tx.addr = cpu_to_le32(addr64);
1227 + le->ctrl = 0;
1228 + le->opcode = OP_ADDR64 | HW_OWNER;
1229 + sky2->tx_addr64 = addr64;
1230 + }
1231 +
1232 + le = get_tx_le(sky2);
1233 + le->tx.addr = cpu_to_le32((u32) mapping);
1234 + le->length = cpu_to_le16(frag->size);
1235 + le->ctrl = ctrl;
1236 + le->opcode = OP_BUFFER | HW_OWNER;
1237 +
1238 + fre = sky2->tx_ring
1239 + + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
1240 + pci_unmap_addr_set(fre, mapaddr, mapping);
1241 + }
1242 +
1243 + re->idx = sky2->tx_prod;
1244 + le->ctrl |= EOP;
1245 +
1246 + sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
1247 + &sky2->tx_last_put, TX_RING_SIZE);
1248 +
1249 + if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1250 + netif_stop_queue(dev);
1251 +
1252 +out_unlock:
1253 + mmiowb();
1254 + spin_unlock(&sky2->tx_lock);
1255 +
1256 + dev->trans_start = jiffies;
1257 + return NETDEV_TX_OK;
1258 +}
1259 +
1260 +/*
1261 + * Free ring elements from starting at tx_cons until "done"
1262 + *
1263 + * NB: the hardware will tell us about partial completion of multi-part
1264 + * buffers; these are deferred until completion.
1265 + */
1266 +static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1267 +{
1268 + struct net_device *dev = sky2->netdev;
1269 + struct pci_dev *pdev = sky2->hw->pdev;
1270 + u16 nxt, put;
1271 + unsigned i;
1272 +
1273 + BUG_ON(done >= TX_RING_SIZE);
1274 +
1275 + if (unlikely(netif_msg_tx_done(sky2)))
1276 + printk(KERN_DEBUG "%s: tx done, up to %u\n",
1277 + dev->name, done);
1278 +
1279 + for (put = sky2->tx_cons; put != done; put = nxt) {
1280 + struct tx_ring_info *re = sky2->tx_ring + put;
1281 + struct sk_buff *skb = re->skb;
1282 +
1283 + nxt = re->idx;
1284 + BUG_ON(nxt >= TX_RING_SIZE);
1285 + prefetch(sky2->tx_ring + nxt);
1286 +
1287 + /* Check for partial status */
1288 + if (tx_dist(put, done) < tx_dist(put, nxt))
1289 + break;
1290 +
1291 + skb = re->skb;
1292 + pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1293 + skb_headlen(skb), PCI_DMA_TODEVICE);
1294 +
1295 + for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1296 + struct tx_ring_info *fre;
1297 + fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE;
1298 + pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
1299 + skb_shinfo(skb)->frags[i].size,
1300 + PCI_DMA_TODEVICE);
1301 + }
1302 +
1303 + dev_kfree_skb_any(skb);
1304 + }
1305 +
1306 + spin_lock(&sky2->tx_lock);
1307 + sky2->tx_cons = put;
1308 + if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
1309 + netif_wake_queue(dev);
1310 + spin_unlock(&sky2->tx_lock);
1311 +}
1312 +
1313 +/* Cleanup all untransmitted buffers, assume transmitter not running */
1314 +static void sky2_tx_clean(struct sky2_port *sky2)
1315 +{
1316 + sky2_tx_complete(sky2, sky2->tx_prod);
1317 +}
1318 +
1319 +/* Network shutdown */
1320 +static int sky2_down(struct net_device *dev)
1321 +{
1322 + struct sky2_port *sky2 = netdev_priv(dev);
1323 + struct sky2_hw *hw = sky2->hw;
1324 + unsigned port = sky2->port;
1325 + u16 ctrl;
1326 +
1327 + /* Never really got started! */
1328 + if (!sky2->tx_le)
1329 + return 0;
1330 +
1331 + if (netif_msg_ifdown(sky2))
1332 + printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1333 +
1334 + /* Stop more packets from being queued */
1335 + netif_stop_queue(dev);
1336 +
1337 + /* Disable port IRQ */
1338 + local_irq_disable();
1339 + hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1340 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
1341 + local_irq_enable();
1342 +
1343 + flush_scheduled_work();
1344 +
1345 + sky2_phy_reset(hw, port);
1346 +
1347 + /* Stop transmitter */
1348 + sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1349 + sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1350 +
1351 + sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1352 + RB_RST_SET | RB_DIS_OP_MD);
1353 +
1354 + ctrl = gma_read16(hw, port, GM_GP_CTRL);
1355 + ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1356 + gma_write16(hw, port, GM_GP_CTRL, ctrl);
1357 +
1358 + sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1359 +
1360 + /* Workaround shared GMAC reset */
1361 + if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1362 + && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1363 + sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1364 +
1365 + /* Disable Force Sync bit and Enable Alloc bit */
1366 + sky2_write8(hw, SK_REG(port, TXA_CTRL),
1367 + TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1368 +
1369 + /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1370 + sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1371 + sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1372 +
1373 + /* Reset the PCI FIFO of the async Tx queue */
1374 + sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1375 + BMU_RST_SET | BMU_FIFO_RST);
1376 +
1377 + /* Reset the Tx prefetch units */
1378 + sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1379 + PREF_UNIT_RST_SET);
1380 +
1381 + sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1382 +
1383 + sky2_rx_stop(sky2);
1384 +
1385 + sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1386 + sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1387 +
1388 + /* turn off LED's */
1389 + sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1390 +
1391 + synchronize_irq(hw->pdev->irq);
1392 +
1393 + sky2_tx_clean(sky2);
1394 + sky2_rx_clean(sky2);
1395 +
1396 + pci_free_consistent(hw->pdev, RX_LE_BYTES,
1397 + sky2->rx_le, sky2->rx_le_map);
1398 + kfree(sky2->rx_ring);
1399 +
1400 + pci_free_consistent(hw->pdev,
1401 + TX_RING_SIZE * sizeof(struct sky2_tx_le),
1402 + sky2->tx_le, sky2->tx_le_map);
1403 + kfree(sky2->tx_ring);
1404 +
1405 + sky2->tx_le = NULL;
1406 + sky2->rx_le = NULL;
1407 +
1408 + sky2->rx_ring = NULL;
1409 + sky2->tx_ring = NULL;
1410 +
1411 + return 0;
1412 +}
1413 +
1414 +static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1415 +{
1416 + if (!hw->copper)
1417 + return SPEED_1000;
1418 +
1419 + if (hw->chip_id == CHIP_ID_YUKON_FE)
1420 + return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1421 +
1422 + switch (aux & PHY_M_PS_SPEED_MSK) {
1423 + case PHY_M_PS_SPEED_1000:
1424 + return SPEED_1000;
1425 + case PHY_M_PS_SPEED_100:
1426 + return SPEED_100;
1427 + default:
1428 + return SPEED_10;
1429 + }
1430 +}
1431 +
1432 +static void sky2_link_up(struct sky2_port *sky2)
1433 +{
1434 + struct sky2_hw *hw = sky2->hw;
1435 + unsigned port = sky2->port;
1436 + u16 reg;
1437 +
1438 + /* Enable Transmit FIFO Underrun */
1439 + sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1440 +
1441 + reg = gma_read16(hw, port, GM_GP_CTRL);
1442 + if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1443 + reg |= GM_GPCR_DUP_FULL;
1444 +
1445 + /* enable Rx/Tx */
1446 + reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1447 + gma_write16(hw, port, GM_GP_CTRL, reg);
1448 + gma_read16(hw, port, GM_GP_CTRL);
1449 +
1450 + gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1451 +
1452 + netif_carrier_on(sky2->netdev);
1453 + netif_wake_queue(sky2->netdev);
1454 +
1455 + /* Turn on link LED */
1456 + sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1457 + LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1458 +
1459 + if (hw->chip_id == CHIP_ID_YUKON_XL) {
1460 + u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1461 +
1462 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1463 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1464 + PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1465 + SPEED_10 ? 7 : 0) |
1466 + PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1467 + SPEED_100 ? 7 : 0) |
1468 + PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1469 + SPEED_1000 ? 7 : 0));
1470 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1471 + }
1472 +
1473 + if (netif_msg_link(sky2))
1474 + printk(KERN_INFO PFX
1475 + "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1476 + sky2->netdev->name, sky2->speed,
1477 + sky2->duplex == DUPLEX_FULL ? "full" : "half",
1478 + (sky2->tx_pause && sky2->rx_pause) ? "both" :
1479 + sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1480 +}
1481 +
1482 +static void sky2_link_down(struct sky2_port *sky2)
1483 +{
1484 + struct sky2_hw *hw = sky2->hw;
1485 + unsigned port = sky2->port;
1486 + u16 reg;
1487 +
1488 + gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1489 +
1490 + reg = gma_read16(hw, port, GM_GP_CTRL);
1491 + reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1492 + gma_write16(hw, port, GM_GP_CTRL, reg);
1493 + gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1494 +
1495 + if (sky2->rx_pause && !sky2->tx_pause) {
1496 + /* restore Asymmetric Pause bit */
1497 + gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1498 + gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1499 + | PHY_M_AN_ASP);
1500 + }
1501 +
1502 + netif_carrier_off(sky2->netdev);
1503 + netif_stop_queue(sky2->netdev);
1504 +
1505 + /* Turn on link LED */
1506 + sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1507 +
1508 + if (netif_msg_link(sky2))
1509 + printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1510 + sky2_phy_init(hw, port);
1511 +}
1512 +
1513 +static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1514 +{
1515 + struct sky2_hw *hw = sky2->hw;
1516 + unsigned port = sky2->port;
1517 + u16 lpa;
1518 +
1519 + lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1520 +
1521 + if (lpa & PHY_M_AN_RF) {
1522 + printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1523 + return -1;
1524 + }
1525 +
1526 + if (hw->chip_id != CHIP_ID_YUKON_FE &&
1527 + gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1528 + printk(KERN_ERR PFX "%s: master/slave fault",
1529 + sky2->netdev->name);
1530 + return -1;
1531 + }
1532 +
1533 + if (!(aux & PHY_M_PS_SPDUP_RES)) {
1534 + printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1535 + sky2->netdev->name);
1536 + return -1;
1537 + }
1538 +
1539 + sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1540 +
1541 + sky2->speed = sky2_phy_speed(hw, aux);
1542 +
1543 + /* Pause bits are offset (9..8) */
1544 + if (hw->chip_id == CHIP_ID_YUKON_XL)
1545 + aux >>= 6;
1546 +
1547 + sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1548 + sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1549 +
1550 + if ((sky2->tx_pause || sky2->rx_pause)
1551 + && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1552 + sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1553 + else
1554 + sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1555 +
1556 + return 0;
1557 +}
1558 +
1559 +/*
1560 + * Interrupt from PHY are handled outside of interrupt context
1561 + * because accessing phy registers requires spin wait which might
1562 + * cause excess interrupt latency.
1563 + */
1564 +static void sky2_phy_task(void *arg)
1565 +{
1566 + struct sky2_port *sky2 = arg;
1567 + struct sky2_hw *hw = sky2->hw;
1568 + u16 istatus, phystat;
1569 +
1570 + down(&sky2->phy_sema);
1571 + istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1572 + phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
1573 +
1574 + if (netif_msg_intr(sky2))
1575 + printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1576 + sky2->netdev->name, istatus, phystat);
1577 +
1578 + if (istatus & PHY_M_IS_AN_COMPL) {
1579 + if (sky2_autoneg_done(sky2, phystat) == 0)
1580 + sky2_link_up(sky2);
1581 + goto out;
1582 + }
1583 +
1584 + if (istatus & PHY_M_IS_LSP_CHANGE)
1585 + sky2->speed = sky2_phy_speed(hw, phystat);
1586 +
1587 + if (istatus & PHY_M_IS_DUP_CHANGE)
1588 + sky2->duplex =
1589 + (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1590 +
1591 + if (istatus & PHY_M_IS_LST_CHANGE) {
1592 + if (phystat & PHY_M_PS_LINK_UP)
1593 + sky2_link_up(sky2);
1594 + else
1595 + sky2_link_down(sky2);
1596 + }
1597 +out:
1598 + up(&sky2->phy_sema);
1599 +
1600 + local_irq_disable();
1601 + hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
1602 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
1603 + local_irq_enable();
1604 +}
1605 +
1606 +static void sky2_tx_timeout(struct net_device *dev)
1607 +{
1608 + struct sky2_port *sky2 = netdev_priv(dev);
1609 + struct sky2_hw *hw = sky2->hw;
1610 + unsigned txq = txqaddr[sky2->port];
1611 +
1612 + if (netif_msg_timer(sky2))
1613 + printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1614 +
1615 + netif_stop_queue(dev);
1616 +
1617 + sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1618 + sky2_read32(hw, Q_ADDR(txq, Q_CSR));
1619 +
1620 + sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1621 +
1622 + sky2_tx_clean(sky2);
1623 +
1624 + sky2_qset(hw, txq);
1625 + sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1626 +
1627 + netif_wake_queue(dev);
1628 +}
1629 +
1630 +
1631 +#define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
1632 +/* Want receive buffer size to be multiple of 64 bits, and incl room for vlan */
1633 +static inline unsigned sky2_buf_size(int mtu)
1634 +{
1635 + return roundup(mtu + ETH_HLEN + 4, 8);
1636 +}
1637 +
1638 +static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1639 +{
1640 + struct sky2_port *sky2 = netdev_priv(dev);
1641 + struct sky2_hw *hw = sky2->hw;
1642 + int err;
1643 + u16 ctl, mode;
1644 +
1645 + if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1646 + return -EINVAL;
1647 +
1648 + if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1649 + return -EINVAL;
1650 +
1651 + if (!netif_running(dev)) {
1652 + dev->mtu = new_mtu;
1653 + return 0;
1654 + }
1655 +
1656 + sky2_write32(hw, B0_IMSK, 0);
1657 +
1658 + dev->trans_start = jiffies; /* prevent tx timeout */
1659 + netif_stop_queue(dev);
1660 + netif_poll_disable(hw->dev[0]);
1661 +
1662 + ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1663 + gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1664 + sky2_rx_stop(sky2);
1665 + sky2_rx_clean(sky2);
1666 +
1667 + dev->mtu = new_mtu;
1668 + sky2->rx_bufsize = sky2_buf_size(new_mtu);
1669 + mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1670 + GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1671 +
1672 + if (dev->mtu > ETH_DATA_LEN)
1673 + mode |= GM_SMOD_JUMBO_ENA;
1674 +
1675 + gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1676 +
1677 + sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1678 +
1679 + err = sky2_rx_start(sky2);
1680 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
1681 +
1682 + if (err)
1683 + dev_close(dev);
1684 + else {
1685 + gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1686 +
1687 + netif_poll_enable(hw->dev[0]);
1688 + netif_wake_queue(dev);
1689 + }
1690 +
1691 + return err;
1692 +}
1693 +
1694 +/*
1695 + * Receive one packet.
1696 + * For small packets or errors, just reuse existing skb.
1697 + * For larger packets, get new buffer.
1698 + */
1699 +static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1700 + u16 length, u32 status)
1701 +{
1702 + struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1703 + struct sk_buff *skb = NULL;
1704 +
1705 + if (unlikely(netif_msg_rx_status(sky2)))
1706 + printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1707 + sky2->netdev->name, sky2->rx_next, status, length);
1708 +
1709 + sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1710 + prefetch(sky2->rx_ring + sky2->rx_next);
1711 +
1712 + if (status & GMR_FS_ANY_ERR)
1713 + goto error;
1714 +
1715 + if (!(status & GMR_FS_RX_OK))
1716 + goto resubmit;
1717 +
1718 + if ((status >> 16) != length || length > sky2->rx_bufsize)
1719 + goto oversize;
1720 +
1721 + if (length < copybreak) {
1722 + skb = alloc_skb(length + 2, GFP_ATOMIC);
1723 + if (!skb)
1724 + goto resubmit;
1725 +
1726 + skb_reserve(skb, 2);
1727 + pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1728 + length, PCI_DMA_FROMDEVICE);
1729 + memcpy(skb->data, re->skb->data, length);
1730 + skb->ip_summed = re->skb->ip_summed;
1731 + skb->csum = re->skb->csum;
1732 + pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1733 + length, PCI_DMA_FROMDEVICE);
1734 + } else {
1735 + struct sk_buff *nskb;
1736 +
1737 + nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
1738 + if (!nskb)
1739 + goto resubmit;
1740 +
1741 + skb = re->skb;
1742 + re->skb = nskb;
1743 + pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1744 + sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1745 + prefetch(skb->data);
1746 +
1747 + re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1748 + sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1749 + }
1750 +
1751 + skb_put(skb, length);
1752 +resubmit:
1753 + re->skb->ip_summed = CHECKSUM_NONE;
1754 + sky2_rx_add(sky2, re->mapaddr);
1755 +
1756 + /* Tell receiver about new buffers. */
1757 + sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
1758 + &sky2->rx_last_put, RX_LE_SIZE);
1759 +
1760 + return skb;
1761 +
1762 +oversize:
1763 + ++sky2->net_stats.rx_over_errors;
1764 + goto resubmit;
1765 +
1766 +error:
1767 + ++sky2->net_stats.rx_errors;
1768 +
1769 + if (netif_msg_rx_err(sky2))
1770 + printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1771 + sky2->netdev->name, status, length);
1772 +
1773 + if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1774 + sky2->net_stats.rx_length_errors++;
1775 + if (status & GMR_FS_FRAGMENT)
1776 + sky2->net_stats.rx_frame_errors++;
1777 + if (status & GMR_FS_CRC_ERR)
1778 + sky2->net_stats.rx_crc_errors++;
1779 + if (status & GMR_FS_RX_FF_OV)
1780 + sky2->net_stats.rx_fifo_errors++;
1781 +
1782 + goto resubmit;
1783 +}
1784 +
1785 +/*
1786 + * Check for transmit complete
1787 + */
1788 +#define TX_NO_STATUS 0xffff
1789 +
1790 +static inline void sky2_tx_check(struct sky2_hw *hw, int port, u16 last)
1791 +{
1792 + if (last != TX_NO_STATUS) {
1793 + struct net_device *dev = hw->dev[port];
1794 + if (dev && netif_running(dev)) {
1795 + struct sky2_port *sky2 = netdev_priv(dev);
1796 + sky2_tx_complete(sky2, last);
1797 + }
1798 + }
1799 +}
1800 +
1801 +/*
1802 + * Both ports share the same status interrupt, therefore there is only
1803 + * one poll routine.
1804 + */
1805 +static int sky2_poll(struct net_device *dev0, int *budget)
1806 +{
1807 + struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1808 + unsigned int to_do = min(dev0->quota, *budget);
1809 + unsigned int work_done = 0;
1810 + u16 hwidx;
1811 + u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS };
1812 +
1813 + hwidx = sky2_read16(hw, STAT_PUT_IDX);
1814 + BUG_ON(hwidx >= STATUS_RING_SIZE);
1815 + rmb();
1816 +
1817 + while (hwidx != hw->st_idx) {
1818 + struct sky2_status_le *le = hw->st_le + hw->st_idx;
1819 + struct net_device *dev;
1820 + struct sky2_port *sky2;
1821 + struct sk_buff *skb;
1822 + u32 status;
1823 + u16 length;
1824 + u8 op;
1825 +
1826 + le = hw->st_le + hw->st_idx;
1827 + hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
1828 + prefetch(hw->st_le + hw->st_idx);
1829 +
1830 + BUG_ON(le->link >= 2);
1831 + dev = hw->dev[le->link];
1832 + if (dev == NULL || !netif_running(dev))
1833 + continue;
1834 +
1835 + sky2 = netdev_priv(dev);
1836 + status = le32_to_cpu(le->status);
1837 + length = le16_to_cpu(le->length);
1838 + op = le->opcode & ~HW_OWNER;
1839 + le->opcode = 0;
1840 +
1841 + switch (op) {
1842 + case OP_RXSTAT:
1843 + skb = sky2_receive(sky2, length, status);
1844 + if (!skb)
1845 + break;
1846 +
1847 + skb->dev = dev;
1848 + skb->protocol = eth_type_trans(skb, dev);
1849 + dev->last_rx = jiffies;
1850 +
1851 +#ifdef SKY2_VLAN_TAG_USED
1852 + if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1853 + vlan_hwaccel_receive_skb(skb,
1854 + sky2->vlgrp,
1855 + be16_to_cpu(sky2->rx_tag));
1856 + } else
1857 +#endif
1858 + netif_receive_skb(skb);
1859 +
1860 + if (++work_done >= to_do)
1861 + goto exit_loop;
1862 + break;
1863 +
1864 +#ifdef SKY2_VLAN_TAG_USED
1865 + case OP_RXVLAN:
1866 + sky2->rx_tag = length;
1867 + break;
1868 +
1869 + case OP_RXCHKSVLAN:
1870 + sky2->rx_tag = length;
1871 + /* fall through */
1872 +#endif
1873 + case OP_RXCHKS:
1874 + skb = sky2->rx_ring[sky2->rx_next].skb;
1875 + skb->ip_summed = CHECKSUM_HW;
1876 + skb->csum = le16_to_cpu(status);
1877 + break;
1878 +
1879 + case OP_TXINDEXLE:
1880 + /* TX index reports status for both ports */
1881 + tx_done[0] = status & 0xffff;
1882 + tx_done[1] = ((status >> 24) & 0xff)
1883 + | (u16)(length & 0xf) << 8;
1884 + break;
1885 +
1886 + default:
1887 + if (net_ratelimit())
1888 + printk(KERN_WARNING PFX
1889 + "unknown status opcode 0x%x\n", op);
1890 + break;
1891 + }
1892 + }
1893 +
1894 +exit_loop:
1895 + sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1896 + mmiowb();
1897 +
1898 + sky2_tx_check(hw, 0, tx_done[0]);
1899 + sky2_tx_check(hw, 1, tx_done[1]);
1900 +
1901 + if (sky2_read16(hw, STAT_PUT_IDX) == hw->st_idx) {
1902 + /* need to restart TX timer */
1903 + if (is_ec_a1(hw)) {
1904 + sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1905 + sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1906 + }
1907 +
1908 + netif_rx_complete(dev0);
1909 + hw->intr_mask |= Y2_IS_STAT_BMU;
1910 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
1911 + mmiowb();
1912 + return 0;
1913 + } else {
1914 + *budget -= work_done;
1915 + dev0->quota -= work_done;
1916 + return 1;
1917 + }
1918 +}
1919 +
1920 +static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1921 +{
1922 + struct net_device *dev = hw->dev[port];
1923 +
1924 + printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1925 + dev->name, status);
1926 +
1927 + if (status & Y2_IS_PAR_RD1) {
1928 + printk(KERN_ERR PFX "%s: ram data read parity error\n",
1929 + dev->name);
1930 + /* Clear IRQ */
1931 + sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1932 + }
1933 +
1934 + if (status & Y2_IS_PAR_WR1) {
1935 + printk(KERN_ERR PFX "%s: ram data write parity error\n",
1936 + dev->name);
1937 +
1938 + sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1939 + }
1940 +
1941 + if (status & Y2_IS_PAR_MAC1) {
1942 + printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
1943 + sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1944 + }
1945 +
1946 + if (status & Y2_IS_PAR_RX1) {
1947 + printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
1948 + sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1949 + }
1950 +
1951 + if (status & Y2_IS_TCP_TXA1) {
1952 + printk(KERN_ERR PFX "%s: TCP segmentation error\n", dev->name);
1953 + sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1954 + }
1955 +}
1956 +
1957 +static void sky2_hw_intr(struct sky2_hw *hw)
1958 +{
1959 + u32 status = sky2_read32(hw, B0_HWE_ISRC);
1960 +
1961 + if (status & Y2_IS_TIST_OV)
1962 + sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1963 +
1964 + if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
1965 + u16 pci_err;
1966 +
1967 + pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
1968 + printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
1969 + pci_name(hw->pdev), pci_err);
1970 +
1971 + sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1972 + pci_write_config_word(hw->pdev, PCI_STATUS,
1973 + pci_err | PCI_STATUS_ERROR_BITS);
1974 + sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1975 + }
1976 +
1977 + if (status & Y2_IS_PCI_EXP) {
1978 + /* PCI-Express uncorrectable Error occurred */
1979 + u32 pex_err;
1980 +
1981 + pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
1982 +
1983 + printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
1984 + pci_name(hw->pdev), pex_err);
1985 +
1986 + /* clear the interrupt */
1987 + sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1988 + pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1989 + 0xffffffffUL);
1990 + sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1991 +
1992 + if (pex_err & PEX_FATAL_ERRORS) {
1993 + u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
1994 + hwmsk &= ~Y2_IS_PCI_EXP;
1995 + sky2_write32(hw, B0_HWE_IMSK, hwmsk);
1996 + }
1997 + }
1998 +
1999 + if (status & Y2_HWE_L1_MASK)
2000 + sky2_hw_error(hw, 0, status);
2001 + status >>= 8;
2002 + if (status & Y2_HWE_L1_MASK)
2003 + sky2_hw_error(hw, 1, status);
2004 +}
2005 +
2006 +static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2007 +{
2008 + struct net_device *dev = hw->dev[port];
2009 + struct sky2_port *sky2 = netdev_priv(dev);
2010 + u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2011 +
2012 + if (netif_msg_intr(sky2))
2013 + printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2014 + dev->name, status);
2015 +
2016 + if (status & GM_IS_RX_FF_OR) {
2017 + ++sky2->net_stats.rx_fifo_errors;
2018 + sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2019 + }
2020 +
2021 + if (status & GM_IS_TX_FF_UR) {
2022 + ++sky2->net_stats.tx_fifo_errors;
2023 + sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2024 + }
2025 +}
2026 +
2027 +static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2028 +{
2029 + struct net_device *dev = hw->dev[port];
2030 + struct sky2_port *sky2 = netdev_priv(dev);
2031 +
2032 + hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
2033 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
2034 + schedule_work(&sky2->phy_task);
2035 +}
2036 +
2037 +static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2038 +{
2039 + struct sky2_hw *hw = dev_id;
2040 + struct net_device *dev0 = hw->dev[0];
2041 + u32 status;
2042 +
2043 + status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2044 + if (status == 0 || status == ~0)
2045 + return IRQ_NONE;
2046 +
2047 + if (status & Y2_IS_HW_ERR)
2048 + sky2_hw_intr(hw);
2049 +
2050 + /* Do NAPI for Rx and Tx status */
2051 + if (status & Y2_IS_STAT_BMU) {
2052 + hw->intr_mask &= ~Y2_IS_STAT_BMU;
2053 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
2054 +
2055 + if (likely(__netif_rx_schedule_prep(dev0))) {
2056 + prefetch(&hw->st_le[hw->st_idx]);
2057 + __netif_rx_schedule(dev0);
2058 + }
2059 + }
2060 +
2061 + if (status & Y2_IS_IRQ_PHY1)
2062 + sky2_phy_intr(hw, 0);
2063 +
2064 + if (status & Y2_IS_IRQ_PHY2)
2065 + sky2_phy_intr(hw, 1);
2066 +
2067 + if (status & Y2_IS_IRQ_MAC1)
2068 + sky2_mac_intr(hw, 0);
2069 +
2070 + if (status & Y2_IS_IRQ_MAC2)
2071 + sky2_mac_intr(hw, 1);
2072 +
2073 + sky2_write32(hw, B0_Y2_SP_ICR, 2);
2074 +
2075 + sky2_read32(hw, B0_IMSK);
2076 +
2077 + return IRQ_HANDLED;
2078 +}
2079 +
2080 +#ifdef CONFIG_NET_POLL_CONTROLLER
2081 +static void sky2_netpoll(struct net_device *dev)
2082 +{
2083 + struct sky2_port *sky2 = netdev_priv(dev);
2084 +
2085 + sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
2086 +}
2087 +#endif
2088 +
2089 +/* Chip internal frequency for clock calculations */
2090 +static inline u32 sky2_mhz(const struct sky2_hw *hw)
2091 +{
2092 + switch (hw->chip_id) {
2093 + case CHIP_ID_YUKON_EC:
2094 + case CHIP_ID_YUKON_EC_U:
2095 + return 125; /* 125 Mhz */
2096 + case CHIP_ID_YUKON_FE:
2097 + return 100; /* 100 Mhz */
2098 + default: /* YUKON_XL */
2099 + return 156; /* 156 Mhz */
2100 + }
2101 +}
2102 +
2103 +static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2104 +{
2105 + return sky2_mhz(hw) * us;
2106 +}
2107 +
2108 +static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2109 +{
2110 + return clk / sky2_mhz(hw);
2111 +}
2112 +
2113 +
2114 +static int sky2_reset(struct sky2_hw *hw)
2115 +{
2116 + u32 ctst;
2117 + u16 status;
2118 + u8 t8, pmd_type;
2119 + int i;
2120 +
2121 + ctst = sky2_read32(hw, B0_CTST);
2122 +
2123 + sky2_write8(hw, B0_CTST, CS_RST_CLR);
2124 + hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2125 + if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2126 + printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2127 + pci_name(hw->pdev), hw->chip_id);
2128 + return -EOPNOTSUPP;
2129 + }
2130 +
2131 + /* ring for status responses */
2132 + hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
2133 + &hw->st_dma);
2134 + if (!hw->st_le)
2135 + return -ENOMEM;
2136 +
2137 + /* disable ASF */
2138 + if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2139 + sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2140 + sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2141 + }
2142 +
2143 + /* do a SW reset */
2144 + sky2_write8(hw, B0_CTST, CS_RST_SET);
2145 + sky2_write8(hw, B0_CTST, CS_RST_CLR);
2146 +
2147 + /* clear PCI errors, if any */
2148 + pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2149 + sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2150 + pci_write_config_word(hw->pdev, PCI_STATUS,
2151 + status | PCI_STATUS_ERROR_BITS);
2152 +
2153 + sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2154 +
2155 + /* clear any PEX errors */
2156 + if (is_pciex(hw)) {
2157 + u16 lstat;
2158 + pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
2159 + 0xffffffffUL);
2160 + pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat);
2161 + }
2162 +
2163 + pmd_type = sky2_read8(hw, B2_PMD_TYP);
2164 + hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2165 +
2166 + hw->ports = 1;
2167 + t8 = sky2_read8(hw, B2_Y2_HW_RES);
2168 + if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2169 + if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2170 + ++hw->ports;
2171 + }
2172 + hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2173 +
2174 + sky2_set_power_state(hw, PCI_D0);
2175 +
2176 + for (i = 0; i < hw->ports; i++) {
2177 + sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2178 + sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2179 + }
2180 +
2181 + sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2182 +
2183 + /* Clear I2C IRQ noise */
2184 + sky2_write32(hw, B2_I2C_IRQ, 1);
2185 +
2186 + /* turn off hardware timer (unused) */
2187 + sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2188 + sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2189 +
2190 + sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2191 +
2192 + /* Turn off descriptor polling */
2193 + sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2194 +
2195 + /* Turn off receive timestamp */
2196 + sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2197 + sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2198 +
2199 + /* enable the Tx Arbiters */
2200 + for (i = 0; i < hw->ports; i++)
2201 + sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2202 +
2203 + /* Initialize ram interface */
2204 + for (i = 0; i < hw->ports; i++) {
2205 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2206 +
2207 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2208 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2209 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2210 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2211 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2212 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2213 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2214 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2215 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2216 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2217 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2218 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2219 + }
2220 +
2221 + sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2222 +
2223 + for (i = 0; i < hw->ports; i++)
2224 + sky2_phy_reset(hw, i);
2225 +
2226 + memset(hw->st_le, 0, STATUS_LE_BYTES);
2227 + hw->st_idx = 0;
2228 +
2229 + sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2230 + sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2231 +
2232 + sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2233 + sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2234 +
2235 + /* Set the list last index */
2236 + sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2237 +
2238 + /* These status setup values are copied from SysKonnect's driver */
2239 + if (is_ec_a1(hw)) {
2240 + /* WA for dev. #4.3 */
2241 + sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
2242 +
2243 + /* set Status-FIFO watermark */
2244 + sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
2245 +
2246 + /* set Status-FIFO ISR watermark */
2247 + sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
2248 + sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 10000));
2249 + } else {
2250 + sky2_write16(hw, STAT_TX_IDX_TH, 10);
2251 + sky2_write8(hw, STAT_FIFO_WM, 16);
2252 +
2253 + /* set Status-FIFO ISR watermark */
2254 + if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2255 + sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2256 + else
2257 + sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2258 +
2259 + sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2260 + sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2261 + sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2262 + }
2263 +
2264 + /* enable status unit */
2265 + sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2266 +
2267 + sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2268 + sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2269 + sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2270 +
2271 + return 0;
2272 +}
2273 +
2274 +static inline u32 sky2_supported_modes(const struct sky2_hw *hw)
2275 +{
2276 + u32 modes;
2277 + if (hw->copper) {
2278 + modes = SUPPORTED_10baseT_Half
2279 + | SUPPORTED_10baseT_Full
2280 + | SUPPORTED_100baseT_Half
2281 + | SUPPORTED_100baseT_Full
2282 + | SUPPORTED_Autoneg | SUPPORTED_TP;
2283 +
2284 + if (hw->chip_id != CHIP_ID_YUKON_FE)
2285 + modes |= SUPPORTED_1000baseT_Half
2286 + | SUPPORTED_1000baseT_Full;
2287 + } else
2288 + modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
2289 + | SUPPORTED_Autoneg;
2290 + return modes;
2291 +}
2292 +
2293 +static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2294 +{
2295 + struct sky2_port *sky2 = netdev_priv(dev);
2296 + struct sky2_hw *hw = sky2->hw;
2297 +
2298 + ecmd->transceiver = XCVR_INTERNAL;
2299 + ecmd->supported = sky2_supported_modes(hw);
2300 + ecmd->phy_address = PHY_ADDR_MARV;
2301 + if (hw->copper) {
2302 + ecmd->supported = SUPPORTED_10baseT_Half
2303 + | SUPPORTED_10baseT_Full
2304 + | SUPPORTED_100baseT_Half
2305 + | SUPPORTED_100baseT_Full
2306 + | SUPPORTED_1000baseT_Half
2307 + | SUPPORTED_1000baseT_Full
2308 + | SUPPORTED_Autoneg | SUPPORTED_TP;
2309 + ecmd->port = PORT_TP;
2310 + } else
2311 + ecmd->port = PORT_FIBRE;
2312 +
2313 + ecmd->advertising = sky2->advertising;
2314 + ecmd->autoneg = sky2->autoneg;
2315 + ecmd->speed = sky2->speed;
2316 + ecmd->duplex = sky2->duplex;
2317 + return 0;
2318 +}
2319 +
2320 +static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2321 +{
2322 + struct sky2_port *sky2 = netdev_priv(dev);
2323 + const struct sky2_hw *hw = sky2->hw;
2324 + u32 supported = sky2_supported_modes(hw);
2325 +
2326 + if (ecmd->autoneg == AUTONEG_ENABLE) {
2327 + ecmd->advertising = supported;
2328 + sky2->duplex = -1;
2329 + sky2->speed = -1;
2330 + } else {
2331 + u32 setting;
2332 +
2333 + switch (ecmd->speed) {
2334 + case SPEED_1000:
2335 + if (ecmd->duplex == DUPLEX_FULL)
2336 + setting = SUPPORTED_1000baseT_Full;
2337 + else if (ecmd->duplex == DUPLEX_HALF)
2338 + setting = SUPPORTED_1000baseT_Half;
2339 + else
2340 + return -EINVAL;
2341 + break;
2342 + case SPEED_100:
2343 + if (ecmd->duplex == DUPLEX_FULL)
2344 + setting = SUPPORTED_100baseT_Full;
2345 + else if (ecmd->duplex == DUPLEX_HALF)
2346 + setting = SUPPORTED_100baseT_Half;
2347 + else
2348 + return -EINVAL;
2349 + break;
2350 +
2351 + case SPEED_10:
2352 + if (ecmd->duplex == DUPLEX_FULL)
2353 + setting = SUPPORTED_10baseT_Full;
2354 + else if (ecmd->duplex == DUPLEX_HALF)
2355 + setting = SUPPORTED_10baseT_Half;
2356 + else
2357 + return -EINVAL;
2358 + break;
2359 + default:
2360 + return -EINVAL;
2361 + }
2362 +
2363 + if ((setting & supported) == 0)
2364 + return -EINVAL;
2365 +
2366 + sky2->speed = ecmd->speed;
2367 + sky2->duplex = ecmd->duplex;
2368 + }
2369 +
2370 + sky2->autoneg = ecmd->autoneg;
2371 + sky2->advertising = ecmd->advertising;
2372 +
2373 + if (netif_running(dev))
2374 + sky2_phy_reinit(sky2);
2375 +
2376 + return 0;
2377 +}
2378 +
2379 +static void sky2_get_drvinfo(struct net_device *dev,
2380 + struct ethtool_drvinfo *info)
2381 +{
2382 + struct sky2_port *sky2 = netdev_priv(dev);
2383 +
2384 + strcpy(info->driver, DRV_NAME);
2385 + strcpy(info->version, DRV_VERSION);
2386 + strcpy(info->fw_version, "N/A");
2387 + strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2388 +}
2389 +
2390 +static const struct sky2_stat {
2391 + char name[ETH_GSTRING_LEN];
2392 + u16 offset;
2393 +} sky2_stats[] = {
2394 + { "tx_bytes", GM_TXO_OK_HI },
2395 + { "rx_bytes", GM_RXO_OK_HI },
2396 + { "tx_broadcast", GM_TXF_BC_OK },
2397 + { "rx_broadcast", GM_RXF_BC_OK },
2398 + { "tx_multicast", GM_TXF_MC_OK },
2399 + { "rx_multicast", GM_RXF_MC_OK },
2400 + { "tx_unicast", GM_TXF_UC_OK },
2401 + { "rx_unicast", GM_RXF_UC_OK },
2402 + { "tx_mac_pause", GM_TXF_MPAUSE },
2403 + { "rx_mac_pause", GM_RXF_MPAUSE },
2404 + { "collisions", GM_TXF_SNG_COL },
2405 + { "late_collision",GM_TXF_LAT_COL },
2406 + { "aborted", GM_TXF_ABO_COL },
2407 + { "multi_collisions", GM_TXF_MUL_COL },
2408 + { "fifo_underrun", GM_TXE_FIFO_UR },
2409 + { "fifo_overflow", GM_RXE_FIFO_OV },
2410 + { "rx_toolong", GM_RXF_LNG_ERR },
2411 + { "rx_jabber", GM_RXF_JAB_PKT },
2412 + { "rx_runt", GM_RXE_FRAG },
2413 + { "rx_too_long", GM_RXF_LNG_ERR },
2414 + { "rx_fcs_error", GM_RXF_FCS_ERR },
2415 +};
2416 +
2417 +static u32 sky2_get_rx_csum(struct net_device *dev)
2418 +{
2419 + struct sky2_port *sky2 = netdev_priv(dev);
2420 +
2421 + return sky2->rx_csum;
2422 +}
2423 +
2424 +static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2425 +{
2426 + struct sky2_port *sky2 = netdev_priv(dev);
2427 +
2428 + sky2->rx_csum = data;
2429 +
2430 + sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2431 + data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2432 +
2433 + return 0;
2434 +}
2435 +
2436 +static u32 sky2_get_msglevel(struct net_device *netdev)
2437 +{
2438 + struct sky2_port *sky2 = netdev_priv(netdev);
2439 + return sky2->msg_enable;
2440 +}
2441 +
2442 +static int sky2_nway_reset(struct net_device *dev)
2443 +{
2444 + struct sky2_port *sky2 = netdev_priv(dev);
2445 +
2446 + if (sky2->autoneg != AUTONEG_ENABLE)
2447 + return -EINVAL;
2448 +
2449 + sky2_phy_reinit(sky2);
2450 +
2451 + return 0;
2452 +}
2453 +
2454 +static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2455 +{
2456 + struct sky2_hw *hw = sky2->hw;
2457 + unsigned port = sky2->port;
2458 + int i;
2459 +
2460 + data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2461 + | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2462 + data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2463 + | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2464 +
2465 + for (i = 2; i < count; i++)
2466 + data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2467 +}
2468 +
2469 +static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2470 +{
2471 + struct sky2_port *sky2 = netdev_priv(netdev);
2472 + sky2->msg_enable = value;
2473 +}
2474 +
2475 +static int sky2_get_stats_count(struct net_device *dev)
2476 +{
2477 + return ARRAY_SIZE(sky2_stats);
2478 +}
2479 +
2480 +static void sky2_get_ethtool_stats(struct net_device *dev,
2481 + struct ethtool_stats *stats, u64 * data)
2482 +{
2483 + struct sky2_port *sky2 = netdev_priv(dev);
2484 +
2485 + sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2486 +}
2487 +
2488 +static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2489 +{
2490 + int i;
2491 +
2492 + switch (stringset) {
2493 + case ETH_SS_STATS:
2494 + for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2495 + memcpy(data + i * ETH_GSTRING_LEN,
2496 + sky2_stats[i].name, ETH_GSTRING_LEN);
2497 + break;
2498 + }
2499 +}
2500 +
2501 +/* Use hardware MIB variables for critical path statistics and
2502 + * transmit feedback not reported at interrupt.
2503 + * Other errors are accounted for in interrupt handler.
2504 + */
2505 +static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2506 +{
2507 + struct sky2_port *sky2 = netdev_priv(dev);
2508 + u64 data[13];
2509 +
2510 + sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2511 +
2512 + sky2->net_stats.tx_bytes = data[0];
2513 + sky2->net_stats.rx_bytes = data[1];
2514 + sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2515 + sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2516 + sky2->net_stats.multicast = data[5] + data[7];
2517 + sky2->net_stats.collisions = data[10];
2518 + sky2->net_stats.tx_aborted_errors = data[12];
2519 +
2520 + return &sky2->net_stats;
2521 +}
2522 +
2523 +static int sky2_set_mac_address(struct net_device *dev, void *p)
2524 +{
2525 + struct sky2_port *sky2 = netdev_priv(dev);
2526 + struct sockaddr *addr = p;
2527 +
2528 + if (!is_valid_ether_addr(addr->sa_data))
2529 + return -EADDRNOTAVAIL;
2530 +
2531 + memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2532 + memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8,
2533 + dev->dev_addr, ETH_ALEN);
2534 + memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8,
2535 + dev->dev_addr, ETH_ALEN);
2536 +
2537 + if (netif_running(dev))
2538 + sky2_phy_reinit(sky2);
2539 +
2540 + return 0;
2541 +}
2542 +
2543 +static void sky2_set_multicast(struct net_device *dev)
2544 +{
2545 + struct sky2_port *sky2 = netdev_priv(dev);
2546 + struct sky2_hw *hw = sky2->hw;
2547 + unsigned port = sky2->port;
2548 + struct dev_mc_list *list = dev->mc_list;
2549 + u16 reg;
2550 + u8 filter[8];
2551 +
2552 + memset(filter, 0, sizeof(filter));
2553 +
2554 + reg = gma_read16(hw, port, GM_RX_CTRL);
2555 + reg |= GM_RXCR_UCF_ENA;
2556 +
2557 + if (dev->flags & IFF_PROMISC) /* promiscuous */
2558 + reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2559 + else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2560 + memset(filter, 0xff, sizeof(filter));
2561 + else if (dev->mc_count == 0) /* no multicast */
2562 + reg &= ~GM_RXCR_MCF_ENA;
2563 + else {
2564 + int i;
2565 + reg |= GM_RXCR_MCF_ENA;
2566 +
2567 + for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2568 + u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2569 + filter[bit / 8] |= 1 << (bit % 8);
2570 + }
2571 + }
2572 +
2573 + gma_write16(hw, port, GM_MC_ADDR_H1,
2574 + (u16) filter[0] | ((u16) filter[1] << 8));
2575 + gma_write16(hw, port, GM_MC_ADDR_H2,
2576 + (u16) filter[2] | ((u16) filter[3] << 8));
2577 + gma_write16(hw, port, GM_MC_ADDR_H3,
2578 + (u16) filter[4] | ((u16) filter[5] << 8));
2579 + gma_write16(hw, port, GM_MC_ADDR_H4,
2580 + (u16) filter[6] | ((u16) filter[7] << 8));
2581 +
2582 + gma_write16(hw, port, GM_RX_CTRL, reg);
2583 +}
2584 +
2585 +/* Can have one global because blinking is controlled by
2586 + * ethtool and that is always under RTNL mutex
2587 + */
2588 +static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2589 +{
2590 + u16 pg;
2591 +
2592 + switch (hw->chip_id) {
2593 + case CHIP_ID_YUKON_XL:
2594 + pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2595 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2596 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2597 + on ? (PHY_M_LEDC_LOS_CTRL(1) |
2598 + PHY_M_LEDC_INIT_CTRL(7) |
2599 + PHY_M_LEDC_STA1_CTRL(7) |
2600 + PHY_M_LEDC_STA0_CTRL(7))
2601 + : 0);
2602 +
2603 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2604 + break;
2605 +
2606 + default:
2607 + gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2608 + gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2609 + on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2610 + PHY_M_LED_MO_10(MO_LED_ON) |
2611 + PHY_M_LED_MO_100(MO_LED_ON) |
2612 + PHY_M_LED_MO_1000(MO_LED_ON) |
2613 + PHY_M_LED_MO_RX(MO_LED_ON)
2614 + : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2615 + PHY_M_LED_MO_10(MO_LED_OFF) |
2616 + PHY_M_LED_MO_100(MO_LED_OFF) |
2617 + PHY_M_LED_MO_1000(MO_LED_OFF) |
2618 + PHY_M_LED_MO_RX(MO_LED_OFF));
2619 +
2620 + }
2621 +}
2622 +
2623 +/* blink LED's for finding board */
2624 +static int sky2_phys_id(struct net_device *dev, u32 data)
2625 +{
2626 + struct sky2_port *sky2 = netdev_priv(dev);
2627 + struct sky2_hw *hw = sky2->hw;
2628 + unsigned port = sky2->port;
2629 + u16 ledctrl, ledover = 0;
2630 + long ms;
2631 + int interrupted;
2632 + int onoff = 1;
2633 +
2634 + if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2635 + ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2636 + else
2637 + ms = data * 1000;
2638 +
2639 + /* save initial values */
2640 + down(&sky2->phy_sema);
2641 + if (hw->chip_id == CHIP_ID_YUKON_XL) {
2642 + u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2643 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2644 + ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2645 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2646 + } else {
2647 + ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2648 + ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2649 + }
2650 +
2651 + interrupted = 0;
2652 + while (!interrupted && ms > 0) {
2653 + sky2_led(hw, port, onoff);
2654 + onoff = !onoff;
2655 +
2656 + up(&sky2->phy_sema);
2657 + interrupted = msleep_interruptible(250);
2658 + down(&sky2->phy_sema);
2659 +
2660 + ms -= 250;
2661 + }
2662 +
2663 + /* resume regularly scheduled programming */
2664 + if (hw->chip_id == CHIP_ID_YUKON_XL) {
2665 + u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2666 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2667 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2668 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2669 + } else {
2670 + gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2671 + gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2672 + }
2673 + up(&sky2->phy_sema);
2674 +
2675 + return 0;
2676 +}
2677 +
2678 +static void sky2_get_pauseparam(struct net_device *dev,
2679 + struct ethtool_pauseparam *ecmd)
2680 +{
2681 + struct sky2_port *sky2 = netdev_priv(dev);
2682 +
2683 + ecmd->tx_pause = sky2->tx_pause;
2684 + ecmd->rx_pause = sky2->rx_pause;
2685 + ecmd->autoneg = sky2->autoneg;
2686 +}
2687 +
2688 +static int sky2_set_pauseparam(struct net_device *dev,
2689 + struct ethtool_pauseparam *ecmd)
2690 +{
2691 + struct sky2_port *sky2 = netdev_priv(dev);
2692 + int err = 0;
2693 +
2694 + sky2->autoneg = ecmd->autoneg;
2695 + sky2->tx_pause = ecmd->tx_pause != 0;
2696 + sky2->rx_pause = ecmd->rx_pause != 0;
2697 +
2698 + sky2_phy_reinit(sky2);
2699 +
2700 + return err;
2701 +}
2702 +
2703 +#ifdef CONFIG_PM
2704 +static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2705 +{
2706 + struct sky2_port *sky2 = netdev_priv(dev);
2707 +
2708 + wol->supported = WAKE_MAGIC;
2709 + wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2710 +}
2711 +
2712 +static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2713 +{
2714 + struct sky2_port *sky2 = netdev_priv(dev);
2715 + struct sky2_hw *hw = sky2->hw;
2716 +
2717 + if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2718 + return -EOPNOTSUPP;
2719 +
2720 + sky2->wol = wol->wolopts == WAKE_MAGIC;
2721 +
2722 + if (sky2->wol) {
2723 + memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2724 +
2725 + sky2_write16(hw, WOL_CTRL_STAT,
2726 + WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2727 + WOL_CTL_ENA_MAGIC_PKT_UNIT);
2728 + } else
2729 + sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2730 +
2731 + return 0;
2732 +}
2733 +#endif
2734 +
2735 +static int sky2_get_coalesce(struct net_device *dev,
2736 + struct ethtool_coalesce *ecmd)
2737 +{
2738 + struct sky2_port *sky2 = netdev_priv(dev);
2739 + struct sky2_hw *hw = sky2->hw;
2740 +
2741 + if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2742 + ecmd->tx_coalesce_usecs = 0;
2743 + else {
2744 + u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2745 + ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2746 + }
2747 + ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2748 +
2749 + if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2750 + ecmd->rx_coalesce_usecs = 0;
2751 + else {
2752 + u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2753 + ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2754 + }
2755 + ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2756 +
2757 + if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2758 + ecmd->rx_coalesce_usecs_irq = 0;
2759 + else {
2760 + u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2761 + ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2762 + }
2763 +
2764 + ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2765 +
2766 + return 0;
2767 +}
2768 +
2769 +/* Note: this affect both ports */
2770 +static int sky2_set_coalesce(struct net_device *dev,
2771 + struct ethtool_coalesce *ecmd)
2772 +{
2773 + struct sky2_port *sky2 = netdev_priv(dev);
2774 + struct sky2_hw *hw = sky2->hw;
2775 + const u32 tmin = sky2_clk2us(hw, 1);
2776 + const u32 tmax = 5000;
2777 +
2778 + if (ecmd->tx_coalesce_usecs != 0 &&
2779 + (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax))
2780 + return -EINVAL;
2781 +
2782 + if (ecmd->rx_coalesce_usecs != 0 &&
2783 + (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax))
2784 + return -EINVAL;
2785 +
2786 + if (ecmd->rx_coalesce_usecs_irq != 0 &&
2787 + (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax))
2788 + return -EINVAL;
2789 +
2790 + if (ecmd->tx_max_coalesced_frames > 0xffff)
2791 + return -EINVAL;
2792 + if (ecmd->rx_max_coalesced_frames > 0xff)
2793 + return -EINVAL;
2794 + if (ecmd->rx_max_coalesced_frames_irq > 0xff)
2795 + return -EINVAL;
2796 +
2797 + if (ecmd->tx_coalesce_usecs == 0)
2798 + sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2799 + else {
2800 + sky2_write32(hw, STAT_TX_TIMER_INI,
2801 + sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2802 + sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2803 + }
2804 + sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2805 +
2806 + if (ecmd->rx_coalesce_usecs == 0)
2807 + sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2808 + else {
2809 + sky2_write32(hw, STAT_LEV_TIMER_INI,
2810 + sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2811 + sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2812 + }
2813 + sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2814 +
2815 + if (ecmd->rx_coalesce_usecs_irq == 0)
2816 + sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2817 + else {
2818 + sky2_write32(hw, STAT_TX_TIMER_INI,
2819 + sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2820 + sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2821 + }
2822 + sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2823 + return 0;
2824 +}
2825 +
2826 +static void sky2_get_ringparam(struct net_device *dev,
2827 + struct ethtool_ringparam *ering)
2828 +{
2829 + struct sky2_port *sky2 = netdev_priv(dev);
2830 +
2831 + ering->rx_max_pending = RX_MAX_PENDING;
2832 + ering->rx_mini_max_pending = 0;
2833 + ering->rx_jumbo_max_pending = 0;
2834 + ering->tx_max_pending = TX_RING_SIZE - 1;
2835 +
2836 + ering->rx_pending = sky2->rx_pending;
2837 + ering->rx_mini_pending = 0;
2838 + ering->rx_jumbo_pending = 0;
2839 + ering->tx_pending = sky2->tx_pending;
2840 +}
2841 +
2842 +static int sky2_set_ringparam(struct net_device *dev,
2843 + struct ethtool_ringparam *ering)
2844 +{
2845 + struct sky2_port *sky2 = netdev_priv(dev);
2846 + int err = 0;
2847 +
2848 + if (ering->rx_pending > RX_MAX_PENDING ||
2849 + ering->rx_pending < 8 ||
2850 + ering->tx_pending < MAX_SKB_TX_LE ||
2851 + ering->tx_pending > TX_RING_SIZE - 1)
2852 + return -EINVAL;
2853 +
2854 + if (netif_running(dev))
2855 + sky2_down(dev);
2856 +
2857 + sky2->rx_pending = ering->rx_pending;
2858 + sky2->tx_pending = ering->tx_pending;
2859 +
2860 + if (netif_running(dev)) {
2861 + err = sky2_up(dev);
2862 + if (err)
2863 + dev_close(dev);
2864 + else
2865 + sky2_set_multicast(dev);
2866 + }
2867 +
2868 + return err;
2869 +}
2870 +
2871 +static int sky2_get_regs_len(struct net_device *dev)
2872 +{
2873 + return 0x4000;
2874 +}
2875 +
2876 +/*
2877 + * Returns copy of control register region
2878 + * Note: access to the RAM address register set will cause timeouts.
2879 + */
2880 +static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2881 + void *p)
2882 +{
2883 + const struct sky2_port *sky2 = netdev_priv(dev);
2884 + const void __iomem *io = sky2->hw->regs;
2885 +
2886 + BUG_ON(regs->len < B3_RI_WTO_R1);
2887 + regs->version = 1;
2888 + memset(p, 0, regs->len);
2889 +
2890 + memcpy_fromio(p, io, B3_RAM_ADDR);
2891 +
2892 + memcpy_fromio(p + B3_RI_WTO_R1,
2893 + io + B3_RI_WTO_R1,
2894 + regs->len - B3_RI_WTO_R1);
2895 +}
2896 +
2897 +static struct ethtool_ops sky2_ethtool_ops = {
2898 + .get_settings = sky2_get_settings,
2899 + .set_settings = sky2_set_settings,
2900 + .get_drvinfo = sky2_get_drvinfo,
2901 + .get_msglevel = sky2_get_msglevel,
2902 + .set_msglevel = sky2_set_msglevel,
2903 + .nway_reset = sky2_nway_reset,
2904 + .get_regs_len = sky2_get_regs_len,
2905 + .get_regs = sky2_get_regs,
2906 + .get_link = ethtool_op_get_link,
2907 + .get_sg = ethtool_op_get_sg,
2908 + .set_sg = ethtool_op_set_sg,
2909 + .get_tx_csum = ethtool_op_get_tx_csum,
2910 + .set_tx_csum = ethtool_op_set_tx_csum,
2911 + .get_tso = ethtool_op_get_tso,
2912 + .set_tso = ethtool_op_set_tso,
2913 + .get_rx_csum = sky2_get_rx_csum,
2914 + .set_rx_csum = sky2_set_rx_csum,
2915 + .get_strings = sky2_get_strings,
2916 + .get_coalesce = sky2_get_coalesce,
2917 + .set_coalesce = sky2_set_coalesce,
2918 + .get_ringparam = sky2_get_ringparam,
2919 + .set_ringparam = sky2_set_ringparam,
2920 + .get_pauseparam = sky2_get_pauseparam,
2921 + .set_pauseparam = sky2_set_pauseparam,
2922 +#ifdef CONFIG_PM
2923 + .get_wol = sky2_get_wol,
2924 + .set_wol = sky2_set_wol,
2925 +#endif
2926 + .phys_id = sky2_phys_id,
2927 + .get_stats_count = sky2_get_stats_count,
2928 + .get_ethtool_stats = sky2_get_ethtool_stats,
2929 + .get_perm_addr = ethtool_op_get_perm_addr,
2930 +};
2931 +
2932 +/* Initialize network device */
2933 +static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2934 + unsigned port, int highmem)
2935 +{
2936 + struct sky2_port *sky2;
2937 + struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2938 +
2939 + if (!dev) {
2940 + printk(KERN_ERR "sky2 etherdev alloc failed");
2941 + return NULL;
2942 + }
2943 +
2944 + SET_MODULE_OWNER(dev);
2945 + SET_NETDEV_DEV(dev, &hw->pdev->dev);
2946 + dev->irq = hw->pdev->irq;
2947 + dev->open = sky2_up;
2948 + dev->stop = sky2_down;
2949 + dev->do_ioctl = sky2_ioctl;
2950 + dev->hard_start_xmit = sky2_xmit_frame;
2951 + dev->get_stats = sky2_get_stats;
2952 + dev->set_multicast_list = sky2_set_multicast;
2953 + dev->set_mac_address = sky2_set_mac_address;
2954 + dev->change_mtu = sky2_change_mtu;
2955 + SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
2956 + dev->tx_timeout = sky2_tx_timeout;
2957 + dev->watchdog_timeo = TX_WATCHDOG;
2958 + if (port == 0)
2959 + dev->poll = sky2_poll;
2960 + dev->weight = NAPI_WEIGHT;
2961 +#ifdef CONFIG_NET_POLL_CONTROLLER
2962 + dev->poll_controller = sky2_netpoll;
2963 +#endif
2964 +
2965 + sky2 = netdev_priv(dev);
2966 + sky2->netdev = dev;
2967 + sky2->hw = hw;
2968 + sky2->msg_enable = netif_msg_init(debug, default_msg);
2969 +
2970 + spin_lock_init(&sky2->tx_lock);
2971 + /* Auto speed and flow control */
2972 + sky2->autoneg = AUTONEG_ENABLE;
2973 + sky2->tx_pause = 1;
2974 + sky2->rx_pause = 1;
2975 + sky2->duplex = -1;
2976 + sky2->speed = -1;
2977 + sky2->advertising = sky2_supported_modes(hw);
2978 +
2979 + /* Receive checksum disabled for Yukon XL
2980 + * because of observed problems with incorrect
2981 + * values when multiple packets are received in one interrupt
2982 + */
2983 + sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
2984 +
2985 + INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2);
2986 + init_MUTEX(&sky2->phy_sema);
2987 + sky2->tx_pending = TX_DEF_PENDING;
2988 + sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
2989 + sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
2990 +
2991 + hw->dev[port] = dev;
2992 +
2993 + sky2->port = port;
2994 +
2995 + dev->features |= NETIF_F_LLTX;
2996 + if (hw->chip_id != CHIP_ID_YUKON_EC_U)
2997 + dev->features |= NETIF_F_TSO;
2998 + if (highmem)
2999 + dev->features |= NETIF_F_HIGHDMA;
3000 + dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3001 +
3002 +#ifdef SKY2_VLAN_TAG_USED
3003 + dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3004 + dev->vlan_rx_register = sky2_vlan_rx_register;
3005 + dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3006 +#endif
3007 +
3008 + /* read the mac address */
3009 + memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3010 + memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3011 +
3012 + /* device is off until link detection */
3013 + netif_carrier_off(dev);
3014 + netif_stop_queue(dev);
3015 +
3016 + return dev;
3017 +}
3018 +
3019 +static inline void sky2_show_addr(struct net_device *dev)
3020 +{
3021 + const struct sky2_port *sky2 = netdev_priv(dev);
3022 +
3023 + if (netif_msg_probe(sky2))
3024 + printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3025 + dev->name,
3026 + dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3027 + dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3028 +}
3029 +
3030 +static int __devinit sky2_probe(struct pci_dev *pdev,
3031 + const struct pci_device_id *ent)
3032 +{
3033 + struct net_device *dev, *dev1 = NULL;
3034 + struct sky2_hw *hw;
3035 + int err, pm_cap, using_dac = 0;
3036 +
3037 + err = pci_enable_device(pdev);
3038 + if (err) {
3039 + printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3040 + pci_name(pdev));
3041 + goto err_out;
3042 + }
3043 +
3044 + err = pci_request_regions(pdev, DRV_NAME);
3045 + if (err) {
3046 + printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3047 + pci_name(pdev));
3048 + goto err_out;
3049 + }
3050 +
3051 + pci_set_master(pdev);
3052 +
3053 + /* Find power-management capability. */
3054 + pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3055 + if (pm_cap == 0) {
3056 + printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3057 + "aborting.\n");
3058 + err = -EIO;
3059 + goto err_out_free_regions;
3060 + }
3061 +
3062 + if (sizeof(dma_addr_t) > sizeof(u32) &&
3063 + !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3064 + using_dac = 1;
3065 + err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3066 + if (err < 0) {
3067 + printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3068 + "for consistent allocations\n", pci_name(pdev));
3069 + goto err_out_free_regions;
3070 + }
3071 +
3072 + } else {
3073 + err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3074 + if (err) {
3075 + printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3076 + pci_name(pdev));
3077 + goto err_out_free_regions;
3078 + }
3079 + }
3080 +
3081 +#ifdef __BIG_ENDIAN
3082 + /* byte swap descriptors in hardware */
3083 + {
3084 + u32 reg;
3085 +
3086 + pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3087 + reg |= PCI_REV_DESC;
3088 + pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3089 + }
3090 +#endif
3091 +
3092 + err = -ENOMEM;
3093 + hw = kmalloc(sizeof(*hw), GFP_KERNEL);
3094 + if (!hw) {
3095 + printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3096 + pci_name(pdev));
3097 + goto err_out_free_regions;
3098 + }
3099 +
3100 + memset(hw, 0, sizeof(*hw));
3101 + hw->pdev = pdev;
3102 +
3103 + hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3104 + if (!hw->regs) {
3105 + printk(KERN_ERR PFX "%s: cannot map device registers\n",
3106 + pci_name(pdev));
3107 + goto err_out_free_hw;
3108 + }
3109 + hw->pm_cap = pm_cap;
3110 +
3111 + err = sky2_reset(hw);
3112 + if (err)
3113 + goto err_out_iounmap;
3114 +
3115 + printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3116 + DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
3117 + yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3118 + hw->chip_id, hw->chip_rev);
3119 +
3120 + dev = sky2_init_netdev(hw, 0, using_dac);
3121 + if (!dev)
3122 + goto err_out_free_pci;
3123 +
3124 + err = register_netdev(dev);
3125 + if (err) {
3126 + printk(KERN_ERR PFX "%s: cannot register net device\n",
3127 + pci_name(pdev));
3128 + goto err_out_free_netdev;
3129 + }
3130 +
3131 + sky2_show_addr(dev);
3132 +
3133 + if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3134 + if (register_netdev(dev1) == 0)
3135 + sky2_show_addr(dev1);
3136 + else {
3137 + /* Failure to register second port need not be fatal */
3138 + printk(KERN_WARNING PFX
3139 + "register of second port failed\n");
3140 + hw->dev[1] = NULL;
3141 + free_netdev(dev1);
3142 + }
3143 + }
3144 +
3145 + err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
3146 + if (err) {
3147 + printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3148 + pci_name(pdev), pdev->irq);
3149 + goto err_out_unregister;
3150 + }
3151 +
3152 + hw->intr_mask = Y2_IS_BASE;
3153 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
3154 +
3155 + pci_set_drvdata(pdev, hw);
3156 +
3157 + return 0;
3158 +
3159 +err_out_unregister:
3160 + if (dev1) {
3161 + unregister_netdev(dev1);
3162 + free_netdev(dev1);
3163 + }
3164 + unregister_netdev(dev);
3165 +err_out_free_netdev:
3166 + free_netdev(dev);
3167 +err_out_free_pci:
3168 + sky2_write8(hw, B0_CTST, CS_RST_SET);
3169 + pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3170 +err_out_iounmap:
3171 + iounmap(hw->regs);
3172 +err_out_free_hw:
3173 + kfree(hw);
3174 +err_out_free_regions:
3175 + pci_release_regions(pdev);
3176 + pci_disable_device(pdev);
3177 +err_out:
3178 + return err;
3179 +}
3180 +
3181 +static void __devexit sky2_remove(struct pci_dev *pdev)
3182 +{
3183 + struct sky2_hw *hw = pci_get_drvdata(pdev);
3184 + struct net_device *dev0, *dev1;
3185 +
3186 + if (!hw)
3187 + return;
3188 +
3189 + dev0 = hw->dev[0];
3190 + dev1 = hw->dev[1];
3191 + if (dev1)
3192 + unregister_netdev(dev1);
3193 + unregister_netdev(dev0);
3194 +
3195 + sky2_write32(hw, B0_IMSK, 0);
3196 + sky2_set_power_state(hw, PCI_D3hot);
3197 + sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3198 + sky2_write8(hw, B0_CTST, CS_RST_SET);
3199 + sky2_read8(hw, B0_CTST);
3200 +
3201 + free_irq(pdev->irq, hw);
3202 + pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3203 + pci_release_regions(pdev);
3204 + pci_disable_device(pdev);
3205 +
3206 + if (dev1)
3207 + free_netdev(dev1);
3208 + free_netdev(dev0);
3209 + iounmap(hw->regs);
3210 + kfree(hw);
3211 +
3212 + pci_set_drvdata(pdev, NULL);
3213 +}
3214 +
3215 +#ifdef CONFIG_PM
3216 +static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3217 +{
3218 + struct sky2_hw *hw = pci_get_drvdata(pdev);
3219 + int i;
3220 +
3221 + for (i = 0; i < 2; i++) {
3222 + struct net_device *dev = hw->dev[i];
3223 +
3224 + if (dev) {
3225 + if (!netif_running(dev))
3226 + continue;
3227 +
3228 + sky2_down(dev);
3229 + netif_device_detach(dev);
3230 + }
3231 + }
3232 +
3233 + return sky2_set_power_state(hw, pci_choose_state(pdev, state));
3234 +}
3235 +
3236 +static int sky2_resume(struct pci_dev *pdev)
3237 +{
3238 + struct sky2_hw *hw = pci_get_drvdata(pdev);
3239 + int i;
3240 +
3241 + pci_restore_state(pdev);
3242 + pci_enable_wake(pdev, PCI_D0, 0);
3243 + sky2_set_power_state(hw, PCI_D0);
3244 +
3245 + sky2_reset(hw);
3246 +
3247 + for (i = 0; i < 2; i++) {
3248 + struct net_device *dev = hw->dev[i];
3249 + if (dev) {
3250 + if (netif_running(dev)) {
3251 + netif_device_attach(dev);
3252 + if (sky2_up(dev))
3253 + dev_close(dev);
3254 + }
3255 + }
3256 + }
3257 + return 0;
3258 +}
3259 +#endif
3260 +
3261 +static struct pci_driver sky2_driver = {
3262 + .name = DRV_NAME,
3263 + .id_table = sky2_id_table,
3264 + .probe = sky2_probe,
3265 + .remove = __devexit_p(sky2_remove),
3266 +#ifdef CONFIG_PM
3267 + .suspend = sky2_suspend,
3268 + .resume = sky2_resume,
3269 +#endif
3270 +};
3271 +
3272 +static int __init sky2_init_module(void)
3273 +{
3274 + return pci_register_driver(&sky2_driver);
3275 +}
3276 +
3277 +static void __exit sky2_cleanup_module(void)
3278 +{
3279 + pci_unregister_driver(&sky2_driver);
3280 +}
3281 +
3282 +module_init(sky2_init_module);
3283 +module_exit(sky2_cleanup_module);
3284 +
3285 +MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3286 +MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3287 +MODULE_LICENSE("GPL");
3288 +MODULE_VERSION(DRV_VERSION);
3289 --- linux-2.6.15/drivers/net/sky2.h 1970-01-01 01:00:00.000000000 +0100
3290 +++ linux-dsd/drivers/net/sky2.h 2006-01-03 18:10:52.000000000 +0000
3291 @@ -0,0 +1,1922 @@
3292 +/*
3293 + * Definitions for the new Marvell Yukon 2 driver.
3294 + */
3295 +#ifndef _SKY2_H
3296 +#define _SKY2_H
3297 +
3298 +/* PCI config registers */
3299 +#define PCI_DEV_REG1 0x40
3300 +#define PCI_DEV_REG2 0x44
3301 +#define PCI_DEV_STATUS 0x7c
3302 +#define PCI_OS_PCI_X (1<<26)
3303 +
3304 +#define PEX_LNK_STAT 0xf2
3305 +#define PEX_UNC_ERR_STAT 0x104
3306 +#define PEX_DEV_CTRL 0xe8
3307 +
3308 +/* Yukon-2 */
3309 +enum pci_dev_reg_1 {
3310 + PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
3311 + PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
3312 + PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
3313 + PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
3314 + PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
3315 + PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
3316 +};
3317 +
3318 +enum pci_dev_reg_2 {
3319 + PCI_VPD_WR_THR = 0xffL<<24, /* Bit 31..24: VPD Write Threshold */
3320 + PCI_DEV_SEL = 0x7fL<<17, /* Bit 23..17: EEPROM Device Select */
3321 + PCI_VPD_ROM_SZ = 7L<<14, /* Bit 16..14: VPD ROM Size */
3322 +
3323 + PCI_PATCH_DIR = 0xfL<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */
3324 + PCI_EXT_PATCHS = 0xfL<<4, /* Bit 7.. 4: Extended Patches 3..0 */
3325 + PCI_EN_DUMMY_RD = 1<<3, /* Enable Dummy Read */
3326 + PCI_REV_DESC = 1<<2, /* Reverse Desc. Bytes */
3327 +
3328 + PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */
3329 +};
3330 +
3331 +
3332 +#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
3333 + PCI_STATUS_SIG_SYSTEM_ERROR | \
3334 + PCI_STATUS_REC_MASTER_ABORT | \
3335 + PCI_STATUS_REC_TARGET_ABORT | \
3336 + PCI_STATUS_PARITY)
3337 +
3338 +enum pex_dev_ctrl {
3339 + PEX_DC_MAX_RRS_MSK = 7<<12, /* Bit 14..12: Max. Read Request Size */
3340 + PEX_DC_EN_NO_SNOOP = 1<<11,/* Enable No Snoop */
3341 + PEX_DC_EN_AUX_POW = 1<<10,/* Enable AUX Power */
3342 + PEX_DC_EN_PHANTOM = 1<<9, /* Enable Phantom Functions */
3343 + PEX_DC_EN_EXT_TAG = 1<<8, /* Enable Extended Tag Field */
3344 + PEX_DC_MAX_PLS_MSK = 7<<5, /* Bit 7.. 5: Max. Payload Size Mask */
3345 + PEX_DC_EN_REL_ORD = 1<<4, /* Enable Relaxed Ordering */
3346 + PEX_DC_EN_UNS_RQ_RP = 1<<3, /* Enable Unsupported Request Reporting */
3347 + PEX_DC_EN_FAT_ER_RP = 1<<2, /* Enable Fatal Error Reporting */
3348 + PEX_DC_EN_NFA_ER_RP = 1<<1, /* Enable Non-Fatal Error Reporting */
3349 + PEX_DC_EN_COR_ER_RP = 1<<0, /* Enable Correctable Error Reporting */
3350 +};
3351 +#define PEX_DC_MAX_RD_RQ_SIZE(x) (((x)<<12) & PEX_DC_MAX_RRS_MSK)
3352 +
3353 +/* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */
3354 +enum pex_err {
3355 + PEX_UNSUP_REQ = 1<<20, /* Unsupported Request Error */
3356 +
3357 + PEX_MALFOR_TLP = 1<<18, /* Malformed TLP */
3358 +
3359 + PEX_UNEXP_COMP = 1<<16, /* Unexpected Completion */
3360 +
3361 + PEX_COMP_TO = 1<<14, /* Completion Timeout */
3362 + PEX_FLOW_CTRL_P = 1<<13, /* Flow Control Protocol Error */
3363 + PEX_POIS_TLP = 1<<12, /* Poisoned TLP */
3364 +
3365 + PEX_DATA_LINK_P = 1<<4, /* Data Link Protocol Error */
3366 + PEX_FATAL_ERRORS= (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P),
3367 +};
3368 +
3369 +
3370 +enum csr_regs {
3371 + B0_RAP = 0x0000,
3372 + B0_CTST = 0x0004,
3373 + B0_Y2LED = 0x0005,
3374 + B0_POWER_CTRL = 0x0007,
3375 + B0_ISRC = 0x0008,
3376 + B0_IMSK = 0x000c,
3377 + B0_HWE_ISRC = 0x0010,
3378 + B0_HWE_IMSK = 0x0014,
3379 +
3380 + /* Special ISR registers (Yukon-2 only) */
3381 + B0_Y2_SP_ISRC2 = 0x001c,
3382 + B0_Y2_SP_ISRC3 = 0x0020,
3383 + B0_Y2_SP_EISR = 0x0024,
3384 + B0_Y2_SP_LISR = 0x0028,
3385 + B0_Y2_SP_ICR = 0x002c,
3386 +
3387 + B2_MAC_1 = 0x0100,
3388 + B2_MAC_2 = 0x0108,
3389 + B2_MAC_3 = 0x0110,
3390 + B2_CONN_TYP = 0x0118,
3391 + B2_PMD_TYP = 0x0119,
3392 + B2_MAC_CFG = 0x011a,
3393 + B2_CHIP_ID = 0x011b,
3394 + B2_E_0 = 0x011c,
3395 +
3396 + B2_Y2_CLK_GATE = 0x011d,
3397 + B2_Y2_HW_RES = 0x011e,
3398 + B2_E_3 = 0x011f,
3399 + B2_Y2_CLK_CTRL = 0x0120,
3400 +
3401 + B2_TI_INI = 0x0130,
3402 + B2_TI_VAL = 0x0134,
3403 + B2_TI_CTRL = 0x0138,
3404 + B2_TI_TEST = 0x0139,
3405 +
3406 + B2_TST_CTRL1 = 0x0158,
3407 + B2_TST_CTRL2 = 0x0159,
3408 + B2_GP_IO = 0x015c,
3409 +
3410 + B2_I2C_CTRL = 0x0160,
3411 + B2_I2C_DATA = 0x0164,
3412 + B2_I2C_IRQ = 0x0168,
3413 + B2_I2C_SW = 0x016c,
3414 +
3415 + B3_RAM_ADDR = 0x0180,
3416 + B3_RAM_DATA_LO = 0x0184,
3417 + B3_RAM_DATA_HI = 0x0188,
3418 +
3419 +/* RAM Interface Registers */
3420 +/* Yukon-2: use RAM_BUFFER() to access the RAM buffer */
3421 +/*
3422 + * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
3423 + * not usable in SW. Please notice these are NOT real timeouts, these are
3424 + * the number of qWords transferred continuously.
3425 + */
3426 +#define RAM_BUFFER(port, reg) (reg | (port <<6))
3427 +
3428 + B3_RI_WTO_R1 = 0x0190,
3429 + B3_RI_WTO_XA1 = 0x0191,
3430 + B3_RI_WTO_XS1 = 0x0192,
3431 + B3_RI_RTO_R1 = 0x0193,
3432 + B3_RI_RTO_XA1 = 0x0194,
3433 + B3_RI_RTO_XS1 = 0x0195,
3434 + B3_RI_WTO_R2 = 0x0196,
3435 + B3_RI_WTO_XA2 = 0x0197,
3436 + B3_RI_WTO_XS2 = 0x0198,
3437 + B3_RI_RTO_R2 = 0x0199,
3438 + B3_RI_RTO_XA2 = 0x019a,
3439 + B3_RI_RTO_XS2 = 0x019b,
3440 + B3_RI_TO_VAL = 0x019c,
3441 + B3_RI_CTRL = 0x01a0,
3442 + B3_RI_TEST = 0x01a2,
3443 + B3_MA_TOINI_RX1 = 0x01b0,
3444 + B3_MA_TOINI_RX2 = 0x01b1,
3445 + B3_MA_TOINI_TX1 = 0x01b2,
3446 + B3_MA_TOINI_TX2 = 0x01b3,
3447 + B3_MA_TOVAL_RX1 = 0x01b4,
3448 + B3_MA_TOVAL_RX2 = 0x01b5,
3449 + B3_MA_TOVAL_TX1 = 0x01b6,
3450 + B3_MA_TOVAL_TX2 = 0x01b7,
3451 + B3_MA_TO_CTRL = 0x01b8,
3452 + B3_MA_TO_TEST = 0x01ba,
3453 + B3_MA_RCINI_RX1 = 0x01c0,
3454 + B3_MA_RCINI_RX2 = 0x01c1,
3455 + B3_MA_RCINI_TX1 = 0x01c2,
3456 + B3_MA_RCINI_TX2 = 0x01c3,
3457 + B3_MA_RCVAL_RX1 = 0x01c4,
3458 + B3_MA_RCVAL_RX2 = 0x01c5,
3459 + B3_MA_RCVAL_TX1 = 0x01c6,
3460 + B3_MA_RCVAL_TX2 = 0x01c7,
3461 + B3_MA_RC_CTRL = 0x01c8,
3462 + B3_MA_RC_TEST = 0x01ca,
3463 + B3_PA_TOINI_RX1 = 0x01d0,
3464 + B3_PA_TOINI_RX2 = 0x01d4,
3465 + B3_PA_TOINI_TX1 = 0x01d8,
3466 + B3_PA_TOINI_TX2 = 0x01dc,
3467 + B3_PA_TOVAL_RX1 = 0x01e0,
3468 + B3_PA_TOVAL_RX2 = 0x01e4,
3469 + B3_PA_TOVAL_TX1 = 0x01e8,
3470 + B3_PA_TOVAL_TX2 = 0x01ec,
3471 + B3_PA_CTRL = 0x01f0,
3472 + B3_PA_TEST = 0x01f2,
3473 +
3474 + Y2_CFG_SPC = 0x1c00,
3475 +};
3476 +
3477 +/* B0_CTST 16 bit Control/Status register */
3478 +enum {
3479 + Y2_VMAIN_AVAIL = 1<<17,/* VMAIN available (YUKON-2 only) */
3480 + Y2_VAUX_AVAIL = 1<<16,/* VAUX available (YUKON-2 only) */
3481 + Y2_ASF_ENABLE = 1<<13,/* ASF Unit Enable (YUKON-2 only) */
3482 + Y2_ASF_DISABLE = 1<<12,/* ASF Unit Disable (YUKON-2 only) */
3483 + Y2_CLK_RUN_ENA = 1<<11,/* CLK_RUN Enable (YUKON-2 only) */
3484 + Y2_CLK_RUN_DIS = 1<<10,/* CLK_RUN Disable (YUKON-2 only) */
3485 + Y2_LED_STAT_ON = 1<<9, /* Status LED On (YUKON-2 only) */
3486 + Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */
3487 +
3488 + CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
3489 + CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
3490 + CS_STOP_DONE = 1<<5, /* Stop Master is finished */
3491 + CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
3492 + CS_MRST_CLR = 1<<3, /* Clear Master reset */
3493 + CS_MRST_SET = 1<<2, /* Set Master reset */
3494 + CS_RST_CLR = 1<<1, /* Clear Software reset */
3495 + CS_RST_SET = 1, /* Set Software reset */
3496 +};
3497 +
3498 +/* B0_LED 8 Bit LED register */
3499 +enum {
3500 +/* Bit 7.. 2: reserved */
3501 + LED_STAT_ON = 1<<1, /* Status LED on */
3502 + LED_STAT_OFF = 1, /* Status LED off */
3503 +};
3504 +
3505 +/* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
3506 +enum {
3507 + PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
3508 + PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
3509 + PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
3510 + PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
3511 + PC_VAUX_ON = 1<<3, /* Switch VAUX On */
3512 + PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
3513 + PC_VCC_ON = 1<<1, /* Switch VCC On */
3514 + PC_VCC_OFF = 1<<0, /* Switch VCC Off */
3515 +};
3516 +
3517 +/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
3518 +
3519 +/* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */
3520 +/* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */
3521 +/* B0_Y2_SP_EISR 32 bit Enter ISR Reg */
3522 +/* B0_Y2_SP_LISR 32 bit Leave ISR Reg */
3523 +enum {
3524 + Y2_IS_HW_ERR = 1<<31, /* Interrupt HW Error */
3525 + Y2_IS_STAT_BMU = 1<<30, /* Status BMU Interrupt */
3526 + Y2_IS_ASF = 1<<29, /* ASF subsystem Interrupt */
3527 +
3528 + Y2_IS_POLL_CHK = 1<<27, /* Check IRQ from polling unit */
3529 + Y2_IS_TWSI_RDY = 1<<26, /* IRQ on end of TWSI Tx */
3530 + Y2_IS_IRQ_SW = 1<<25, /* SW forced IRQ */
3531 + Y2_IS_TIMINT = 1<<24, /* IRQ from Timer */
3532 +
3533 + Y2_IS_IRQ_PHY2 = 1<<12, /* Interrupt from PHY 2 */
3534 + Y2_IS_IRQ_MAC2 = 1<<11, /* Interrupt from MAC 2 */
3535 + Y2_IS_CHK_RX2 = 1<<10, /* Descriptor error Rx 2 */
3536 + Y2_IS_CHK_TXS2 = 1<<9, /* Descriptor error TXS 2 */
3537 + Y2_IS_CHK_TXA2 = 1<<8, /* Descriptor error TXA 2 */
3538 +
3539 + Y2_IS_IRQ_PHY1 = 1<<4, /* Interrupt from PHY 1 */
3540 + Y2_IS_IRQ_MAC1 = 1<<3, /* Interrupt from MAC 1 */
3541 + Y2_IS_CHK_RX1 = 1<<2, /* Descriptor error Rx 1 */
3542 + Y2_IS_CHK_TXS1 = 1<<1, /* Descriptor error TXS 1 */
3543 + Y2_IS_CHK_TXA1 = 1<<0, /* Descriptor error TXA 1 */
3544 +
3545 + Y2_IS_BASE = Y2_IS_HW_ERR | Y2_IS_STAT_BMU |
3546 + Y2_IS_POLL_CHK | Y2_IS_TWSI_RDY |
3547 + Y2_IS_IRQ_SW | Y2_IS_TIMINT,
3548 + Y2_IS_PORT_1 = Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1 |
3549 + Y2_IS_CHK_RX1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXS1,
3550 + Y2_IS_PORT_2 = Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 |
3551 + Y2_IS_CHK_RX2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_TXS2,
3552 +};
3553 +
3554 +/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
3555 +enum {
3556 + IS_ERR_MSK = 0x00003fff,/* All Error bits */
3557 +
3558 + IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
3559 + IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
3560 + IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
3561 + IS_IRQ_STAT = 1<<10, /* IRQ status exception */
3562 + IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
3563 + IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
3564 + IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
3565 + IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
3566 + IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
3567 + IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
3568 + IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
3569 + IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
3570 + IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
3571 + IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
3572 +};
3573 +
3574 +/* Hardware error interrupt mask for Yukon 2 */
3575 +enum {
3576 + Y2_IS_TIST_OV = 1<<29,/* Time Stamp Timer overflow interrupt */
3577 + Y2_IS_SENSOR = 1<<28, /* Sensor interrupt */
3578 + Y2_IS_MST_ERR = 1<<27, /* Master error interrupt */
3579 + Y2_IS_IRQ_STAT = 1<<26, /* Status exception interrupt */
3580 + Y2_IS_PCI_EXP = 1<<25, /* PCI-Express interrupt */
3581 + Y2_IS_PCI_NEXP = 1<<24, /* PCI-Express error similar to PCI error */
3582 + /* Link 2 */
3583 + Y2_IS_PAR_RD2 = 1<<13, /* Read RAM parity error interrupt */
3584 + Y2_IS_PAR_WR2 = 1<<12, /* Write RAM parity error interrupt */
3585 + Y2_IS_PAR_MAC2 = 1<<11, /* MAC hardware fault interrupt */
3586 + Y2_IS_PAR_RX2 = 1<<10, /* Parity Error Rx Queue 2 */
3587 + Y2_IS_TCP_TXS2 = 1<<9, /* TCP length mismatch sync Tx queue IRQ */
3588 + Y2_IS_TCP_TXA2 = 1<<8, /* TCP length mismatch async Tx queue IRQ */
3589 + /* Link 1 */
3590 + Y2_IS_PAR_RD1 = 1<<5, /* Read RAM parity error interrupt */
3591 + Y2_IS_PAR_WR1 = 1<<4, /* Write RAM parity error interrupt */
3592 + Y2_IS_PAR_MAC1 = 1<<3, /* MAC hardware fault interrupt */
3593 + Y2_IS_PAR_RX1 = 1<<2, /* Parity Error Rx Queue 1 */
3594 + Y2_IS_TCP_TXS1 = 1<<1, /* TCP length mismatch sync Tx queue IRQ */
3595 + Y2_IS_TCP_TXA1 = 1<<0, /* TCP length mismatch async Tx queue IRQ */
3596 +
3597 + Y2_HWE_L1_MASK = Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |
3598 + Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1,
3599 + Y2_HWE_L2_MASK = Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |
3600 + Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2,
3601 +
3602 + Y2_HWE_ALL_MASK = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT |
3603 + Y2_IS_PCI_EXP |
3604 + Y2_HWE_L1_MASK | Y2_HWE_L2_MASK,
3605 +};
3606 +
3607 +/* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
3608 +enum {
3609 + DPT_START = 1<<1,
3610 + DPT_STOP = 1<<0,
3611 +};
3612 +
3613 +/* B2_TST_CTRL1 8 bit Test Control Register 1 */
3614 +enum {
3615 + TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
3616 + TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
3617 + TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
3618 + TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
3619 + TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
3620 + TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
3621 + TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
3622 + TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
3623 +};
3624 +
3625 +/* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
3626 +enum {
3627 + CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
3628 + /* Bit 3.. 2: reserved */
3629 + CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
3630 + CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
3631 +};
3632 +
3633 +/* B2_CHIP_ID 8 bit Chip Identification Number */
3634 +enum {
3635 + CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */
3636 + CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */
3637 + CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
3638 + CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
3639 + CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
3640 + CHIP_ID_YUKON_EC_U = 0xb4, /* Chip ID for YUKON-2 EC Ultra */
3641 + CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
3642 + CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
3643 +
3644 + CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */
3645 + CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */
3646 + CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */
3647 +};
3648 +
3649 +/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
3650 +enum {
3651 + Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactive (0 = active) */
3652 + Y2_CLK_GAT_LNK2_DIS = 1<<6, /* Disable clock gating Link 2 */
3653 + Y2_COR_CLK_LNK2_DIS = 1<<5, /* Disable Core clock Link 2 */
3654 + Y2_PCI_CLK_LNK2_DIS = 1<<4, /* Disable PCI clock Link 2 */
3655 + Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactive (0 = active) */
3656 + Y2_CLK_GAT_LNK1_DIS = 1<<2, /* Disable clock gating Link 1 */
3657 + Y2_COR_CLK_LNK1_DIS = 1<<1, /* Disable Core clock Link 1 */
3658 + Y2_PCI_CLK_LNK1_DIS = 1<<0, /* Disable PCI clock Link 1 */
3659 +};
3660 +
3661 +/* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
3662 +enum {
3663 + CFG_LED_MODE_MSK = 7<<2, /* Bit 4.. 2: LED Mode Mask */
3664 + CFG_LINK_2_AVAIL = 1<<1, /* Link 2 available */
3665 + CFG_LINK_1_AVAIL = 1<<0, /* Link 1 available */
3666 +};
3667 +#define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2)
3668 +#define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)
3669 +
3670 +
3671 +/* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */
3672 +enum {
3673 + Y2_CLK_DIV_VAL_MSK = 0xff<<16,/* Bit 23..16: Clock Divisor Value */
3674 +#define Y2_CLK_DIV_VAL(x) (((x)<<16) & Y2_CLK_DIV_VAL_MSK)
3675 + Y2_CLK_DIV_VAL2_MSK = 7<<21, /* Bit 23..21: Clock Divisor Value */
3676 + Y2_CLK_SELECT2_MSK = 0x1f<<16,/* Bit 20..16: Clock Select */
3677 +#define Y2_CLK_DIV_VAL_2(x) (((x)<<21) & Y2_CLK_DIV_VAL2_MSK)
3678 +#define Y2_CLK_SEL_VAL_2(x) (((x)<<16) & Y2_CLK_SELECT2_MSK)
3679 + Y2_CLK_DIV_ENA = 1<<1, /* Enable Core Clock Division */
3680 + Y2_CLK_DIV_DIS = 1<<0, /* Disable Core Clock Division */
3681 +};
3682 +
3683 +/* B2_TI_CTRL 8 bit Timer control */
3684 +/* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
3685 +enum {
3686 + TIM_START = 1<<2, /* Start Timer */
3687 + TIM_STOP = 1<<1, /* Stop Timer */
3688 + TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
3689 +};
3690 +
3691 +/* B2_TI_TEST 8 Bit Timer Test */
3692 +/* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
3693 +/* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
3694 +enum {
3695 + TIM_T_ON = 1<<2, /* Test mode on */
3696 + TIM_T_OFF = 1<<1, /* Test mode off */
3697 + TIM_T_STEP = 1<<0, /* Test step */
3698 +};
3699 +
3700 +/* B3_RAM_ADDR 32 bit RAM Address, to read or write */
3701 + /* Bit 31..19: reserved */
3702 +#define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
3703 +/* RAM Interface Registers */
3704 +
3705 +/* B3_RI_CTRL 16 bit RAM Interface Control Register */
3706 +enum {
3707 + RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
3708 + RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
3709 +
3710 + RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
3711 + RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
3712 +};
3713 +
3714 +#define SK_RI_TO_53 36 /* RAM interface timeout */
3715 +
3716 +
3717 +/* Port related registers FIFO, and Arbiter */
3718 +#define SK_REG(port,reg) (((port)<<7)+(reg))
3719 +
3720 +/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
3721 +/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
3722 +/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
3723 +/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
3724 +/* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
3725 +
3726 +#define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
3727 +
3728 +/* TXA_CTRL 8 bit Tx Arbiter Control Register */
3729 +enum {
3730 + TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
3731 + TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
3732 + TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
3733 + TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
3734 + TXA_START_RC = 1<<3, /* Start sync Rate Control */
3735 + TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
3736 + TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
3737 + TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
3738 +};
3739 +
3740 +/*
3741 + * Bank 4 - 5
3742 + */
3743 +/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
3744 +enum {
3745 + TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
3746 + TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
3747 + TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
3748 + TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
3749 + TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
3750 + TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
3751 + TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
3752 +};
3753 +
3754 +
3755 +enum {
3756 + B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
3757 + B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
3758 + B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
3759 + B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
3760 + B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
3761 + B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
3762 + B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
3763 + B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
3764 + B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
3765 +};
3766 +
3767 +/* Queue Register Offsets, use Q_ADDR() to access */
3768 +enum {
3769 + B8_Q_REGS = 0x0400, /* base of Queue registers */
3770 + Q_D = 0x00, /* 8*32 bit Current Descriptor */
3771 + Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */
3772 + Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */
3773 + Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
3774 + Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
3775 + Q_BC = 0x30, /* 32 bit Current Byte Counter */
3776 + Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
3777 + Q_F = 0x38, /* 32 bit Flag Register */
3778 + Q_T1 = 0x3c, /* 32 bit Test Register 1 */
3779 + Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */
3780 + Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */
3781 + Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */
3782 + Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */
3783 + Q_T2 = 0x40, /* 32 bit Test Register 2 */
3784 + Q_T3 = 0x44, /* 32 bit Test Register 3 */
3785 +
3786 +/* Yukon-2 */
3787 + Q_DONE = 0x24, /* 16 bit Done Index (Yukon-2 only) */
3788 + Q_WM = 0x40, /* 16 bit FIFO Watermark */
3789 + Q_AL = 0x42, /* 8 bit FIFO Alignment */
3790 + Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */
3791 + Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */
3792 + Q_RP = 0x48, /* 8 bit FIFO Read Pointer */
3793 + Q_RL = 0x4a, /* 8 bit FIFO Read Level */
3794 + Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */
3795 + Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */
3796 + Q_WL = 0x4e, /* 8 bit FIFO Write Level */
3797 + Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */
3798 +};
3799 +#define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
3800 +
3801 +
3802 +/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
3803 +enum {
3804 + Y2_B8_PREF_REGS = 0x0450,
3805 +
3806 + PREF_UNIT_CTRL = 0x00, /* 32 bit Control register */
3807 + PREF_UNIT_LAST_IDX = 0x04, /* 16 bit Last Index */
3808 + PREF_UNIT_ADDR_LO = 0x08, /* 32 bit List start addr, low part */
3809 + PREF_UNIT_ADDR_HI = 0x0c, /* 32 bit List start addr, high part*/
3810 + PREF_UNIT_GET_IDX = 0x10, /* 16 bit Get Index */
3811 + PREF_UNIT_PUT_IDX = 0x14, /* 16 bit Put Index */
3812 + PREF_UNIT_FIFO_WP = 0x20, /* 8 bit FIFO write pointer */
3813 + PREF_UNIT_FIFO_RP = 0x24, /* 8 bit FIFO read pointer */
3814 + PREF_UNIT_FIFO_WM = 0x28, /* 8 bit FIFO watermark */
3815 + PREF_UNIT_FIFO_LEV = 0x2c, /* 8 bit FIFO level */
3816 +
3817 + PREF_UNIT_MASK_IDX = 0x0fff,
3818 +};
3819 +#define Y2_QADDR(q,reg) (Y2_B8_PREF_REGS + (q) + (reg))
3820 +
3821 +/* RAM Buffer Register Offsets */
3822 +enum {
3823 +
3824 + RB_START = 0x00,/* 32 bit RAM Buffer Start Address */
3825 + RB_END = 0x04,/* 32 bit RAM Buffer End Address */
3826 + RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
3827 + RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
3828 + RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
3829 + RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
3830 + RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */
3831 + RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
3832 + /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
3833 + RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
3834 + RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
3835 + RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
3836 + RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
3837 + RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
3838 +};
3839 +
3840 +/* Receive and Transmit Queues */
3841 +enum {
3842 + Q_R1 = 0x0000, /* Receive Queue 1 */
3843 + Q_R2 = 0x0080, /* Receive Queue 2 */
3844 + Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
3845 + Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
3846 + Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
3847 + Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
3848 +};
3849 +
3850 +/* Different PHY Types */
3851 +enum {
3852 + PHY_ADDR_MARV = 0,
3853 +};
3854 +
3855 +#define RB_ADDR(offs, queue) (B16_RAM_REGS + (queue) + (offs))
3856 +
3857 +
3858 +enum {
3859 + LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
3860 + LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
3861 + LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
3862 + LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
3863 +
3864 + LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
3865 +
3866 +/* Receive GMAC FIFO (YUKON and Yukon-2) */
3867 +
3868 + RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
3869 + RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
3870 + RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
3871 + RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
3872 + RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
3873 + RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
3874 + RX_GMF_UP_THR = 0x0c58,/* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */
3875 + RX_GMF_LP_THR = 0x0c5a,/* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */
3876 + RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
3877 + RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
3878 +
3879 + RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
3880 +
3881 + RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
3882 +
3883 + RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
3884 +};
3885 +
3886 +
3887 +/* Q_BC 32 bit Current Byte Counter */
3888 +
3889 +/* BMU Control Status Registers */
3890 +/* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
3891 +/* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
3892 +/* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
3893 +/* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
3894 +/* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
3895 +/* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
3896 +/* Q_CSR 32 bit BMU Control/Status Register */
3897 +
3898 +/* Rx BMU Control / Status Registers (Yukon-2) */
3899 +enum {
3900 + BMU_IDLE = 1<<31, /* BMU Idle State */
3901 + BMU_RX_TCP_PKT = 1<<30, /* Rx TCP Packet (when RSS Hash enabled) */
3902 + BMU_RX_IP_PKT = 1<<29, /* Rx IP Packet (when RSS Hash enabled) */
3903 +
3904 + BMU_ENA_RX_RSS_HASH = 1<<15, /* Enable Rx RSS Hash */
3905 + BMU_DIS_RX_RSS_HASH = 1<<14, /* Disable Rx RSS Hash */
3906 + BMU_ENA_RX_CHKSUM = 1<<13, /* Enable Rx TCP/IP Checksum Check */
3907 + BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */
3908 + BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */
3909 + BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment. error (Tx) */
3910 + BMU_CLR_IRQ_CHK = 1<<10, /* Clear IRQ Check */
3911 + BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */
3912 + BMU_START = 1<<8, /* Start Rx/Tx Queue */
3913 + BMU_FIFO_OP_ON = 1<<7, /* FIFO Operational On */
3914 + BMU_FIFO_OP_OFF = 1<<6, /* FIFO Operational Off */
3915 + BMU_FIFO_ENA = 1<<5, /* Enable FIFO */
3916 + BMU_FIFO_RST = 1<<4, /* Reset FIFO */
3917 + BMU_OP_ON = 1<<3, /* BMU Operational On */
3918 + BMU_OP_OFF = 1<<2, /* BMU Operational Off */
3919 + BMU_RST_CLR = 1<<1, /* Clear BMU Reset (Enable) */
3920 + BMU_RST_SET = 1<<0, /* Set BMU Reset */
3921 +
3922 + BMU_CLR_RESET = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR,
3923 + BMU_OPER_INIT = BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START |
3924 + BMU_FIFO_ENA | BMU_OP_ON,
3925 +
3926 + BMU_WM_DEFAULT = 0x600,
3927 +};
3928 +
3929 +/* Tx BMU Control / Status Registers (Yukon-2) */
3930 + /* Bit 31: same as for Rx */
3931 +enum {
3932 + BMU_TX_IPIDINCR_ON = 1<<13, /* Enable IP ID Increment */
3933 + BMU_TX_IPIDINCR_OFF = 1<<12, /* Disable IP ID Increment */
3934 + BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment length mismatch */
3935 +};
3936 +
3937 +/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
3938 +/* PREF_UNIT_CTRL 32 bit Prefetch Control register */
3939 +enum {
3940 + PREF_UNIT_OP_ON = 1<<3, /* prefetch unit operational */
3941 + PREF_UNIT_OP_OFF = 1<<2, /* prefetch unit not operational */
3942 + PREF_UNIT_RST_CLR = 1<<1, /* Clear Prefetch Unit Reset */
3943 + PREF_UNIT_RST_SET = 1<<0, /* Set Prefetch Unit Reset */
3944 +};
3945 +
3946 +/* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
3947 +/* RB_START 32 bit RAM Buffer Start Address */
3948 +/* RB_END 32 bit RAM Buffer End Address */
3949 +/* RB_WP 32 bit RAM Buffer Write Pointer */
3950 +/* RB_RP 32 bit RAM Buffer Read Pointer */
3951 +/* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
3952 +/* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
3953 +/* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
3954 +/* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
3955 +/* RB_PC 32 bit RAM Buffer Packet Counter */
3956 +/* RB_LEV 32 bit RAM Buffer Level Register */
3957 +
3958 +#define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
3959 +/* RB_TST2 8 bit RAM Buffer Test Register 2 */
3960 +/* RB_TST1 8 bit RAM Buffer Test Register 1 */
3961 +
3962 +/* RB_CTRL 8 bit RAM Buffer Control Register */
3963 +enum {
3964 + RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
3965 + RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
3966 + RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
3967 + RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
3968 + RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
3969 + RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
3970 +};
3971 +
3972 +
3973 +/* Transmit GMAC FIFO (YUKON only) */
3974 +enum {
3975 + TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
3976 + TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
3977 + TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
3978 +
3979 + TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
3980 + TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
3981 + TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
3982 +
3983 + TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
3984 + TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
3985 + TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
3986 +};
3987 +
3988 +/* Descriptor Poll Timer Registers */
3989 +enum {
3990 + B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
3991 + B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
3992 + B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
3993 +
3994 + B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
3995 +};
3996 +
3997 +/* Time Stamp Timer Registers (YUKON only) */
3998 +enum {
3999 + GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
4000 + GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
4001 + GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
4002 +};
4003 +
4004 +/* Polling Unit Registers (Yukon-2 only) */
4005 +enum {
4006 + POLL_CTRL = 0x0e20, /* 32 bit Polling Unit Control Reg */
4007 + POLL_LAST_IDX = 0x0e24,/* 16 bit Polling Unit List Last Index */
4008 +
4009 + POLL_LIST_ADDR_LO= 0x0e28,/* 32 bit Poll. List Start Addr (low) */
4010 + POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */
4011 +};
4012 +
4013 +/* ASF Subsystem Registers (Yukon-2 only) */
4014 +enum {
4015 + B28_Y2_SMB_CONFIG = 0x0e40,/* 32 bit ASF SMBus Config Register */
4016 + B28_Y2_SMB_CSD_REG = 0x0e44,/* 32 bit ASF SMB Control/Status/Data */
4017 + B28_Y2_ASF_IRQ_V_BASE=0x0e60,/* 32 bit ASF IRQ Vector Base */
4018 +
4019 + B28_Y2_ASF_STAT_CMD= 0x0e68,/* 32 bit ASF Status and Command Reg */
4020 + B28_Y2_ASF_HOST_COM= 0x0e6c,/* 32 bit ASF Host Communication Reg */
4021 + B28_Y2_DATA_REG_1 = 0x0e70,/* 32 bit ASF/Host Data Register 1 */
4022 + B28_Y2_DATA_REG_2 = 0x0e74,/* 32 bit ASF/Host Data Register 2 */
4023 + B28_Y2_DATA_REG_3 = 0x0e78,/* 32 bit ASF/Host Data Register 3 */
4024 + B28_Y2_DATA_REG_4 = 0x0e7c,/* 32 bit ASF/Host Data Register 4 */
4025 +};
4026 +
4027 +/* Status BMU Registers (Yukon-2 only)*/
4028 +enum {
4029 + STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */
4030 + STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */
4031 +
4032 + STAT_LIST_ADDR_LO= 0x0e88,/* 32 bit Status List Start Addr (low) */
4033 + STAT_LIST_ADDR_HI= 0x0e8c,/* 32 bit Status List Start Addr (high) */
4034 + STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */
4035 + STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */
4036 + STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */
4037 + STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */
4038 + STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */
4039 + STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */
4040 +
4041 +/* FIFO Control/Status Registers (Yukon-2 only)*/
4042 + STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */
4043 + STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */
4044 + STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */
4045 + STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */
4046 + STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */
4047 + STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */
4048 + STAT_FIFO_ISR_WM= 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */
4049 +
4050 +/* Level and ISR Timer Registers (Yukon-2 only)*/
4051 + STAT_LEV_TIMER_INI= 0x0eb0,/* 32 bit Level Timer Init. Value Reg */
4052 + STAT_LEV_TIMER_CNT= 0x0eb4,/* 32 bit Level Timer Counter Reg */
4053 + STAT_LEV_TIMER_CTRL= 0x0eb8,/* 8 bit Level Timer Control Reg */
4054 + STAT_LEV_TIMER_TEST= 0x0eb9,/* 8 bit Level Timer Test Reg */
4055 + STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */
4056 + STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */
4057 + STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */
4058 + STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */
4059 + STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */
4060 + STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */
4061 + STAT_ISR_TIMER_CTRL= 0x0ed8,/* 8 bit ISR Timer Control Reg */
4062 + STAT_ISR_TIMER_TEST= 0x0ed9,/* 8 bit ISR Timer Test Reg */
4063 +};
4064 +
4065 +enum {
4066 + LINKLED_OFF = 0x01,
4067 + LINKLED_ON = 0x02,
4068 + LINKLED_LINKSYNC_OFF = 0x04,
4069 + LINKLED_LINKSYNC_ON = 0x08,
4070 + LINKLED_BLINK_OFF = 0x10,
4071 + LINKLED_BLINK_ON = 0x20,
4072 +};
4073 +
4074 +/* GMAC and GPHY Control Registers (YUKON only) */
4075 +enum {
4076 + GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
4077 + GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
4078 + GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
4079 + GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
4080 + GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
4081 +
4082 +/* Wake-up Frame Pattern Match Control Registers (YUKON only) */
4083 +
4084 + WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
4085 +
4086 + WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
4087 + WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
4088 + WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
4089 + WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
4090 + WOL_PATT_PME = 0x0f2a,/* 8 bit WOL PME Match Enable (Yukon-2) */
4091 + WOL_PATT_ASFM = 0x0f2b,/* 8 bit WOL ASF Match Enable (Yukon-2) */
4092 + WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
4093 +
4094 +/* WOL Pattern Length Registers (YUKON only) */
4095 +
4096 + WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
4097 + WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
4098 +
4099 +/* WOL Pattern Counter Registers (YUKON only) */
4100 +
4101 +
4102 + WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
4103 + WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
4104 +};
4105 +
4106 +enum {
4107 + WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
4108 + WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
4109 +};
4110 +
4111 +enum {
4112 + BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
4113 + BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
4114 +};
4115 +
4116 +/*
4117 + * Marvel-PHY Registers, indirect addressed over GMAC
4118 + */
4119 +enum {
4120 + PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
4121 + PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
4122 + PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
4123 + PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
4124 + PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
4125 + PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
4126 + PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
4127 + PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
4128 + PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
4129 + /* Marvel-specific registers */
4130 + PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
4131 + PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
4132 + PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
4133 + PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
4134 + PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
4135 + PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
4136 + PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
4137 + PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
4138 + PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
4139 + PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
4140 + PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
4141 + PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
4142 + PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
4143 + PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
4144 + PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
4145 + PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
4146 + PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
4147 + PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
4148 +
4149 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
4150 + PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
4151 + PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
4152 + PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
4153 + PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
4154 + PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
4155 +};
4156 +
4157 +enum {
4158 + PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
4159 + PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
4160 + PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
4161 + PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
4162 + PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
4163 + PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
4164 + PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
4165 + PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
4166 + PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
4167 + PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
4168 +};
4169 +
4170 +enum {
4171 + PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
4172 + PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
4173 + PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
4174 +};
4175 +
4176 +enum {
4177 + PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
4178 +
4179 + PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
4180 + PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
4181 + PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */
4182 + PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
4183 + PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
4184 + PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
4185 + PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
4186 +};
4187 +
4188 +enum {
4189 + PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
4190 + PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
4191 + PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
4192 +};
4193 +
4194 +/* different Marvell PHY Ids */
4195 +enum {
4196 + PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
4197 +
4198 + PHY_BCOM_ID1_A1 = 0x6041,
4199 + PHY_BCOM_ID1_B2 = 0x6043,
4200 + PHY_BCOM_ID1_C0 = 0x6044,
4201 + PHY_BCOM_ID1_C5 = 0x6047,
4202 +
4203 + PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
4204 + PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
4205 + PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
4206 + PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
4207 +};
4208 +
4209 +/* Advertisement register bits */
4210 +enum {
4211 + PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
4212 + PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
4213 + PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */
4214 +
4215 + PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
4216 + PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */
4217 + PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */
4218 + PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
4219 + PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
4220 + PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
4221 + PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
4222 + PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
4223 + PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
4224 + PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
4225 + PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL |
4226 + PHY_AN_100HALF | PHY_AN_100FULL,
4227 +};
4228 +
4229 +/***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
4230 +/***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
4231 +enum {
4232 + PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
4233 + PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
4234 + PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
4235 + PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
4236 + PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
4237 + PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
4238 + /* Bit 9..8: reserved */
4239 + PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
4240 +};
4241 +
4242 +/** Marvell-Specific */
4243 +enum {
4244 + PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
4245 + PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */
4246 + PHY_M_AN_RF = 1<<13, /* Remote Fault */
4247 +
4248 + PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */
4249 + PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */
4250 + PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
4251 + PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
4252 + PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
4253 + PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
4254 + PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
4255 + PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
4256 +};
4257 +
4258 +/* special defines for FIBER (88E1011S only) */
4259 +enum {
4260 + PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
4261 + PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
4262 + PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
4263 + PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
4264 +};
4265 +
4266 +/* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
4267 +enum {
4268 + PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
4269 + PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
4270 + PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
4271 + PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
4272 +};
4273 +
4274 +/***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
4275 +enum {
4276 + PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
4277 + PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
4278 + PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
4279 + PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
4280 + PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
4281 + PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
4282 +};
4283 +
4284 +/***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
4285 +enum {
4286 + PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
4287 + PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
4288 + PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
4289 + PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */
4290 + PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
4291 + PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */
4292 + PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
4293 + PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */
4294 + PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */
4295 + PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */
4296 + PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */
4297 + PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */
4298 +};
4299 +
4300 +enum {
4301 + PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */
4302 + PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
4303 +};
4304 +
4305 +#define PHY_M_PC_MDI_XMODE(x) (((x)<<5) & PHY_M_PC_MDIX_MSK)
4306 +
4307 +enum {
4308 + PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
4309 + PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */
4310 + PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
4311 +};
4312 +
4313 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
4314 +enum {
4315 + PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
4316 + PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */
4317 + PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */
4318 + PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */
4319 + PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
4320 +
4321 + PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */
4322 + PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
4323 +
4324 + PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */
4325 + PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
4326 +};
4327 +
4328 +/***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
4329 +enum {
4330 + PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
4331 + PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */
4332 + PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */
4333 + PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */
4334 + PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */
4335 + PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */
4336 + PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */
4337 + PHY_M_PS_LINK_UP = 1<<10, /* Link Up */
4338 + PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
4339 + PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */
4340 + PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */
4341 + PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */
4342 + PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */
4343 + PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */
4344 + PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */
4345 + PHY_M_PS_JABBER = 1<<0, /* Jabber */
4346 +};
4347 +
4348 +#define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
4349 +
4350 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
4351 +enum {
4352 + PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */
4353 + PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
4354 +};
4355 +
4356 +enum {
4357 + PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
4358 + PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */
4359 + PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */
4360 + PHY_M_IS_AN_PR = 1<<12, /* Page Received */
4361 + PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
4362 + PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */
4363 + PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */
4364 + PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */
4365 + PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */
4366 + PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */
4367 + PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */
4368 + PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */
4369 +
4370 + PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */
4371 + PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */
4372 + PHY_M_IS_JABBER = 1<<0, /* Jabber */
4373 +
4374 + PHY_M_DEF_MSK = PHY_M_IS_LSP_CHANGE | PHY_M_IS_LST_CHANGE
4375 + | PHY_M_IS_FIFO_ERROR,
4376 + PHY_M_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
4377 +};
4378 +
4379 +
4380 +/***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
4381 +enum {
4382 + PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
4383 + PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
4384 +
4385 + PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
4386 + PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
4387 + /* (88E1011 only) */
4388 + PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */
4389 + /* (88E1011 only) */
4390 + PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */
4391 + /* (88E1111 only) */
4392 + PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
4393 + /* !!! Errata in spec. (1 = disable) */
4394 + PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
4395 + PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */
4396 + PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
4397 + PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
4398 + PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
4399 + PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};
4400 +
4401 +#define PHY_M_EC_M_DSC(x) ((x)<<10 & PHY_M_EC_M_DSC_MSK)
4402 + /* 00=1x; 01=2x; 10=3x; 11=4x */
4403 +#define PHY_M_EC_S_DSC(x) ((x)<<8 & PHY_M_EC_S_DSC_MSK)
4404 + /* 00=dis; 01=1x; 10=2x; 11=3x */
4405 +#define PHY_M_EC_DSC_2(x) ((x)<<9 & PHY_M_EC_M_DSC_MSK2)
4406 + /* 000=1x; 001=2x; 010=3x; 011=4x */
4407 +#define PHY_M_EC_MAC_S(x) ((x)<<4 & PHY_M_EC_MAC_S_MSK)
4408 + /* 01X=0; 110=2.5; 111=25 (MHz) */
4409 +
4410 +/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
4411 +enum {
4412 + PHY_M_PC_DIS_LINK_Pa = 1<<15,/* Disable Link Pulses */
4413 + PHY_M_PC_DSC_MSK = 7<<12,/* Bit 14..12: Downshift Counter */
4414 + PHY_M_PC_DOWN_S_ENA = 1<<11,/* Downshift Enable */
4415 +};
4416 +/* !!! Errata in spec. (1 = disable) */
4417 +
4418 +#define PHY_M_PC_DSC(x) (((x)<<12) & PHY_M_PC_DSC_MSK)
4419 + /* 100=5x; 101=6x; 110=7x; 111=8x */
4420 +enum {
4421 + MAC_TX_CLK_0_MHZ = 2,
4422 + MAC_TX_CLK_2_5_MHZ = 6,
4423 + MAC_TX_CLK_25_MHZ = 7,
4424 +};
4425 +
4426 +/***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
4427 +enum {
4428 + PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */
4429 + PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
4430 + PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
4431 + PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
4432 + PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
4433 + PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
4434 + PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
4435 + /* (88E1111 only) */
4436 +};
4437 +
4438 +enum {
4439 + PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */
4440 + /* (88E1011 only) */
4441 + PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
4442 + PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
4443 + PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
4444 + PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
4445 + PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
4446 +};
4447 +
4448 +#define PHY_M_LED_PULS_DUR(x) (((x)<<12) & PHY_M_LEDC_PULS_MSK)
4449 +
4450 +/***** PHY_MARV_PHY_STAT (page 3)16 bit r/w Polarity Control Reg. *****/
4451 +enum {
4452 + PHY_M_POLC_LS1M_MSK = 0xf<<12, /* Bit 15..12: LOS,STAT1 Mix % Mask */
4453 + PHY_M_POLC_IS0M_MSK = 0xf<<8, /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
4454 + PHY_M_POLC_LOS_MSK = 0x3<<6, /* Bit 7.. 6: LOS Pol. Ctrl. Mask */
4455 + PHY_M_POLC_INIT_MSK = 0x3<<4, /* Bit 5.. 4: INIT Pol. Ctrl. Mask */
4456 + PHY_M_POLC_STA1_MSK = 0x3<<2, /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */
4457 + PHY_M_POLC_STA0_MSK = 0x3, /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */
4458 +};
4459 +
4460 +#define PHY_M_POLC_LS1_P_MIX(x) (((x)<<12) & PHY_M_POLC_LS1M_MSK)
4461 +#define PHY_M_POLC_IS0_P_MIX(x) (((x)<<8) & PHY_M_POLC_IS0M_MSK)
4462 +#define PHY_M_POLC_LOS_CTRL(x) (((x)<<6) & PHY_M_POLC_LOS_MSK)
4463 +#define PHY_M_POLC_INIT_CTRL(x) (((x)<<4) & PHY_M_POLC_INIT_MSK)
4464 +#define PHY_M_POLC_STA1_CTRL(x) (((x)<<2) & PHY_M_POLC_STA1_MSK)
4465 +#define PHY_M_POLC_STA0_CTRL(x) (((x)<<0) & PHY_M_POLC_STA0_MSK)
4466 +
4467 +enum {
4468 + PULS_NO_STR = 0,/* no pulse stretching */
4469 + PULS_21MS = 1,/* 21 ms to 42 ms */
4470 + PULS_42MS = 2,/* 42 ms to 84 ms */
4471 + PULS_84MS = 3,/* 84 ms to 170 ms */
4472 + PULS_170MS = 4,/* 170 ms to 340 ms */
4473 + PULS_340MS = 5,/* 340 ms to 670 ms */
4474 + PULS_670MS = 6,/* 670 ms to 1.3 s */
4475 + PULS_1300MS = 7,/* 1.3 s to 2.7 s */
4476 +};
4477 +
4478 +#define PHY_M_LED_BLINK_RT(x) (((x)<<8) & PHY_M_LEDC_BL_R_MSK)
4479 +
4480 +enum {
4481 + BLINK_42MS = 0,/* 42 ms */
4482 + BLINK_84MS = 1,/* 84 ms */
4483 + BLINK_170MS = 2,/* 170 ms */
4484 + BLINK_340MS = 3,/* 340 ms */
4485 + BLINK_670MS = 4,/* 670 ms */
4486 +};
4487 +
4488 +/***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
4489 +#define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */
4490 + /* Bit 13..12: reserved */
4491 +#define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */
4492 +#define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */
4493 +#define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */
4494 +#define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */
4495 +#define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */
4496 +#define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */
4497 +
4498 +enum {
4499 + MO_LED_NORM = 0,
4500 + MO_LED_BLINK = 1,
4501 + MO_LED_OFF = 2,
4502 + MO_LED_ON = 3,
4503 +};
4504 +
4505 +/***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
4506 +enum {
4507 + PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */
4508 + PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */
4509 + PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
4510 + PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */
4511 + PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */
4512 +};
4513 +
4514 +/***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
4515 +enum {
4516 + PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
4517 + PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */
4518 + PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */
4519 + PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */
4520 + PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */
4521 + PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */
4522 + PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */
4523 + /* (88E1111 only) */
4524 +
4525 + PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
4526 + PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */
4527 + PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
4528 +};
4529 +
4530 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
4531 +/***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
4532 + /* Bit 15..12: reserved (used internally) */
4533 +enum {
4534 + PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
4535 + PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
4536 + PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
4537 +};
4538 +
4539 +#define PHY_M_FELP_LED2_CTRL(x) (((x)<<8) & PHY_M_FELP_LED2_MSK)
4540 +#define PHY_M_FELP_LED1_CTRL(x) (((x)<<4) & PHY_M_FELP_LED1_MSK)
4541 +#define PHY_M_FELP_LED0_CTRL(x) (((x)<<0) & PHY_M_FELP_LED0_MSK)
4542 +
4543 +enum {
4544 + LED_PAR_CTRL_COLX = 0x00,
4545 + LED_PAR_CTRL_ERROR = 0x01,
4546 + LED_PAR_CTRL_DUPLEX = 0x02,
4547 + LED_PAR_CTRL_DP_COL = 0x03,
4548 + LED_PAR_CTRL_SPEED = 0x04,
4549 + LED_PAR_CTRL_LINK = 0x05,
4550 + LED_PAR_CTRL_TX = 0x06,
4551 + LED_PAR_CTRL_RX = 0x07,
4552 + LED_PAR_CTRL_ACT = 0x08,
4553 + LED_PAR_CTRL_LNK_RX = 0x09,
4554 + LED_PAR_CTRL_LNK_AC = 0x0a,
4555 + LED_PAR_CTRL_ACT_BL = 0x0b,
4556 + LED_PAR_CTRL_TX_BL = 0x0c,
4557 + LED_PAR_CTRL_RX_BL = 0x0d,
4558 + LED_PAR_CTRL_COL_BL = 0x0e,
4559 + LED_PAR_CTRL_INACT = 0x0f
4560 +};
4561 +
4562 +/*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
4563 +enum {
4564 + PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */
4565 + PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
4566 + PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
4567 +};
4568 +
4569 +/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
4570 +/***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
4571 +enum {
4572 + PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */
4573 + PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */
4574 + PHY_M_MAC_MD_COPPER = 5,/* Copper only */
4575 + PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */
4576 +};
4577 +#define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK)
4578 +
4579 +/***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
4580 +enum {
4581 + PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */
4582 + PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
4583 + PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */
4584 + PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
4585 +};
4586 +
4587 +#define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK)
4588 +#define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK)
4589 +#define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK)
4590 +#define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK)
4591 +
4592 +/* GMAC registers */
4593 +/* Port Registers */
4594 +enum {
4595 + GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
4596 + GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
4597 + GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
4598 + GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
4599 + GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
4600 + GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
4601 + GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
4602 +/* Source Address Registers */
4603 + GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
4604 + GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
4605 + GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
4606 + GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
4607 + GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
4608 + GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
4609 +
4610 +/* Multicast Address Hash Registers */
4611 + GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
4612 + GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
4613 + GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
4614 + GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
4615 +
4616 +/* Interrupt Source Registers */
4617 + GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
4618 + GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
4619 + GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
4620 +
4621 +/* Interrupt Mask Registers */
4622 + GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
4623 + GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
4624 + GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
4625 +
4626 +/* Serial Management Interface (SMI) Registers */
4627 + GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
4628 + GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
4629 + GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
4630 +};
4631 +
4632 +/* MIB Counters */
4633 +#define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */
4634 +#define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */
4635 +
4636 +/*
4637 + * MIB Counters base address definitions (low word) -
4638 + * use offset 4 for access to high word (32 bit r/o)
4639 + */
4640 +enum {
4641 + GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */
4642 + GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */
4643 + GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
4644 + GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
4645 + GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
4646 + /* GM_MIB_CNT_BASE + 40: reserved */
4647 + GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
4648 + GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
4649 + GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
4650 + GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */
4651 + GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
4652 + GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
4653 + GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
4654 + GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */
4655 + GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */
4656 + GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */
4657 + GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */
4658 + GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */
4659 + GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */
4660 + GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152, /* Rx Frame too Long Error */
4661 + GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160, /* Rx Jabber Packet Frame */
4662 + /* GM_MIB_CNT_BASE + 168: reserved */
4663 + GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176, /* Rx FIFO overflow Event */
4664 + /* GM_MIB_CNT_BASE + 184: reserved */
4665 + GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192, /* Unicast Frames Xmitted OK */
4666 + GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200, /* Broadcast Frames Xmitted OK */
4667 + GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208, /* Pause MAC Ctrl Frames Xmitted */
4668 + GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216, /* Multicast Frames Xmitted OK */
4669 + GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224, /* Octets Transmitted OK Low */
4670 + GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232, /* Octets Transmitted OK High */
4671 + GM_TXF_64B = GM_MIB_CNT_BASE + 240, /* 64 Byte Tx Frame */
4672 + GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */
4673 + GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */
4674 + GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */
4675 + GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */
4676 + GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */
4677 + GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */
4678 +
4679 + GM_TXF_COL = GM_MIB_CNT_BASE + 304, /* Tx Collision */
4680 + GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312, /* Tx Late Collision */
4681 + GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320, /* Tx aborted due to Exces. Col. */
4682 + GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328, /* Tx Multiple Collision */
4683 + GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336, /* Tx Single Collision */
4684 + GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344, /* Tx FIFO Underrun Event */
4685 +};
4686 +
4687 +/* GMAC Bit Definitions */
4688 +/* GM_GP_STAT 16 bit r/o General Purpose Status Register */
4689 +enum {
4690 + GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */
4691 + GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
4692 + GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
4693 + GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
4694 + GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
4695 + GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
4696 + GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occured */
4697 + GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occured */
4698 +
4699 + GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
4700 + GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
4701 + GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */
4702 + GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
4703 + GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
4704 +};
4705 +
4706 +/* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
4707 +enum {
4708 + GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
4709 + GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
4710 + GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
4711 + GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
4712 + GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
4713 + GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
4714 + GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
4715 + GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */
4716 + GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */
4717 + GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
4718 + GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
4719 + GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */
4720 + GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
4721 + GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
4722 + GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
4723 +};
4724 +
4725 +#define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
4726 +#define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
4727 +
4728 +/* GM_TX_CTRL 16 bit r/w Transmit Control Register */
4729 +enum {
4730 + GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
4731 + GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
4732 + GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
4733 + GM_TXCR_COL_THR_MSK = 1<<10, /* Bit 12..10: Collision Threshold */
4734 +};
4735 +
4736 +#define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
4737 +#define TX_COL_DEF 0x04
4738 +
4739 +/* GM_RX_CTRL 16 bit r/w Receive Control Register */
4740 +enum {
4741 + GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
4742 + GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
4743 + GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
4744 + GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
4745 +};
4746 +
4747 +/* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
4748 +enum {
4749 + GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
4750 + GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */
4751 + GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */
4752 + GM_TXPA_BO_LIM_MSK = 0x0f, /* Bit 3.. 0: Backoff Limit Mask */
4753 +
4754 + TX_JAM_LEN_DEF = 0x03,
4755 + TX_JAM_IPG_DEF = 0x0b,
4756 + TX_IPG_JAM_DEF = 0x1c,
4757 + TX_BOF_LIM_DEF = 0x04,
4758 +};
4759 +
4760 +#define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK)
4761 +#define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK)
4762 +#define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK)
4763 +#define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK)
4764 +
4765 +
4766 +/* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
4767 +enum {
4768 + GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
4769 + GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */
4770 + GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */
4771 + GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
4772 + GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
4773 +};
4774 +
4775 +#define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
4776 +#define DATA_BLIND_DEF 0x04
4777 +
4778 +#define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
4779 +#define IPG_DATA_DEF 0x1e
4780 +
4781 +/* GM_SMI_CTRL 16 bit r/w SMI Control Register */
4782 +enum {
4783 + GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */
4784 + GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */
4785 + GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
4786 + GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
4787 + GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
4788 +};
4789 +
4790 +#define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
4791 +#define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK)
4792 +
4793 +/* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
4794 +enum {
4795 + GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
4796 + GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
4797 +};
4798 +
4799 +/* Receive Frame Status Encoding */
4800 +enum {
4801 + GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */
4802 + GMR_FS_VLAN = 1<<13, /* VLAN Packet */
4803 + GMR_FS_JABBER = 1<<12, /* Jabber Packet */
4804 + GMR_FS_UN_SIZE = 1<<11, /* Undersize Packet */
4805 + GMR_FS_MC = 1<<10, /* Multicast Packet */
4806 + GMR_FS_BC = 1<<9, /* Broadcast Packet */
4807 + GMR_FS_RX_OK = 1<<8, /* Receive OK (Good Packet) */
4808 + GMR_FS_GOOD_FC = 1<<7, /* Good Flow-Control Packet */
4809 + GMR_FS_BAD_FC = 1<<6, /* Bad Flow-Control Packet */
4810 + GMR_FS_MII_ERR = 1<<5, /* MII Error */
4811 + GMR_FS_LONG_ERR = 1<<4, /* Too Long Packet */
4812 + GMR_FS_FRAGMENT = 1<<3, /* Fragment */
4813 +
4814 + GMR_FS_CRC_ERR = 1<<1, /* CRC Error */
4815 + GMR_FS_RX_FF_OV = 1<<0, /* Rx FIFO Overflow */
4816 +
4817 + GMR_FS_ANY_ERR = GMR_FS_RX_FF_OV | GMR_FS_CRC_ERR |
4818 + GMR_FS_FRAGMENT | GMR_FS_LONG_ERR |
4819 + GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
4820 + GMR_FS_UN_SIZE | GMR_FS_JABBER,
4821 +};
4822 +
4823 +/* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
4824 +enum {
4825 + RX_TRUNC_ON = 1<<27, /* enable packet truncation */
4826 + RX_TRUNC_OFF = 1<<26, /* disable packet truncation */
4827 + RX_VLAN_STRIP_ON = 1<<25, /* enable VLAN stripping */
4828 + RX_VLAN_STRIP_OFF = 1<<24, /* disable VLAN stripping */
4829 +
4830 + GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */
4831 + GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */
4832 + GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */
4833 +
4834 + GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */
4835 + GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */
4836 + GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */
4837 + GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
4838 + GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
4839 + GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
4840 + GMF_CLI_RX_C = 1<<4, /* Clear IRQ Rx Frame Complete */
4841 +
4842 + GMF_OPER_ON = 1<<3, /* Operational Mode On */
4843 + GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
4844 + GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
4845 + GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */
4846 +
4847 + RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */
4848 +
4849 + GMF_RX_CTRL_DEF = GMF_OPER_ON | GMF_RX_F_FL_ON,
4850 +};
4851 +
4852 +
4853 +/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
4854 +enum {
4855 + TX_STFW_DIS = 1<<31,/* Disable Store & Forward (Yukon-EC Ultra) */
4856 + TX_STFW_ENA = 1<<30,/* Enable Store & Forward (Yukon-EC Ultra) */
4857 +
4858 + TX_VLAN_TAG_ON = 1<<25,/* enable VLAN tagging */
4859 + TX_VLAN_TAG_OFF = 1<<24,/* disable VLAN tagging */
4860 +
4861 + GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */
4862 + GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */
4863 + GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */
4864 +
4865 + GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */
4866 + GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
4867 + GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */
4868 +};
4869 +
4870 +/* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
4871 +enum {
4872 + GMT_ST_START = 1<<2, /* Start Time Stamp Timer */
4873 + GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */
4874 + GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */
4875 +};
4876 +
4877 +/* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */
4878 +enum {
4879 + Y2_ASF_OS_PRES = 1<<4, /* ASF operation system present */
4880 + Y2_ASF_RESET = 1<<3, /* ASF system in reset state */
4881 + Y2_ASF_RUNNING = 1<<2, /* ASF system operational */
4882 + Y2_ASF_CLR_HSTI = 1<<1, /* Clear ASF IRQ */
4883 + Y2_ASF_IRQ = 1<<0, /* Issue an IRQ to ASF system */
4884 +
4885 + Y2_ASF_UC_STATE = 3<<2, /* ASF uC State */
4886 + Y2_ASF_CLK_HALT = 0, /* ASF system clock stopped */
4887 +};
4888 +
4889 +/* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */
4890 +enum {
4891 + Y2_ASF_CLR_ASFI = 1<<1, /* Clear host IRQ */
4892 + Y2_ASF_HOST_IRQ = 1<<0, /* Issue an IRQ to HOST system */
4893 +};
4894 +
4895 +/* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
4896 +enum {
4897 + SC_STAT_CLR_IRQ = 1<<4, /* Status Burst IRQ clear */
4898 + SC_STAT_OP_ON = 1<<3, /* Operational Mode On */
4899 + SC_STAT_OP_OFF = 1<<2, /* Operational Mode Off */
4900 + SC_STAT_RST_CLR = 1<<1, /* Clear Status Unit Reset (Enable) */
4901 + SC_STAT_RST_SET = 1<<0, /* Set Status Unit Reset */
4902 +};
4903 +
4904 +/* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
4905 +enum {
4906 + GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */
4907 + GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
4908 + GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */
4909 + GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */
4910 + GMC_PAUSE_ON = 1<<3, /* Pause On */
4911 + GMC_PAUSE_OFF = 1<<2, /* Pause Off */
4912 + GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */
4913 + GMC_RST_SET = 1<<0, /* Set GMAC Reset */
4914 +};
4915 +
4916 +/* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
4917 +enum {
4918 + GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
4919 + GPC_INT_POL_HI = 1<<27, /* IRQ Polarity is Active HIGH */
4920 + GPC_75_OHM = 1<<26, /* Use 75 Ohm Termination instead of 50 */
4921 + GPC_DIS_FC = 1<<25, /* Disable Automatic Fiber/Copper Detection */
4922 + GPC_DIS_SLEEP = 1<<24, /* Disable Energy Detect */
4923 + GPC_HWCFG_M_3 = 1<<23, /* HWCFG_MODE[3] */
4924 + GPC_HWCFG_M_2 = 1<<22, /* HWCFG_MODE[2] */
4925 + GPC_HWCFG_M_1 = 1<<21, /* HWCFG_MODE[1] */
4926 + GPC_HWCFG_M_0 = 1<<20, /* HWCFG_MODE[0] */
4927 + GPC_ANEG_0 = 1<<19, /* ANEG[0] */
4928 + GPC_ENA_XC = 1<<18, /* Enable MDI crossover */
4929 + GPC_DIS_125 = 1<<17, /* Disable 125 MHz clock */
4930 + GPC_ANEG_3 = 1<<16, /* ANEG[3] */
4931 + GPC_ANEG_2 = 1<<15, /* ANEG[2] */
4932 + GPC_ANEG_1 = 1<<14, /* ANEG[1] */
4933 + GPC_ENA_PAUSE = 1<<13, /* Enable Pause (SYM_OR_REM) */
4934 + GPC_PHYADDR_4 = 1<<12, /* Bit 4 of Phy Addr */
4935 + GPC_PHYADDR_3 = 1<<11, /* Bit 3 of Phy Addr */
4936 + GPC_PHYADDR_2 = 1<<10, /* Bit 2 of Phy Addr */
4937 + GPC_PHYADDR_1 = 1<<9, /* Bit 1 of Phy Addr */
4938 + GPC_PHYADDR_0 = 1<<8, /* Bit 0 of Phy Addr */
4939 + /* Bits 7..2: reserved */
4940 + GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */
4941 + GPC_RST_SET = 1<<0, /* Set GPHY Reset */
4942 +};
4943 +
4944 +/* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
4945 +/* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
4946 +enum {
4947 + GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */
4948 + GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */
4949 + GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */
4950 + GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */
4951 + GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */
4952 + GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
4953 +
4954 +#define GMAC_DEF_MSK GM_IS_TX_FF_UR
4955 +
4956 +/* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
4957 + /* Bits 15.. 2: reserved */
4958 + GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */
4959 + GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */
4960 +
4961 +
4962 +/* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
4963 + WOL_CTL_LINK_CHG_OCC = 1<<15,
4964 + WOL_CTL_MAGIC_PKT_OCC = 1<<14,
4965 + WOL_CTL_PATTERN_OCC = 1<<13,
4966 + WOL_CTL_CLEAR_RESULT = 1<<12,
4967 + WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11,
4968 + WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10,
4969 + WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9,
4970 + WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8,
4971 + WOL_CTL_ENA_PME_ON_PATTERN = 1<<7,
4972 + WOL_CTL_DIS_PME_ON_PATTERN = 1<<6,
4973 + WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5,
4974 + WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4,
4975 + WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3,
4976 + WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2,
4977 + WOL_CTL_ENA_PATTERN_UNIT = 1<<1,
4978 + WOL_CTL_DIS_PATTERN_UNIT = 1<<0,
4979 +};
4980 +
4981 +#define WOL_CTL_DEFAULT \
4982 + (WOL_CTL_DIS_PME_ON_LINK_CHG | \
4983 + WOL_CTL_DIS_PME_ON_PATTERN | \
4984 + WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
4985 + WOL_CTL_DIS_LINK_CHG_UNIT | \
4986 + WOL_CTL_DIS_PATTERN_UNIT | \
4987 + WOL_CTL_DIS_MAGIC_PKT_UNIT)
4988 +
4989 +/* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
4990 +#define WOL_CTL_PATT_ENA(x) (1 << (x))
4991 +
4992 +
4993 +/* Control flags */
4994 +enum {
4995 + UDPTCP = 1<<0,
4996 + CALSUM = 1<<1,
4997 + WR_SUM = 1<<2,
4998 + INIT_SUM= 1<<3,
4999 + LOCK_SUM= 1<<4,
5000 + INS_VLAN= 1<<5,
5001 + FRC_STAT= 1<<6,
5002 + EOP = 1<<7,
5003 +};
5004 +
5005 +enum {
5006 + HW_OWNER = 1<<7,
5007 + OP_TCPWRITE = 0x11,
5008 + OP_TCPSTART = 0x12,
5009 + OP_TCPINIT = 0x14,
5010 + OP_TCPLCK = 0x18,
5011 + OP_TCPCHKSUM = OP_TCPSTART,
5012 + OP_TCPIS = OP_TCPINIT | OP_TCPSTART,
5013 + OP_TCPLW = OP_TCPLCK | OP_TCPWRITE,
5014 + OP_TCPLSW = OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE,
5015 + OP_TCPLISW = OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE,
5016 +
5017 + OP_ADDR64 = 0x21,
5018 + OP_VLAN = 0x22,
5019 + OP_ADDR64VLAN = OP_ADDR64 | OP_VLAN,
5020 + OP_LRGLEN = 0x24,
5021 + OP_LRGLENVLAN = OP_LRGLEN | OP_VLAN,
5022 + OP_BUFFER = 0x40,
5023 + OP_PACKET = 0x41,
5024 + OP_LARGESEND = 0x43,
5025 +
5026 +/* YUKON-2 STATUS opcodes defines */
5027 + OP_RXSTAT = 0x60,
5028 + OP_RXTIMESTAMP = 0x61,
5029 + OP_RXVLAN = 0x62,
5030 + OP_RXCHKS = 0x64,
5031 + OP_RXCHKSVLAN = OP_RXCHKS | OP_RXVLAN,
5032 + OP_RXTIMEVLAN = OP_RXTIMESTAMP | OP_RXVLAN,
5033 + OP_RSS_HASH = 0x65,
5034 + OP_TXINDEXLE = 0x68,
5035 +};
5036 +
5037 +/* Yukon 2 hardware interface
5038 + * Not tested on big endian
5039 + */
5040 +struct sky2_tx_le {
5041 + union {
5042 + __le32 addr;
5043 + struct {
5044 + __le16 offset;
5045 + __le16 start;
5046 + } csum __attribute((packed));
5047 + struct {
5048 + __le16 size;
5049 + __le16 rsvd;
5050 + } tso __attribute((packed));
5051 + } tx;
5052 + __le16 length; /* also vlan tag or checksum start */
5053 + u8 ctrl;
5054 + u8 opcode;
5055 +} __attribute((packed));
5056 +
5057 +struct sky2_rx_le {
5058 + __le32 addr;
5059 + __le16 length;
5060 + u8 ctrl;
5061 + u8 opcode;
5062 +} __attribute((packed));;
5063 +
5064 +struct sky2_status_le {
5065 + __le32 status; /* also checksum */
5066 + __le16 length; /* also vlan tag */
5067 + u8 link;
5068 + u8 opcode;
5069 +} __attribute((packed));
5070 +
5071 +struct tx_ring_info {
5072 + struct sk_buff *skb;
5073 + DECLARE_PCI_UNMAP_ADDR(mapaddr);
5074 + u16 idx;
5075 +};
5076 +
5077 +struct ring_info {
5078 + struct sk_buff *skb;
5079 + dma_addr_t mapaddr;
5080 +};
5081 +
5082 +struct sky2_port {
5083 + struct sky2_hw *hw;
5084 + struct net_device *netdev;
5085 + unsigned port;
5086 + u32 msg_enable;
5087 +
5088 + spinlock_t tx_lock ____cacheline_aligned_in_smp;
5089 + struct tx_ring_info *tx_ring;
5090 + struct sky2_tx_le *tx_le;
5091 + u16 tx_cons; /* next le to check */
5092 + u16 tx_prod; /* next le to use */
5093 + u32 tx_addr64;
5094 + u16 tx_pending;
5095 + u16 tx_last_put;
5096 + u16 tx_last_mss;
5097 +
5098 + struct ring_info *rx_ring ____cacheline_aligned_in_smp;
5099 + struct sky2_rx_le *rx_le;
5100 + u32 rx_addr64;
5101 + u16 rx_next; /* next re to check */
5102 + u16 rx_put; /* next le index to use */
5103 + u16 rx_pending;
5104 + u16 rx_last_put;
5105 + u16 rx_bufsize;
5106 +#ifdef SKY2_VLAN_TAG_USED
5107 + u16 rx_tag;
5108 + struct vlan_group *vlgrp;
5109 +#endif
5110 +
5111 + dma_addr_t rx_le_map;
5112 + dma_addr_t tx_le_map;
5113 + u32 advertising; /* ADVERTISED_ bits */
5114 + u16 speed; /* SPEED_1000, SPEED_100, ... */
5115 + u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */
5116 + u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */
5117 + u8 rx_pause;
5118 + u8 tx_pause;
5119 + u8 rx_csum;
5120 + u8 wol;
5121 +
5122 + struct net_device_stats net_stats;
5123 +
5124 + struct work_struct phy_task;
5125 + struct semaphore phy_sema;
5126 +};
5127 +
5128 +struct sky2_hw {
5129 + void __iomem *regs;
5130 + struct pci_dev *pdev;
5131 + u32 intr_mask;
5132 + struct net_device *dev[2];
5133 +
5134 + int pm_cap;
5135 + u8 chip_id;
5136 + u8 chip_rev;
5137 + u8 copper;
5138 + u8 ports;
5139 +
5140 + struct sky2_status_le *st_le;
5141 + u32 st_idx;
5142 + dma_addr_t st_dma;
5143 +};
5144 +
5145 +/* Register accessor for memory mapped device */
5146 +static inline u32 sky2_read32(const struct sky2_hw *hw, unsigned reg)
5147 +{
5148 + return readl(hw->regs + reg);
5149 +}
5150 +
5151 +static inline u16 sky2_read16(const struct sky2_hw *hw, unsigned reg)
5152 +{
5153 + return readw(hw->regs + reg);
5154 +}
5155 +
5156 +static inline u8 sky2_read8(const struct sky2_hw *hw, unsigned reg)
5157 +{
5158 + return readb(hw->regs + reg);
5159 +}
5160 +
5161 +/* This should probably go away, bus based tweeks suck */
5162 +static inline int is_pciex(const struct sky2_hw *hw)
5163 +{
5164 + u32 status;
5165 + pci_read_config_dword(hw->pdev, PCI_DEV_STATUS, &status);
5166 + return (status & PCI_OS_PCI_X) == 0;
5167 +}
5168 +
5169 +static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val)
5170 +{
5171 + writel(val, hw->regs + reg);
5172 +}
5173 +
5174 +static inline void sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val)
5175 +{
5176 + writew(val, hw->regs + reg);
5177 +}
5178 +
5179 +static inline void sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val)
5180 +{
5181 + writeb(val, hw->regs + reg);
5182 +}
5183 +
5184 +/* Yukon PHY related registers */
5185 +#define SK_GMAC_REG(port,reg) \
5186 + (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
5187 +#define GM_PHY_RETRIES 100
5188 +
5189 +static inline u16 gma_read16(const struct sky2_hw *hw, unsigned port, unsigned reg)
5190 +{
5191 + return sky2_read16(hw, SK_GMAC_REG(port,reg));
5192 +}
5193 +
5194 +static inline u32 gma_read32(struct sky2_hw *hw, unsigned port, unsigned reg)
5195 +{
5196 + unsigned base = SK_GMAC_REG(port, reg);
5197 + return (u32) sky2_read16(hw, base)
5198 + | (u32) sky2_read16(hw, base+4) << 16;
5199 +}
5200 +
5201 +static inline void gma_write16(const struct sky2_hw *hw, unsigned port, int r, u16 v)
5202 +{
5203 + sky2_write16(hw, SK_GMAC_REG(port,r), v);
5204 +}
5205 +
5206 +static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg,
5207 + const u8 *addr)
5208 +{
5209 + gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8));
5210 + gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
5211 + gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
5212 +}
5213 +#endif
5214 --- linux-2.6.15/drivers/net/Makefile 2006-01-03 03:21:10.000000000 +0000
5215 +++ linux-dsd/drivers/net/Makefile 2006-01-03 18:10:52.000000000 +0000
5216 @@ -59,6 +59,7 @@ spidernet-y += spider_net.o spider_net_e
5217 obj-$(CONFIG_SPIDER_NET) += spidernet.o
5218 obj-$(CONFIG_TC35815) += tc35815.o
5219 obj-$(CONFIG_SKGE) += skge.o
5220 +obj-$(CONFIG_SKY2) += sky2.o
5221 obj-$(CONFIG_SK98LIN) += sk98lin/
5222 obj-$(CONFIG_SKFP) += skfp/
5223 obj-$(CONFIG_VIA_RHINE) += via-rhine.o
5224 --- linux-2.6.15/drivers/net/Kconfig 2006-01-03 03:21:10.000000000 +0000
5225 +++ linux-dsd/drivers/net/Kconfig 2006-01-03 18:10:52.000000000 +0000
5226 @@ -2008,7 +2008,17 @@ config SKGE
5227
5228 It does not support the link failover and network management
5229 features that "portable" vendor supplied sk98lin driver does.
5230 -
5231 +
5232 +config SKY2
5233 + tristate "SysKonnect Yukon2 support (EXPERIMENTAL)"
5234 + depends on PCI && EXPERIMENTAL
5235 + select CRC32
5236 + ---help---
5237 + This driver support the Marvell Yukon 2 Gigabit Ethernet adapter.
5238 +
5239 + To compile this driver as a module, choose M here: the module
5240 + will be called sky2. This is recommended.
5241 +
5242 config SK98LIN
5243 tristate "Marvell Yukon Chipset / SysKonnect SK-98xx Support"
5244 depends on PCI
5245 --- linux-2.6.15/include/linux/netdevice.h 2006-01-03 03:21:10.000000000 +0000
5246 +++ linux-dsd/include/linux/netdevice.h 2006-01-03 18:10:52.000000000 +0000
5247 @@ -801,12 +801,16 @@ static inline u32 netif_msg_init(int deb
5248 return (1 << debug_value) - 1;
5249 }
5250
5251 -/* Schedule rx intr now? */
5252 +/* Test if receive needs to be scheduled */
5253 +static inline int __netif_rx_schedule_prep(struct net_device *dev)
5254 +{
5255 + return !test_and_set_bit(__LINK_STATE_RX_SCHED, &dev->state);
5256 +}
5257
5258 +/* Test if receive needs to be scheduled but only if up */
5259 static inline int netif_rx_schedule_prep(struct net_device *dev)
5260 {
5261 - return netif_running(dev) &&
5262 - !test_and_set_bit(__LINK_STATE_RX_SCHED, &dev->state);
5263 + return netif_running(dev) && __netif_rx_schedule_prep(dev);
5264 }
5265
5266 /* Add interface to tail of rx poll list. This assumes that _prep has

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