/[linux-patches]/genpatches-2.6/tags/3.0-30/1023_linux-3.0.24.patch
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Contents of /genpatches-2.6/tags/3.0-30/1023_linux-3.0.24.patch

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Revision 2206 - (show annotations) (download)
Mon Sep 17 18:58:14 2012 UTC (2 years, 3 months ago) by mpagano
File size: 122304 byte(s)
3.0-30 release
1 diff --git a/Documentation/hwmon/jc42 b/Documentation/hwmon/jc42
2 index a22ecf4..52729a7 100644
3 --- a/Documentation/hwmon/jc42
4 +++ b/Documentation/hwmon/jc42
5 @@ -7,21 +7,29 @@ Supported chips:
6 Addresses scanned: I2C 0x18 - 0x1f
7 Datasheets:
8 http://www.analog.com/static/imported-files/data_sheets/ADT7408.pdf
9 - * IDT TSE2002B3, TS3000B3
10 - Prefix: 'tse2002b3', 'ts3000b3'
11 + * Atmel AT30TS00
12 + Prefix: 'at30ts00'
13 Addresses scanned: I2C 0x18 - 0x1f
14 Datasheets:
15 - http://www.idt.com/products/getdoc.cfm?docid=18715691
16 - http://www.idt.com/products/getdoc.cfm?docid=18715692
17 + http://www.atmel.com/Images/doc8585.pdf
18 + * IDT TSE2002B3, TSE2002GB2, TS3000B3, TS3000GB2
19 + Prefix: 'tse2002', 'ts3000'
20 + Addresses scanned: I2C 0x18 - 0x1f
21 + Datasheets:
22 + http://www.idt.com/sites/default/files/documents/IDT_TSE2002B3C_DST_20100512_120303152056.pdf
23 + http://www.idt.com/sites/default/files/documents/IDT_TSE2002GB2A1_DST_20111107_120303145914.pdf
24 + http://www.idt.com/sites/default/files/documents/IDT_TS3000B3A_DST_20101129_120303152013.pdf
25 + http://www.idt.com/sites/default/files/documents/IDT_TS3000GB2A1_DST_20111104_120303151012.pdf
26 * Maxim MAX6604
27 Prefix: 'max6604'
28 Addresses scanned: I2C 0x18 - 0x1f
29 Datasheets:
30 http://datasheets.maxim-ic.com/en/ds/MAX6604.pdf
31 - * Microchip MCP9805, MCP98242, MCP98243, MCP9843
32 - Prefixes: 'mcp9805', 'mcp98242', 'mcp98243', 'mcp9843'
33 + * Microchip MCP9804, MCP9805, MCP98242, MCP98243, MCP9843
34 + Prefixes: 'mcp9804', 'mcp9805', 'mcp98242', 'mcp98243', 'mcp9843'
35 Addresses scanned: I2C 0x18 - 0x1f
36 Datasheets:
37 + http://ww1.microchip.com/downloads/en/DeviceDoc/22203C.pdf
38 http://ww1.microchip.com/downloads/en/DeviceDoc/21977b.pdf
39 http://ww1.microchip.com/downloads/en/DeviceDoc/21996a.pdf
40 http://ww1.microchip.com/downloads/en/DeviceDoc/22153c.pdf
41 @@ -48,6 +56,12 @@ Supported chips:
42 Datasheets:
43 http://www.st.com/stonline/products/literature/ds/13447/stts424.pdf
44 http://www.st.com/stonline/products/literature/ds/13448/stts424e02.pdf
45 + * ST Microelectronics STTS2002, STTS3000
46 + Prefix: 'stts2002', 'stts3000'
47 + Addresses scanned: I2C 0x18 - 0x1f
48 + Datasheets:
49 + http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATASHEET/CD00225278.pdf
50 + http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATA_BRIEF/CD00270920.pdf
51 * JEDEC JC 42.4 compliant temperature sensor chips
52 Prefix: 'jc42'
53 Addresses scanned: I2C 0x18 - 0x1f
54 diff --git a/Makefile b/Makefile
55 index d14684e..7526032 100644
56 --- a/Makefile
57 +++ b/Makefile
58 @@ -1,6 +1,6 @@
59 VERSION = 3
60 PATCHLEVEL = 0
61 -SUBLEVEL = 23
62 +SUBLEVEL = 24
63 EXTRAVERSION =
64 NAME = Sneaky Weasel
65
66 diff --git a/arch/alpha/include/asm/futex.h b/arch/alpha/include/asm/futex.h
67 index e8a761a..f939794 100644
68 --- a/arch/alpha/include/asm/futex.h
69 +++ b/arch/alpha/include/asm/futex.h
70 @@ -108,7 +108,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
71 " lda $31,3b-2b(%0)\n"
72 " .previous\n"
73 : "+r"(ret), "=&r"(prev), "=&r"(cmp)
74 - : "r"(uaddr), "r"((long)oldval), "r"(newval)
75 + : "r"(uaddr), "r"((long)(int)oldval), "r"(newval)
76 : "memory");
77
78 *uval = prev;
79 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
80 index 2456bad..f9b212e 100644
81 --- a/arch/arm/Kconfig
82 +++ b/arch/arm/Kconfig
83 @@ -1179,7 +1179,7 @@ config ARM_ERRATA_743622
84 depends on CPU_V7
85 help
86 This option enables the workaround for the 743622 Cortex-A9
87 - (r2p0..r2p2) erratum. Under very rare conditions, a faulty
88 + (r2p*) erratum. Under very rare conditions, a faulty
89 optimisation in the Cortex-A9 Store Buffer may lead to data
90 corruption. This workaround sets a specific bit in the diagnostic
91 register of the Cortex-A9 which disables the Store Buffer
92 diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
93 index cf7e598..46c0449 100644
94 --- a/arch/arm/mach-dove/common.c
95 +++ b/arch/arm/mach-dove/common.c
96 @@ -31,6 +31,7 @@
97 #include <asm/mach/arch.h>
98 #include <linux/irq.h>
99 #include <plat/time.h>
100 +#include <plat/ehci-orion.h>
101 #include <plat/common.h>
102 #include "common.h"
103
104 @@ -74,7 +75,7 @@ void __init dove_map_io(void)
105 void __init dove_ehci0_init(void)
106 {
107 orion_ehci_init(&dove_mbus_dram_info,
108 - DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0);
109 + DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);
110 }
111
112 /*****************************************************************************
113 diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
114 index f3248cf..c5dbbb3 100644
115 --- a/arch/arm/mach-kirkwood/common.c
116 +++ b/arch/arm/mach-kirkwood/common.c
117 @@ -28,6 +28,7 @@
118 #include <plat/cache-feroceon-l2.h>
119 #include <plat/mvsdio.h>
120 #include <plat/orion_nand.h>
121 +#include <plat/ehci-orion.h>
122 #include <plat/common.h>
123 #include <plat/time.h>
124 #include "common.h"
125 @@ -74,7 +75,7 @@ void __init kirkwood_ehci_init(void)
126 {
127 kirkwood_clk_ctrl |= CGC_USB0;
128 orion_ehci_init(&kirkwood_mbus_dram_info,
129 - USB_PHYS_BASE, IRQ_KIRKWOOD_USB);
130 + USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA);
131 }
132
133
134 diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h
135 index ac78795..7afccf4 100644
136 --- a/arch/arm/mach-kirkwood/mpp.h
137 +++ b/arch/arm/mach-kirkwood/mpp.h
138 @@ -31,313 +31,313 @@
139 #define MPP_F6282_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 0, 1 )
140
141 #define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1, 1 )
142 -#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1, 1 )
143 -#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1, 1 )
144 +#define MPP0_NF_IO2 MPP( 0, 0x1, 0, 0, 1, 1, 1, 1, 1 )
145 +#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 0, 1, 1, 1, 1, 1 )
146
147 #define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1, 1 )
148 -#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1, 1 )
149 -#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1, 1 )
150 +#define MPP1_NF_IO3 MPP( 1, 0x1, 0, 0, 1, 1, 1, 1, 1 )
151 +#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 0, 1, 1, 1, 1, 1 )
152
153 #define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1, 1 )
154 -#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1, 1 )
155 -#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1, 1 )
156 +#define MPP2_NF_IO4 MPP( 2, 0x1, 0, 0, 1, 1, 1, 1, 1 )
157 +#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 0, 1, 1, 1, 1, 1 )
158
159 #define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1, 1 )
160 -#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1, 1 )
161 -#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1, 1 )
162 +#define MPP3_NF_IO5 MPP( 3, 0x1, 0, 0, 1, 1, 1, 1, 1 )
163 +#define MPP3_SPI_MISO MPP( 3, 0x2, 0, 0, 1, 1, 1, 1, 1 )
164
165 #define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1, 1 )
166 -#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1, 1 )
167 -#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1, 1 )
168 -#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1, 1 )
169 +#define MPP4_NF_IO6 MPP( 4, 0x1, 0, 0, 1, 1, 1, 1, 1 )
170 +#define MPP4_UART0_RXD MPP( 4, 0x2, 0, 0, 1, 1, 1, 1, 1 )
171 +#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 0, 0, 0, 1, 1, 1 )
172 #define MPP4_LCD_VGA_HSYNC MPP( 4, 0xb, 0, 0, 0, 0, 0, 0, 1 )
173 -#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1, 0 )
174 +#define MPP4_PTP_CLK MPP( 4, 0xd, 0, 0, 1, 1, 1, 1, 0 )
175
176 #define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1, 1 )
177 -#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1, 1 )
178 -#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1, 1 )
179 -#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1, 0 )
180 -#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1, 1 )
181 +#define MPP5_NF_IO7 MPP( 5, 0x1, 0, 0, 1, 1, 1, 1, 1 )
182 +#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 0, 1, 1, 1, 1, 1 )
183 +#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 0, 1, 1, 1, 1, 0 )
184 +#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 0, 0, 1, 1, 1, 1 )
185 #define MPP5_LCD_VGA_VSYNC MPP( 5, 0xb, 0, 0, 0, 0, 0, 0, 1 )
186
187 -#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1, 1 )
188 -#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1, 1 )
189 -#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1, 0 )
190 +#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 0, 1, 1, 1, 1, 1 )
191 +#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 0, 1, 1, 1, 1, 1 )
192 +#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 0, 1, 1, 1, 1, 0 )
193
194 #define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1, 1 )
195 -#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1, 0 )
196 -#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1, 1 )
197 -#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1, 0 )
198 -#define MPP7_LCD_PWM MPP( 7, 0xb, 0, 1, 0, 0, 0, 0, 1 )
199 +#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 0, 1, 1, 1, 1, 0 )
200 +#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 0, 1, 1, 1, 1, 1 )
201 +#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 0, 1, 1, 1, 1, 0 )
202 +#define MPP7_LCD_PWM MPP( 7, 0xb, 0, 0, 0, 0, 0, 0, 1 )
203
204 #define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1, 1 )
205 -#define MPP8_TW0_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1, 1 )
206 -#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1, 1 )
207 -#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1, 1 )
208 -#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1, 1 )
209 -#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1, 1 )
210 -#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1, 0 )
211 -#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1, 1 )
212 +#define MPP8_TW0_SDA MPP( 8, 0x1, 0, 0, 1, 1, 1, 1, 1 )
213 +#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 0, 1, 1, 1, 1, 1 )
214 +#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 0, 1, 1, 1, 1, 1 )
215 +#define MPP8_MII0_RXERR MPP( 8, 0x4, 0, 0, 0, 1, 1, 1, 1 )
216 +#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 0, 0, 0, 1, 1, 1 )
217 +#define MPP8_PTP_CLK MPP( 8, 0xc, 0, 0, 1, 1, 1, 1, 0 )
218 +#define MPP8_MII0_COL MPP( 8, 0xd, 0, 0, 1, 1, 1, 1, 1 )
219
220 #define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1, 1 )
221 -#define MPP9_TW0_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1, 1 )
222 -#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1, 1 )
223 -#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1, 1 )
224 -#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1, 1 )
225 -#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1, 0 )
226 -#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1, 1 )
227 +#define MPP9_TW0_SCK MPP( 9, 0x1, 0, 0, 1, 1, 1, 1, 1 )
228 +#define MPP9_UART0_CTS MPP( 9, 0x2, 0, 0, 1, 1, 1, 1, 1 )
229 +#define MPP9_UART1_CTS MPP( 9, 0x3, 0, 0, 1, 1, 1, 1, 1 )
230 +#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 0, 0, 1, 1, 1, 1 )
231 +#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 0, 0, 1, 1, 1, 1, 0 )
232 +#define MPP9_MII0_CRS MPP( 9, 0xd, 0, 0, 1, 1, 1, 1, 1 )
233
234 #define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1, 1 )
235 -#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1, 1 )
236 -#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1, 1 )
237 -#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1, 1 )
238 -#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1, 0 )
239 +#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 0, 1, 1, 1, 1, 1 )
240 +#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 0, 1, 1, 1, 1, 1 )
241 +#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 0, 0, 0, 1, 1, 1 )
242 +#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 0, 1, 1, 1, 1, 0 )
243
244 #define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1, 1 )
245 -#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1, 1 )
246 -#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1, 1 )
247 -#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1, 0 )
248 -#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1, 0 )
249 -#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1, 0 )
250 -#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1, 1 )
251 +#define MPP11_SPI_MISO MPP( 11, 0x2, 0, 0, 1, 1, 1, 1, 1 )
252 +#define MPP11_UART0_RXD MPP( 11, 0x3, 0, 0, 1, 1, 1, 1, 1 )
253 +#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 0, 0, 1, 1, 1, 1, 0 )
254 +#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 0, 1, 1, 1, 1, 0 )
255 +#define MPP11_PTP_CLK MPP( 11, 0xd, 0, 0, 1, 1, 1, 1, 0 )
256 +#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 0, 0, 1, 1, 1, 1 )
257
258 #define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1, 1 )
259 -#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1, 1 )
260 -#define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 1, 0, 0, 0, 0, 1 )
261 -#define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 1, 0, 0, 0, 0, 1 )
262 -#define MPP12_TW1_SDA MPP( 12, 0xd, 1, 0, 0, 0, 0, 0, 1 )
263 +#define MPP12_SD_CLK MPP( 12, 0x1, 0, 0, 1, 1, 1, 1, 1 )
264 +#define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 0, 0, 0, 0, 0, 1 )
265 +#define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 0, 0, 0, 0, 0, 1 )
266 +#define MPP12_TW1_SDA MPP( 12, 0xd, 0, 0, 0, 0, 0, 0, 1 )
267
268 #define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1, 1 )
269 -#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1, 1 )
270 -#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1, 1 )
271 -#define MPP13_AU_SPDIFRMCLK MPP( 13, 0xa, 0, 1, 0, 0, 0, 0, 1 )
272 -#define MPP13_LCDPWM MPP( 13, 0xb, 0, 1, 0, 0, 0, 0, 1 )
273 +#define MPP13_SD_CMD MPP( 13, 0x1, 0, 0, 1, 1, 1, 1, 1 )
274 +#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 0, 1, 1, 1, 1, 1 )
275 +#define MPP13_AU_SPDIFRMCLK MPP( 13, 0xa, 0, 0, 0, 0, 0, 0, 1 )
276 +#define MPP13_LCDPWM MPP( 13, 0xb, 0, 0, 0, 0, 0, 0, 1 )
277
278 #define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1, 1 )
279 -#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1, 1 )
280 -#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1, 1 )
281 -#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1, 1 )
282 -#define MPP14_AU_SPDIFI MPP( 14, 0xa, 1, 0, 0, 0, 0, 0, 1 )
283 -#define MPP14_AU_I2SDI MPP( 14, 0xb, 1, 0, 0, 0, 0, 0, 1 )
284 -#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1, 1 )
285 +#define MPP14_SD_D0 MPP( 14, 0x1, 0, 0, 1, 1, 1, 1, 1 )
286 +#define MPP14_UART1_RXD MPP( 14, 0x3, 0, 0, 1, 1, 1, 1, 1 )
287 +#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 0, 0, 0, 1, 1, 1 )
288 +#define MPP14_AU_SPDIFI MPP( 14, 0xa, 0, 0, 0, 0, 0, 0, 1 )
289 +#define MPP14_AU_I2SDI MPP( 14, 0xb, 0, 0, 0, 0, 0, 0, 1 )
290 +#define MPP14_MII0_COL MPP( 14, 0xd, 0, 0, 1, 1, 1, 1, 1 )
291
292 #define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1, 1 )
293 -#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1, 1 )
294 -#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1, 1 )
295 -#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1, 1 )
296 -#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1, 1 )
297 -#define MPP15_SPI_CSn MPP( 15, 0xb, 0, 1, 0, 0, 0, 0, 1 )
298 +#define MPP15_SD_D1 MPP( 15, 0x1, 0, 0, 1, 1, 1, 1, 1 )
299 +#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 0, 1, 1, 1, 1, 1 )
300 +#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 0, 1, 1, 1, 1, 1 )
301 +#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 0, 0, 1, 1, 1, 1 )
302 +#define MPP15_SPI_CSn MPP( 15, 0xb, 0, 0, 0, 0, 0, 0, 1 )
303
304 #define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1, 1 )
305 -#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1, 1 )
306 -#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1, 1 )
307 -#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1, 1 )
308 -#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1, 1 )
309 -#define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 1, 0, 0, 0, 0, 0, 1 )
310 -#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1, 1 )
311 +#define MPP16_SD_D2 MPP( 16, 0x1, 0, 0, 1, 1, 1, 1, 1 )
312 +#define MPP16_UART0_CTS MPP( 16, 0x2, 0, 0, 1, 1, 1, 1, 1 )
313 +#define MPP16_UART1_RXD MPP( 16, 0x3, 0, 0, 1, 1, 1, 1, 1 )
314 +#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 0, 0, 0, 1, 1, 1 )
315 +#define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 0, 0, 0, 0, 0, 0, 1 )
316 +#define MPP16_MII0_CRS MPP( 16, 0xd, 0, 0, 1, 1, 1, 1, 1 )
317
318 #define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1, 1 )
319 -#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1, 1 )
320 -#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1, 1 )
321 -#define MPP17_SATA1_ACTn MPP( 17, 0xa, 0, 1, 0, 0, 0, 0, 1 )
322 -#define MPP17_TW1_SCK MPP( 17, 0xd, 1, 1, 0, 0, 0, 0, 1 )
323 +#define MPP17_SD_D3 MPP( 17, 0x1, 0, 0, 1, 1, 1, 1, 1 )
324 +#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 0, 0, 1, 1, 1, 1 )
325 +#define MPP17_SATA1_ACTn MPP( 17, 0xa, 0, 0, 0, 0, 0, 0, 1 )
326 +#define MPP17_TW1_SCK MPP( 17, 0xd, 0, 0, 0, 0, 0, 0, 1 )
327
328 #define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1, 1 )
329 -#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1, 1 )
330 -#define MPP18_PEX0_CLKREQ MPP( 18, 0x2, 0, 1, 0, 0, 0, 0, 1 )
331 +#define MPP18_NF_IO0 MPP( 18, 0x1, 0, 0, 1, 1, 1, 1, 1 )
332 +#define MPP18_PEX0_CLKREQ MPP( 18, 0x2, 0, 0, 0, 0, 0, 0, 1 )
333
334 #define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1, 1 )
335 -#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1, 1 )
336 +#define MPP19_NF_IO1 MPP( 19, 0x1, 0, 0, 1, 1, 1, 1, 1 )
337
338 #define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1, 1 )
339 -#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1, 1 )
340 -#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1, 1 )
341 +#define MPP20_TSMP0 MPP( 20, 0x1, 0, 0, 0, 0, 1, 1, 1 )
342 +#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 0, 0, 0, 1, 1, 1 )
343 #define MPP20_GE1_TXD0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1, 1 )
344 -#define MPP20_AU_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1, 1 )
345 -#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1, 1 )
346 +#define MPP20_AU_SPDIFI MPP( 20, 0x4, 0, 0, 0, 0, 1, 1, 1 )
347 +#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 0, 0, 0, 1, 1, 1 )
348 #define MPP20_LCD_D0 MPP( 20, 0xb, 0, 0, 0, 0, 0, 0, 1 )
349
350 #define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1, 1 )
351 -#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1, 1 )
352 -#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1, 1 )
353 +#define MPP21_TSMP1 MPP( 21, 0x1, 0, 0, 0, 0, 1, 1, 1 )
354 +#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 0, 0, 0, 1, 1, 1 )
355 #define MPP21_GE1_TXD1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1, 1 )
356 -#define MPP21_AU_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1, 1 )
357 -#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1, 1 )
358 +#define MPP21_AU_SPDIFO MPP( 21, 0x4, 0, 0, 0, 0, 1, 1, 1 )
359 +#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 0, 0, 1, 1, 1, 1 )
360 #define MPP21_LCD_D1 MPP( 21, 0xb, 0, 0, 0, 0, 0, 0, 1 )
361
362 #define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1, 1 )
363 -#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1, 1 )
364 -#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1, 1 )
365 +#define MPP22_TSMP2 MPP( 22, 0x1, 0, 0, 0, 0, 1, 1, 1 )
366 +#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 0, 0, 0, 1, 1, 1 )
367 #define MPP22_GE1_TXD2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1, 1 )
368 -#define MPP22_AU_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1, 1 )
369 -#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1, 1 )
370 +#define MPP22_AU_SPDIFRMKCLK MPP( 22, 0x4, 0, 0, 0, 0, 1, 1, 1 )
371 +#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 0, 0, 0, 1, 1, 1 )
372 #define MPP22_LCD_D2 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
373
374 #define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1, 1 )
375 -#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1, 1 )
376 -#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1, 1 )
377 +#define MPP23_TSMP3 MPP( 23, 0x1, 0, 0, 0, 0, 1, 1, 1 )
378 +#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 0, 0, 0, 0, 1, 1, 1 )
379 #define MPP23_GE1_TXD3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1, 1 )
380 -#define MPP23_AU_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1, 1 )
381 -#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1, 1 )
382 +#define MPP23_AU_I2SBCLK MPP( 23, 0x4, 0, 0, 0, 0, 1, 1, 1 )
383 +#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 0, 0, 1, 1, 1, 1 )
384 #define MPP23_LCD_D3 MPP( 23, 0xb, 0, 0, 0, 0, 0, 0, 1 )
385
386 #define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1, 1 )
387 -#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1, 1 )
388 -#define MPP24_TDM_SPI_CS0 MPP( 24, 0x2, 0, 1, 0, 0, 1, 1, 1 )
389 +#define MPP24_TSMP4 MPP( 24, 0x1, 0, 0, 0, 0, 1, 1, 1 )
390 +#define MPP24_TDM_SPI_CS0 MPP( 24, 0x2, 0, 0, 0, 0, 1, 1, 1 )
391 #define MPP24_GE1_RXD0 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1, 1 )
392 -#define MPP24_AU_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1, 1 )
393 +#define MPP24_AU_I2SDO MPP( 24, 0x4, 0, 0, 0, 0, 1, 1, 1 )
394 #define MPP24_LCD_D4 MPP( 24, 0xb, 0, 0, 0, 0, 0, 0, 1 )
395
396 #define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1, 1 )
397 -#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1, 1 )
398 -#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1, 1 )
399 +#define MPP25_TSMP5 MPP( 25, 0x1, 0, 0, 0, 0, 1, 1, 1 )
400 +#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 0, 0, 0, 1, 1, 1 )
401 #define MPP25_GE1_RXD1 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1, 1 )
402 -#define MPP25_AU_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1, 1 )
403 +#define MPP25_AU_I2SLRCLK MPP( 25, 0x4, 0, 0, 0, 0, 1, 1, 1 )
404 #define MPP25_LCD_D5 MPP( 25, 0xb, 0, 0, 0, 0, 0, 0, 1 )
405
406 #define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1, 1 )
407 -#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1, 1 )
408 -#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1, 1 )
409 +#define MPP26_TSMP6 MPP( 26, 0x1, 0, 0, 0, 0, 1, 1, 1 )
410 +#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 0, 0, 0, 0, 1, 1, 1 )
411 #define MPP26_GE1_RXD2 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1, 1 )
412 -#define MPP26_AU_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1, 1 )
413 +#define MPP26_AU_I2SMCLK MPP( 26, 0x4, 0, 0, 0, 0, 1, 1, 1 )
414 #define MPP26_LCD_D6 MPP( 26, 0xb, 0, 0, 0, 0, 0, 0, 1 )
415
416 #define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1, 1 )
417 -#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1, 1 )
418 -#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1, 1 )
419 +#define MPP27_TSMP7 MPP( 27, 0x1, 0, 0, 0, 0, 1, 1, 1 )
420 +#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 0, 0, 0, 1, 1, 1 )
421 #define MPP27_GE1_RXD3 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1, 1 )
422 -#define MPP27_AU_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1, 1 )
423 +#define MPP27_AU_I2SDI MPP( 27, 0x4, 0, 0, 0, 0, 1, 1, 1 )
424 #define MPP27_LCD_D7 MPP( 27, 0xb, 0, 0, 0, 0, 0, 0, 1 )
425
426 #define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1, 1 )
427 -#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1, 1 )
428 +#define MPP28_TSMP8 MPP( 28, 0x1, 0, 0, 0, 0, 1, 1, 1 )
429 #define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1, 1 )
430 #define MPP28_GE1_COL MPP( 28, 0x3, 0, 0, 0, 1, 1, 1, 1 )
431 -#define MPP28_AU_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1, 1 )
432 +#define MPP28_AU_EXTCLK MPP( 28, 0x4, 0, 0, 0, 0, 1, 1, 1 )
433 #define MPP28_LCD_D8 MPP( 28, 0xb, 0, 0, 0, 0, 0, 0, 1 )
434
435 #define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1, 1 )
436 -#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1, 1 )
437 +#define MPP29_TSMP9 MPP( 29, 0x1, 0, 0, 0, 0, 1, 1, 1 )
438 #define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1, 1 )
439 #define MPP29_GE1_TCLK MPP( 29, 0x3, 0, 0, 0, 1, 1, 1, 1 )
440 #define MPP29_LCD_D9 MPP( 29, 0xb, 0, 0, 0, 0, 0, 0, 1 )
441
442 #define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1, 1 )
443 -#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1, 1 )
444 -#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1, 1 )
445 +#define MPP30_TSMP10 MPP( 30, 0x1, 0, 0, 0, 0, 1, 1, 1 )
446 +#define MPP30_TDM_PCLK MPP( 30, 0x2, 0, 0, 0, 0, 1, 1, 1 )
447 #define MPP30_GE1_RXCTL MPP( 30, 0x3, 0, 0, 0, 1, 1, 1, 1 )
448 #define MPP30_LCD_D10 MPP( 30, 0xb, 0, 0, 0, 0, 0, 0, 1 )
449
450 #define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1, 1 )
451 -#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1, 1 )
452 -#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1, 1 )
453 +#define MPP31_TSMP11 MPP( 31, 0x1, 0, 0, 0, 0, 1, 1, 1 )
454 +#define MPP31_TDM_FS MPP( 31, 0x2, 0, 0, 0, 0, 1, 1, 1 )
455 #define MPP31_GE1_RXCLK MPP( 31, 0x3, 0, 0, 0, 1, 1, 1, 1 )
456 #define MPP31_LCD_D11 MPP( 31, 0xb, 0, 0, 0, 0, 0, 0, 1 )
457
458 #define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1, 1 )
459 -#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1, 1 )
460 -#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1, 1 )
461 +#define MPP32_TSMP12 MPP( 32, 0x1, 0, 0, 0, 0, 1, 1, 1 )
462 +#define MPP32_TDM_DRX MPP( 32, 0x2, 0, 0, 0, 0, 1, 1, 1 )
463 #define MPP32_GE1_TCLKOUT MPP( 32, 0x3, 0, 0, 0, 1, 1, 1, 1 )
464 #define MPP32_LCD_D12 MPP( 32, 0xb, 0, 0, 0, 0, 0, 0, 1 )
465
466 #define MPP33_GPO MPP( 33, 0x0, 0, 1, 0, 1, 1, 1, 1 )
467 -#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1, 1 )
468 +#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 0, 0, 0, 1, 1, 1 )
469 #define MPP33_GE1_TXCTL MPP( 33, 0x3, 0, 0, 0, 1, 1, 1, 1 )
470 #define MPP33_LCD_D13 MPP( 33, 0xb, 0, 0, 0, 0, 0, 0, 1 )
471
472 #define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1, 1 )
473 -#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1, 1 )
474 +#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 0, 0, 0, 1, 1, 1 )
475 #define MPP34_GE1_TXEN MPP( 34, 0x3, 0, 0, 0, 1, 1, 1, 1 )
476 -#define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 1, 0, 0, 0, 1, 1 )
477 +#define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 0, 0, 0, 0, 1, 1 )
478 #define MPP34_LCD_D14 MPP( 34, 0xb, 0, 0, 0, 0, 0, 0, 1 )
479
480 #define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1, 1 )
481 -#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1, 1 )
482 +#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 0, 0, 0, 1, 1, 1 )
483 #define MPP35_GE1_RXERR MPP( 35, 0x3, 0, 0, 0, 1, 1, 1, 1 )
484 -#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1, 1 )
485 +#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 0, 0, 1, 1, 1, 1 )
486 #define MPP35_LCD_D15 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
487 -#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1, 1 )
488 +#define MPP35_MII0_RXERR MPP( 35, 0xc, 0, 0, 1, 1, 1, 1, 1 )
489
490 #define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1, 1 )
491 -#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1, 1 )
492 -#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1, 1 )
493 -#define MPP36_AU_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1, 1 )
494 -#define MPP36_TW1_SDA MPP( 36, 0xb, 1, 1, 0, 0, 0, 0, 1 )
495 +#define MPP36_TSMP0 MPP( 36, 0x1, 0, 0, 0, 0, 0, 1, 1 )
496 +#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 0, 0, 0, 0, 1, 1 )
497 +#define MPP36_AU_SPDIFI MPP( 36, 0x4, 0, 0, 1, 0, 0, 1, 1 )
498 +#define MPP36_TW1_SDA MPP( 36, 0xb, 0, 0, 0, 0, 0, 0, 1 )
499
500 #define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1, 1 )
501 -#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1, 1 )
502 -#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1, 1 )
503 -#define MPP37_AU_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1, 1 )
504 -#define MPP37_TW1_SCK MPP( 37, 0xb, 1, 1, 0, 0, 0, 0, 1 )
505 +#define MPP37_TSMP1 MPP( 37, 0x1, 0, 0, 0, 0, 0, 1, 1 )
506 +#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 0, 0, 0, 0, 1, 1 )
507 +#define MPP37_AU_SPDIFO MPP( 37, 0x4, 0, 0, 1, 0, 0, 1, 1 )
508 +#define MPP37_TW1_SCK MPP( 37, 0xb, 0, 0, 0, 0, 0, 0, 1 )
509
510 #define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1, 1 )
511 -#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1, 1 )
512 -#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1, 1 )
513 -#define MPP38_AU_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1, 1 )
514 +#define MPP38_TSMP2 MPP( 38, 0x1, 0, 0, 0, 0, 0, 1, 1 )
515 +#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 0, 0, 0, 0, 1, 1 )
516 +#define MPP38_AU_SPDIFRMLCLK MPP( 38, 0x4, 0, 0, 1, 0, 0, 1, 1 )
517 #define MPP38_LCD_D18 MPP( 38, 0xb, 0, 0, 0, 0, 0, 0, 1 )
518
519 #define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1, 1 )
520 -#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1, 1 )
521 -#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1, 1 )
522 -#define MPP39_AU_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1, 1 )
523 +#define MPP39_TSMP3 MPP( 39, 0x1, 0, 0, 0, 0, 0, 1, 1 )
524 +#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 0, 0, 0, 0, 1, 1 )
525 +#define MPP39_AU_I2SBCLK MPP( 39, 0x4, 0, 0, 1, 0, 0, 1, 1 )
526 #define MPP39_LCD_D19 MPP( 39, 0xb, 0, 0, 0, 0, 0, 0, 1 )
527
528 #define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1, 1 )
529 -#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1, 1 )
530 -#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1, 1 )
531 -#define MPP40_AU_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1, 1 )
532 +#define MPP40_TSMP4 MPP( 40, 0x1, 0, 0, 0, 0, 0, 1, 1 )
533 +#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 0, 0, 0, 0, 1, 1 )
534 +#define MPP40_AU_I2SDO MPP( 40, 0x4, 0, 0, 1, 0, 0, 1, 1 )
535 #define MPP40_LCD_D20 MPP( 40, 0xb, 0, 0, 0, 0, 0, 0, 1 )
536
537 #define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1, 1 )
538 -#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1, 1 )
539 -#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1, 1 )
540 -#define MPP41_AU_I2SLRCLK MPP( 41, 0x4, 0, 1, 1, 0, 0, 1, 1 )
541 +#define MPP41_TSMP5 MPP( 41, 0x1, 0, 0, 0, 0, 0, 1, 1 )
542 +#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 0, 0, 0, 0, 0, 1, 1 )
543 +#define MPP41_AU_I2SLRCLK MPP( 41, 0x4, 0, 0, 1, 0, 0, 1, 1 )
544 #define MPP41_LCD_D21 MPP( 41, 0xb, 0, 0, 0, 0, 0, 0, 1 )
545
546 #define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1, 1 )
547 -#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1, 1 )
548 -#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1, 1 )
549 -#define MPP42_AU_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1, 1 )
550 +#define MPP42_TSMP6 MPP( 42, 0x1, 0, 0, 0, 0, 0, 1, 1 )
551 +#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 0, 0, 0, 0, 1, 1 )
552 +#define MPP42_AU_I2SMCLK MPP( 42, 0x4, 0, 0, 1, 0, 0, 1, 1 )
553 #define MPP42_LCD_D22 MPP( 42, 0xb, 0, 0, 0, 0, 0, 0, 1 )
554
555 #define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1, 1 )
556 -#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1, 1 )
557 +#define MPP43_TSMP7 MPP( 43, 0x1, 0, 0, 0, 0, 0, 1, 1 )
558 #define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1, 1 )
559 -#define MPP43_AU_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1, 1 )
560 +#define MPP43_AU_I2SDI MPP( 43, 0x4, 0, 0, 1, 0, 0, 1, 1 )
561 #define MPP43_LCD_D23 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
562
563 #define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1, 1 )
564 -#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1, 1 )
565 +#define MPP44_TSMP8 MPP( 44, 0x1, 0, 0, 0, 0, 0, 1, 1 )
566 #define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1, 1 )
567 -#define MPP44_AU_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1, 1 )
568 +#define MPP44_AU_EXTCLK MPP( 44, 0x4, 0, 0, 1, 0, 0, 1, 1 )
569 #define MPP44_LCD_CLK MPP( 44, 0xb, 0, 0, 0, 0, 0, 0, 1 )
570
571 #define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1, 1 )
572 -#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1, 1 )
573 -#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1, 1 )
574 +#define MPP45_TSMP9 MPP( 45, 0x1, 0, 0, 0, 0, 0, 1, 1 )
575 +#define MPP45_TDM_PCLK MPP( 45, 0x2, 0, 0, 0, 0, 0, 1, 1 )
576 #define MPP245_LCD_E MPP( 45, 0xb, 0, 0, 0, 0, 0, 0, 1 )
577
578 #define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1, 1 )
579 -#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1, 1 )
580 -#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1, 1 )
581 +#define MPP46_TSMP10 MPP( 46, 0x1, 0, 0, 0, 0, 0, 1, 1 )
582 +#define MPP46_TDM_FS MPP( 46, 0x2, 0, 0, 0, 0, 0, 1, 1 )
583 #define MPP46_LCD_HSYNC MPP( 46, 0xb, 0, 0, 0, 0, 0, 0, 1 )
584
585 #define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1, 1 )
586 -#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1, 1 )
587 -#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1, 1 )
588 +#define MPP47_TSMP11 MPP( 47, 0x1, 0, 0, 0, 0, 0, 1, 1 )
589 +#define MPP47_TDM_DRX MPP( 47, 0x2, 0, 0, 0, 0, 0, 1, 1 )
590 #define MPP47_LCD_VSYNC MPP( 47, 0xb, 0, 0, 0, 0, 0, 0, 1 )
591
592 #define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1, 1 )
593 -#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1, 1 )
594 -#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1, 1 )
595 +#define MPP48_TSMP12 MPP( 48, 0x1, 0, 0, 0, 0, 0, 1, 1 )
596 +#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 0, 0, 0, 0, 1, 1 )
597 #define MPP48_LCD_D16 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 )
598
599 #define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1, 0 )
600 #define MPP49_GPO MPP( 49, 0x0, 0, 1, 0, 0, 0, 0, 1 )
601 -#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1, 0 )
602 -#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1, 1 )
603 -#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1, 0 )
604 -#define MPP49_PEX0_CLKREQ MPP( 49, 0xa, 0, 1, 0, 0, 0, 0, 1 )
605 +#define MPP49_TSMP9 MPP( 49, 0x1, 0, 0, 0, 0, 0, 1, 0 )
606 +#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 0, 0, 0, 0, 1, 1 )
607 +#define MPP49_PTP_CLK MPP( 49, 0x5, 0, 0, 0, 0, 0, 1, 0 )
608 +#define MPP49_PEX0_CLKREQ MPP( 49, 0xa, 0, 0, 0, 0, 0, 0, 1 )
609 #define MPP49_LCD_D17 MPP( 49, 0xb, 0, 0, 0, 0, 0, 0, 1 )
610
611 #define MPP_MAX 49
612 diff --git a/arch/arm/mach-lpc32xx/include/mach/irqs.h b/arch/arm/mach-lpc32xx/include/mach/irqs.h
613 index 2667f52..9e3b90d 100644
614 --- a/arch/arm/mach-lpc32xx/include/mach/irqs.h
615 +++ b/arch/arm/mach-lpc32xx/include/mach/irqs.h
616 @@ -61,7 +61,7 @@
617 */
618 #define IRQ_LPC32XX_JTAG_COMM_TX LPC32XX_SIC1_IRQ(1)
619 #define IRQ_LPC32XX_JTAG_COMM_RX LPC32XX_SIC1_IRQ(2)
620 -#define IRQ_LPC32XX_GPI_11 LPC32XX_SIC1_IRQ(4)
621 +#define IRQ_LPC32XX_GPI_28 LPC32XX_SIC1_IRQ(4)
622 #define IRQ_LPC32XX_TS_P LPC32XX_SIC1_IRQ(6)
623 #define IRQ_LPC32XX_TS_IRQ LPC32XX_SIC1_IRQ(7)
624 #define IRQ_LPC32XX_TS_AUX LPC32XX_SIC1_IRQ(8)
625 diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
626 index 4eae566..c74de01 100644
627 --- a/arch/arm/mach-lpc32xx/irq.c
628 +++ b/arch/arm/mach-lpc32xx/irq.c
629 @@ -118,6 +118,10 @@ static const struct lpc32xx_event_info lpc32xx_events[NR_IRQS] = {
630 .event_group = &lpc32xx_event_pin_regs,
631 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT,
632 },
633 + [IRQ_LPC32XX_GPI_28] = {
634 + .event_group = &lpc32xx_event_pin_regs,
635 + .mask = LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT,
636 + },
637 [IRQ_LPC32XX_GPIO_00] = {
638 .event_group = &lpc32xx_event_int_regs,
639 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT,
640 @@ -305,9 +309,18 @@ static int lpc32xx_irq_wake(struct irq_data *d, unsigned int state)
641
642 if (state)
643 eventreg |= lpc32xx_events[d->irq].mask;
644 - else
645 + else {
646 eventreg &= ~lpc32xx_events[d->irq].mask;
647
648 + /*
649 + * When disabling the wakeup, clear the latched
650 + * event
651 + */
652 + __raw_writel(lpc32xx_events[d->irq].mask,
653 + lpc32xx_events[d->irq].
654 + event_group->rawstat_reg);
655 + }
656 +
657 __raw_writel(eventreg,
658 lpc32xx_events[d->irq].event_group->enab_reg);
659
660 @@ -380,13 +393,15 @@ void __init lpc32xx_init_irq(void)
661
662 /* Setup SIC1 */
663 __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE));
664 - __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE));
665 - __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE));
666 + __raw_writel(SIC1_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE));
667 + __raw_writel(SIC1_ATR_DEFAULT,
668 + LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE));
669
670 /* Setup SIC2 */
671 __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
672 - __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE));
673 - __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE));
674 + __raw_writel(SIC2_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE));
675 + __raw_writel(SIC2_ATR_DEFAULT,
676 + LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE));
677
678 /* Configure supported IRQ's */
679 for (i = 0; i < NR_IRQS; i++) {
680 diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c
681 index 429cfdb..f273528 100644
682 --- a/arch/arm/mach-lpc32xx/serial.c
683 +++ b/arch/arm/mach-lpc32xx/serial.c
684 @@ -88,6 +88,7 @@ struct uartinit {
685 char *uart_ck_name;
686 u32 ck_mode_mask;
687 void __iomem *pdiv_clk_reg;
688 + resource_size_t mapbase;
689 };
690
691 static struct uartinit uartinit_data[] __initdata = {
692 @@ -97,6 +98,7 @@ static struct uartinit uartinit_data[] __initdata = {
693 .ck_mode_mask =
694 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 5),
695 .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL,
696 + .mapbase = LPC32XX_UART5_BASE,
697 },
698 #endif
699 #ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
700 @@ -105,6 +107,7 @@ static struct uartinit uartinit_data[] __initdata = {
701 .ck_mode_mask =
702 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 3),
703 .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL,
704 + .mapbase = LPC32XX_UART3_BASE,
705 },
706 #endif
707 #ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
708 @@ -113,6 +116,7 @@ static struct uartinit uartinit_data[] __initdata = {
709 .ck_mode_mask =
710 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 4),
711 .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL,
712 + .mapbase = LPC32XX_UART4_BASE,
713 },
714 #endif
715 #ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
716 @@ -121,6 +125,7 @@ static struct uartinit uartinit_data[] __initdata = {
717 .ck_mode_mask =
718 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 6),
719 .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL,
720 + .mapbase = LPC32XX_UART6_BASE,
721 },
722 #endif
723 };
724 @@ -165,11 +170,24 @@ void __init lpc32xx_serial_init(void)
725
726 /* pre-UART clock divider set to 1 */
727 __raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg);
728 +
729 + /*
730 + * Force a flush of the RX FIFOs to work around a
731 + * HW bug
732 + */
733 + puart = uartinit_data[i].mapbase;
734 + __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
735 + __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
736 + j = LPC32XX_SUART_FIFO_SIZE;
737 + while (j--)
738 + tmp = __raw_readl(
739 + LPC32XX_UART_DLL_FIFO(puart));
740 + __raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
741 }
742
743 /* This needs to be done after all UART clocks are setup */
744 __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE);
745 - for (i = 0; i < ARRAY_SIZE(uartinit_data) - 1; i++) {
746 + for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
747 /* Force a flush of the RX FIFOs to work around a HW bug */
748 puart = serial_std_platform_data[i].mapbase;
749 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
750 diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
751 index 23d3980..d90e244 100644
752 --- a/arch/arm/mach-mv78xx0/common.c
753 +++ b/arch/arm/mach-mv78xx0/common.c
754 @@ -20,6 +20,7 @@
755 #include <mach/mv78xx0.h>
756 #include <mach/bridge-regs.h>
757 #include <plat/cache-feroceon-l2.h>
758 +#include <plat/ehci-orion.h>
759 #include <plat/orion_nand.h>
760 #include <plat/time.h>
761 #include <plat/common.h>
762 @@ -170,7 +171,7 @@ void __init mv78xx0_map_io(void)
763 void __init mv78xx0_ehci0_init(void)
764 {
765 orion_ehci_init(&mv78xx0_mbus_dram_info,
766 - USB0_PHYS_BASE, IRQ_MV78XX0_USB_0);
767 + USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA);
768 }
769
770
771 diff --git a/arch/arm/mach-mv78xx0/mpp.h b/arch/arm/mach-mv78xx0/mpp.h
772 index b61b509..3752302 100644
773 --- a/arch/arm/mach-mv78xx0/mpp.h
774 +++ b/arch/arm/mach-mv78xx0/mpp.h
775 @@ -24,296 +24,296 @@
776 #define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1)
777
778 #define MPP0_GPIO MPP(0, 0x0, 1, 1, 1)
779 -#define MPP0_GE0_COL MPP(0, 0x1, 1, 0, 1)
780 -#define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 1, 1)
781 +#define MPP0_GE0_COL MPP(0, 0x1, 0, 0, 1)
782 +#define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 0, 1)
783 #define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1)
784
785 #define MPP1_GPIO MPP(1, 0x0, 1, 1, 1)
786 -#define MPP1_GE0_RXERR MPP(1, 0x1, 1, 0, 1)
787 -#define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 1, 1)
788 +#define MPP1_GE0_RXERR MPP(1, 0x1, 0, 0, 1)
789 +#define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 0, 1)
790 #define MPP1_UNUSED MPP(1, 0x3, 0, 0, 1)
791
792 #define MPP2_GPIO MPP(2, 0x0, 1, 1, 1)
793 -#define MPP2_GE0_CRS MPP(2, 0x1, 1, 0, 1)
794 -#define MPP2_GE1_RXCTL MPP(2, 0x2, 1, 0, 1)
795 +#define MPP2_GE0_CRS MPP(2, 0x1, 0, 0, 1)
796 +#define MPP2_GE1_RXCTL MPP(2, 0x2, 0, 0, 1)
797 #define MPP2_UNUSED MPP(2, 0x3, 0, 0, 1)
798
799 #define MPP3_GPIO MPP(3, 0x0, 1, 1, 1)
800 -#define MPP3_GE0_TXERR MPP(3, 0x1, 0, 1, 1)
801 -#define MPP3_GE1_RXCLK MPP(3, 0x2, 1, 0, 1)
802 +#define MPP3_GE0_TXERR MPP(3, 0x1, 0, 0, 1)
803 +#define MPP3_GE1_RXCLK MPP(3, 0x2, 0, 0, 1)
804 #define MPP3_UNUSED MPP(3, 0x3, 0, 0, 1)
805
806 #define MPP4_GPIO MPP(4, 0x0, 1, 1, 1)
807 -#define MPP4_GE0_TXD4 MPP(4, 0x1, 0, 1, 1)
808 -#define MPP4_GE1_TXD0 MPP(4, 0x2, 0, 1, 1)
809 +#define MPP4_GE0_TXD4 MPP(4, 0x1, 0, 0, 1)
810 +#define MPP4_GE1_TXD0 MPP(4, 0x2, 0, 0, 1)
811 #define MPP4_UNUSED MPP(4, 0x3, 0, 0, 1)
812
813 #define MPP5_GPIO MPP(5, 0x0, 1, 1, 1)
814 -#define MPP5_GE0_TXD5 MPP(5, 0x1, 0, 1, 1)
815 -#define MPP5_GE1_TXD1 MPP(5, 0x2, 0, 1, 1)
816 +#define MPP5_GE0_TXD5 MPP(5, 0x1, 0, 0, 1)
817 +#define MPP5_GE1_TXD1 MPP(5, 0x2, 0, 0, 1)
818 #define MPP5_UNUSED MPP(5, 0x3, 0, 0, 1)
819
820 #define MPP6_GPIO MPP(6, 0x0, 1, 1, 1)
821 -#define MPP6_GE0_TXD6 MPP(6, 0x1, 0, 1, 1)
822 -#define MPP6_GE1_TXD2 MPP(6, 0x2, 0, 1, 1)
823 +#define MPP6_GE0_TXD6 MPP(6, 0x1, 0, 0, 1)
824 +#define MPP6_GE1_TXD2 MPP(6, 0x2, 0, 0, 1)
825 #define MPP6_UNUSED MPP(6, 0x3, 0, 0, 1)
826
827 #define MPP7_GPIO MPP(7, 0x0, 1, 1, 1)
828 -#define MPP7_GE0_TXD7 MPP(7, 0x1, 0, 1, 1)
829 -#define MPP7_GE1_TXD3 MPP(7, 0x2, 0, 1, 1)
830 +#define MPP7_GE0_TXD7 MPP(7, 0x1, 0, 0, 1)
831 +#define MPP7_GE1_TXD3 MPP(7, 0x2, 0, 0, 1)
832 #define MPP7_UNUSED MPP(7, 0x3, 0, 0, 1)
833
834 #define MPP8_GPIO MPP(8, 0x0, 1, 1, 1)
835 -#define MPP8_GE0_RXD4 MPP(8, 0x1, 1, 0, 1)
836 -#define MPP8_GE1_RXD0 MPP(8, 0x2, 1, 0, 1)
837 +#define MPP8_GE0_RXD4 MPP(8, 0x1, 0, 0, 1)
838 +#define MPP8_GE1_RXD0 MPP(8, 0x2, 0, 0, 1)
839 #define MPP8_UNUSED MPP(8, 0x3, 0, 0, 1)
840
841 #define MPP9_GPIO MPP(9, 0x0, 1, 1, 1)
842 -#define MPP9_GE0_RXD5 MPP(9, 0x1, 1, 0, 1)
843 -#define MPP9_GE1_RXD1 MPP(9, 0x2, 1, 0, 1)
844 +#define MPP9_GE0_RXD5 MPP(9, 0x1, 0, 0, 1)
845 +#define MPP9_GE1_RXD1 MPP(9, 0x2, 0, 0, 1)
846 #define MPP9_UNUSED MPP(9, 0x3, 0, 0, 1)
847
848 #define MPP10_GPIO MPP(10, 0x0, 1, 1, 1)
849 -#define MPP10_GE0_RXD6 MPP(10, 0x1, 1, 0, 1)
850 -#define MPP10_GE1_RXD2 MPP(10, 0x2, 1, 0, 1)
851 +#define MPP10_GE0_RXD6 MPP(10, 0x1, 0, 0, 1)
852 +#define MPP10_GE1_RXD2 MPP(10, 0x2, 0, 0, 1)
853 #define MPP10_UNUSED MPP(10, 0x3, 0, 0, 1)
854
855 #define MPP11_GPIO MPP(11, 0x0, 1, 1, 1)
856 -#define MPP11_GE0_RXD7 MPP(11, 0x1, 1, 0, 1)
857 -#define MPP11_GE1_RXD3 MPP(11, 0x2, 1, 0, 1)
858 +#define MPP11_GE0_RXD7 MPP(11, 0x1, 0, 0, 1)
859 +#define MPP11_GE1_RXD3 MPP(11, 0x2, 0, 0, 1)
860 #define MPP11_UNUSED MPP(11, 0x3, 0, 0, 1)
861
862 #define MPP12_GPIO MPP(12, 0x0, 1, 1, 1)
863 -#define MPP12_M_BB MPP(12, 0x3, 1, 0, 1)
864 -#define MPP12_UA0_CTSn MPP(12, 0x4, 1, 0, 1)
865 -#define MPP12_NAND_FLASH_REn0 MPP(12, 0x5, 0, 1, 1)
866 -#define MPP12_TDM0_SCSn MPP(12, 0X6, 0, 1, 1)
867 +#define MPP12_M_BB MPP(12, 0x3, 0, 0, 1)
868 +#define MPP12_UA0_CTSn MPP(12, 0x4, 0, 0, 1)
869 +#define MPP12_NAND_FLASH_REn0 MPP(12, 0x5, 0, 0, 1)
870 +#define MPP12_TDM0_SCSn MPP(12, 0X6, 0, 0, 1)
871 #define MPP12_UNUSED MPP(12, 0x1, 0, 0, 1)
872
873 #define MPP13_GPIO MPP(13, 0x0, 1, 1, 1)
874 -#define MPP13_SYSRST_OUTn MPP(13, 0x3, 0, 1, 1)
875 -#define MPP13_UA0_RTSn MPP(13, 0x4, 0, 1, 1)
876 -#define MPP13_NAN_FLASH_WEn0 MPP(13, 0x5, 0, 1, 1)
877 -#define MPP13_TDM_SCLK MPP(13, 0x6, 0, 1, 1)
878 +#define MPP13_SYSRST_OUTn MPP(13, 0x3, 0, 0, 1)
879 +#define MPP13_UA0_RTSn MPP(13, 0x4, 0, 0, 1)
880 +#define MPP13_NAN_FLASH_WEn0 MPP(13, 0x5, 0, 0, 1)
881 +#define MPP13_TDM_SCLK MPP(13, 0x6, 0, 0, 1)
882 #define MPP13_UNUSED MPP(13, 0x1, 0, 0, 1)
883
884 #define MPP14_GPIO MPP(14, 0x0, 1, 1, 1)
885 -#define MPP14_SATA1_ACTn MPP(14, 0x3, 0, 1, 1)
886 -#define MPP14_UA1_CTSn MPP(14, 0x4, 1, 0, 1)
887 -#define MPP14_NAND_FLASH_REn1 MPP(14, 0x5, 0, 1, 1)
888 -#define MPP14_TDM_SMOSI MPP(14, 0x6, 0, 1, 1)
889 +#define MPP14_SATA1_ACTn MPP(14, 0x3, 0, 0, 1)
890 +#define MPP14_UA1_CTSn MPP(14, 0x4, 0, 0, 1)
891 +#define MPP14_NAND_FLASH_REn1 MPP(14, 0x5, 0, 0, 1)
892 +#define MPP14_TDM_SMOSI MPP(14, 0x6, 0, 0, 1)
893 #define MPP14_UNUSED MPP(14, 0x1, 0, 0, 1)
894
895 #define MPP15_GPIO MPP(15, 0x0, 1, 1, 1)
896 -#define MPP15_SATA0_ACTn MPP(15, 0x3, 0, 1, 1)
897 -#define MPP15_UA1_RTSn MPP(15, 0x4, 0, 1, 1)
898 -#define MPP15_NAND_FLASH_WEn1 MPP(15, 0x5, 0, 1, 1)
899 -#define MPP15_TDM_SMISO MPP(15, 0x6, 1, 0, 1)
900 +#define MPP15_SATA0_ACTn MPP(15, 0x3, 0, 0, 1)
901 +#define MPP15_UA1_RTSn MPP(15, 0x4, 0, 0, 1)
902 +#define MPP15_NAND_FLASH_WEn1 MPP(15, 0x5, 0, 0, 1)
903 +#define MPP15_TDM_SMISO MPP(15, 0x6, 0, 0, 1)
904 #define MPP15_UNUSED MPP(15, 0x1, 0, 0, 1)
905
906 #define MPP16_GPIO MPP(16, 0x0, 1, 1, 1)
907 -#define MPP16_SATA1_PRESENTn MPP(16, 0x3, 0, 1, 1)
908 -#define MPP16_UA2_TXD MPP(16, 0x4, 0, 1, 1)
909 -#define MPP16_NAND_FLASH_REn3 MPP(16, 0x5, 0, 1, 1)
910 -#define MPP16_TDM_INTn MPP(16, 0x6, 1, 0, 1)
911 +#define MPP16_SATA1_PRESENTn MPP(16, 0x3, 0, 0, 1)
912 +#define MPP16_UA2_TXD MPP(16, 0x4, 0, 0, 1)
913 +#define MPP16_NAND_FLASH_REn3 MPP(16, 0x5, 0, 0, 1)
914 +#define MPP16_TDM_INTn MPP(16, 0x6, 0, 0, 1)
915 #define MPP16_UNUSED MPP(16, 0x1, 0, 0, 1)
916
917
918 #define MPP17_GPIO MPP(17, 0x0, 1, 1, 1)
919 -#define MPP17_SATA0_PRESENTn MPP(17, 0x3, 0, 1, 1)
920 -#define MPP17_UA2_RXD MPP(17, 0x4, 1, 0, 1)
921 -#define MPP17_NAND_FLASH_WEn3 MPP(17, 0x5, 0, 1, 1)
922 -#define MPP17_TDM_RSTn MPP(17, 0x6, 0, 1, 1)
923 +#define MPP17_SATA0_PRESENTn MPP(17, 0x3, 0, 0, 1)
924 +#define MPP17_UA2_RXD MPP(17, 0x4, 0, 0, 1)
925 +#define MPP17_NAND_FLASH_WEn3 MPP(17, 0x5, 0, 0, 1)
926 +#define MPP17_TDM_RSTn MPP(17, 0x6, 0, 0, 1)
927 #define MPP17_UNUSED MPP(17, 0x1, 0, 0, 1)
928
929
930 #define MPP18_GPIO MPP(18, 0x0, 1, 1, 1)
931 -#define MPP18_UA0_CTSn MPP(18, 0x4, 1, 0, 1)
932 -#define MPP18_BOOT_FLASH_REn MPP(18, 0x5, 0, 1, 1)
933 +#define MPP18_UA0_CTSn MPP(18, 0x4, 0, 0, 1)
934 +#define MPP18_BOOT_FLASH_REn MPP(18, 0x5, 0, 0, 1)
935 #define MPP18_UNUSED MPP(18, 0x1, 0, 0, 1)
936
937
938
939 #define MPP19_GPIO MPP(19, 0x0, 1, 1, 1)
940 -#define MPP19_UA0_CTSn MPP(19, 0x4, 0, 1, 1)
941 -#define MPP19_BOOT_FLASH_WEn MPP(19, 0x5, 0, 1, 1)
942 +#define MPP19_UA0_CTSn MPP(19, 0x4, 0, 0, 1)
943 +#define MPP19_BOOT_FLASH_WEn MPP(19, 0x5, 0, 0, 1)
944 #define MPP19_UNUSED MPP(19, 0x1, 0, 0, 1)
945
946
947 #define MPP20_GPIO MPP(20, 0x0, 1, 1, 1)
948 -#define MPP20_UA1_CTSs MPP(20, 0x4, 1, 0, 1)
949 -#define MPP20_TDM_PCLK MPP(20, 0x6, 1, 1, 0)
950 +#define MPP20_UA1_CTSs MPP(20, 0x4, 0, 0, 1)
951 +#define MPP20_TDM_PCLK MPP(20, 0x6, 0, 0, 0)
952 #define MPP20_UNUSED MPP(20, 0x1, 0, 0, 1)
953
954
955
956 #define MPP21_GPIO MPP(21, 0x0, 1, 1, 1)
957 -#define MPP21_UA1_CTSs MPP(21, 0x4, 0, 1, 1)
958 -#define MPP21_TDM_FSYNC MPP(21, 0x6, 1, 1, 0)
959 +#define MPP21_UA1_CTSs MPP(21, 0x4, 0, 0, 1)
960 +#define MPP21_TDM_FSYNC MPP(21, 0x6, 0, 0, 0)
961 #define MPP21_UNUSED MPP(21, 0x1, 0, 0, 1)
962
963
964
965 #define MPP22_GPIO MPP(22, 0x0, 1, 1, 1)
966 -#define MPP22_UA3_TDX MPP(22, 0x4, 0, 1, 1)
967 -#define MPP22_NAND_FLASH_REn2 MPP(22, 0x5, 0, 1, 1)
968 -#define MPP22_TDM_DRX MPP(22, 0x6, 1, 0, 1)
969 +#define MPP22_UA3_TDX MPP(22, 0x4, 0, 0, 1)
970 +#define MPP22_NAND_FLASH_REn2 MPP(22, 0x5, 0, 0, 1)
971 +#define MPP22_TDM_DRX MPP(22, 0x6, 0, 0, 1)
972 #define MPP22_UNUSED MPP(22, 0x1, 0, 0, 1)
973
974
975
976 #define MPP23_GPIO MPP(23, 0x0, 1, 1, 1)
977 -#define MPP23_UA3_RDX MPP(23, 0x4, 1, 0, 1)
978 -#define MPP23_NAND_FLASH_WEn2 MPP(23, 0x5, 0, 1, 1)
979 -#define MPP23_TDM_DTX MPP(23, 0x6, 0, 1, 1)
980 +#define MPP23_UA3_RDX MPP(23, 0x4, 0, 0, 1)
981 +#define MPP23_NAND_FLASH_WEn2 MPP(23, 0x5, 0, 0, 1)
982 +#define MPP23_TDM_DTX MPP(23, 0x6, 0, 0, 1)
983 #define MPP23_UNUSED MPP(23, 0x1, 0, 0, 1)
984
985
986 #define MPP24_GPIO MPP(24, 0x0, 1, 1, 1)
987 -#define MPP24_UA2_TXD MPP(24, 0x4, 0, 1, 1)
988 -#define MPP24_TDM_INTn MPP(24, 0x6, 1, 0, 1)
989 +#define MPP24_UA2_TXD MPP(24, 0x4, 0, 0, 1)
990 +#define MPP24_TDM_INTn MPP(24, 0x6, 0, 0, 1)
991 #define MPP24_UNUSED MPP(24, 0x1, 0, 0, 1)
992
993
994 #define MPP25_GPIO MPP(25, 0x0, 1, 1, 1)
995 -#define MPP25_UA2_RXD MPP(25, 0x4, 1, 0, 1)
996 -#define MPP25_TDM_RSTn MPP(25, 0x6, 0, 1, 1)
997 +#define MPP25_UA2_RXD MPP(25, 0x4, 0, 0, 1)
998 +#define MPP25_TDM_RSTn MPP(25, 0x6, 0, 0, 1)
999 #define MPP25_UNUSED MPP(25, 0x1, 0, 0, 1)
1000
1001
1002 #define MPP26_GPIO MPP(26, 0x0, 1, 1, 1)
1003 -#define MPP26_UA2_CTSn MPP(26, 0x4, 1, 0, 1)
1004 -#define MPP26_TDM_PCLK MPP(26, 0x6, 1, 1, 1)
1005 +#define MPP26_UA2_CTSn MPP(26, 0x4, 0, 0, 1)
1006 +#define MPP26_TDM_PCLK MPP(26, 0x6, 0, 0, 1)
1007 #define MPP26_UNUSED MPP(26, 0x1, 0, 0, 1)
1008
1009
1010 #define MPP27_GPIO MPP(27, 0x0, 1, 1, 1)
1011 -#define MPP27_UA2_RTSn MPP(27, 0x4, 0, 1, 1)
1012 -#define MPP27_TDM_FSYNC MPP(27, 0x6, 1, 1, 1)
1013 +#define MPP27_UA2_RTSn MPP(27, 0x4, 0, 0, 1)
1014 +#define MPP27_TDM_FSYNC MPP(27, 0x6, 0, 0, 1)
1015 #define MPP27_UNUSED MPP(27, 0x1, 0, 0, 1)
1016
1017
1018 #define MPP28_GPIO MPP(28, 0x0, 1, 1, 1)
1019 -#define MPP28_UA3_TXD MPP(28, 0x4, 0, 1, 1)
1020 -#define MPP28_TDM_DRX MPP(28, 0x6, 1, 0, 1)
1021 +#define MPP28_UA3_TXD MPP(28, 0x4, 0, 0, 1)
1022 +#define MPP28_TDM_DRX MPP(28, 0x6, 0, 0, 1)
1023 #define MPP28_UNUSED MPP(28, 0x1, 0, 0, 1)
1024
1025 #define MPP29_GPIO MPP(29, 0x0, 1, 1, 1)
1026 -#define MPP29_UA3_RXD MPP(29, 0x4, 1, 0, 1)
1027 -#define MPP29_SYSRST_OUTn MPP(29, 0x5, 0, 1, 1)
1028 -#define MPP29_TDM_DTX MPP(29, 0x6, 0, 1, 1)
1029 +#define MPP29_UA3_RXD MPP(29, 0x4, 0, 0, 1)
1030 +#define MPP29_SYSRST_OUTn MPP(29, 0x5, 0, 0, 1)
1031 +#define MPP29_TDM_DTX MPP(29, 0x6, 0, 0, 1)
1032 #define MPP29_UNUSED MPP(29, 0x1, 0, 0, 1)
1033
1034 #define MPP30_GPIO MPP(30, 0x0, 1, 1, 1)
1035 -#define MPP30_UA3_CTSn MPP(30, 0x4, 1, 0, 1)
1036 +#define MPP30_UA3_CTSn MPP(30, 0x4, 0, 0, 1)
1037 #define MPP30_UNUSED MPP(30, 0x1, 0, 0, 1)
1038
1039 #define MPP31_GPIO MPP(31, 0x0, 1, 1, 1)
1040 -#define MPP31_UA3_RTSn MPP(31, 0x4, 0, 1, 1)
1041 -#define MPP31_TDM1_SCSn MPP(31, 0x6, 0, 1, 1)
1042 +#define MPP31_UA3_RTSn MPP(31, 0x4, 0, 0, 1)
1043 +#define MPP31_TDM1_SCSn MPP(31, 0x6, 0, 0, 1)
1044 #define MPP31_UNUSED MPP(31, 0x1, 0, 0, 1)
1045
1046
1047 #define MPP32_GPIO MPP(32, 0x1, 1, 1, 1)
1048 -#define MPP32_UA3_TDX MPP(32, 0x4, 0, 1, 1)
1049 -#define MPP32_SYSRST_OUTn MPP(32, 0x5, 0, 1, 1)
1050 -#define MPP32_TDM0_RXQ MPP(32, 0x6, 0, 1, 1)
1051 +#define MPP32_UA3_TDX MPP(32, 0x4, 0, 0, 1)
1052 +#define MPP32_SYSRST_OUTn MPP(32, 0x5, 0, 0, 1)
1053 +#define MPP32_TDM0_RXQ MPP(32, 0x6, 0, 0, 1)
1054 #define MPP32_UNUSED MPP(32, 0x3, 0, 0, 1)
1055
1056
1057 #define MPP33_GPIO MPP(33, 0x1, 1, 1, 1)
1058 -#define MPP33_UA3_RDX MPP(33, 0x4, 1, 0, 1)
1059 -#define MPP33_TDM0_TXQ MPP(33, 0x6, 0, 1, 1)
1060 +#define MPP33_UA3_RDX MPP(33, 0x4, 0, 0, 1)
1061 +#define MPP33_TDM0_TXQ MPP(33, 0x6, 0, 0, 1)
1062 #define MPP33_UNUSED MPP(33, 0x3, 0, 0, 1)
1063
1064
1065
1066 #define MPP34_GPIO MPP(34, 0x1, 1, 1, 1)
1067 -#define MPP34_UA2_TDX MPP(34, 0x4, 0, 1, 1)
1068 -#define MPP34_TDM1_RXQ MPP(34, 0x6, 0, 1, 1)
1069 +#define MPP34_UA2_TDX MPP(34, 0x4, 0, 0, 1)
1070 +#define MPP34_TDM1_RXQ MPP(34, 0x6, 0, 0, 1)
1071 #define MPP34_UNUSED MPP(34, 0x3, 0, 0, 1)
1072
1073
1074
1075 #define MPP35_GPIO MPP(35, 0x1, 1, 1, 1)
1076 -#define MPP35_UA2_RDX MPP(35, 0x4, 1, 0, 1)
1077 -#define MPP35_TDM1_TXQ MPP(35, 0x6, 0, 1, 1)
1078 +#define MPP35_UA2_RDX MPP(35, 0x4, 0, 0, 1)
1079 +#define MPP35_TDM1_TXQ MPP(35, 0x6, 0, 0, 1)
1080 #define MPP35_UNUSED MPP(35, 0x3, 0, 0, 1)
1081
1082 #define MPP36_GPIO MPP(36, 0x1, 1, 1, 1)
1083 -#define MPP36_UA0_CTSn MPP(36, 0x2, 1, 0, 1)
1084 -#define MPP36_UA2_TDX MPP(36, 0x4, 0, 1, 1)
1085 -#define MPP36_TDM0_SCSn MPP(36, 0x6, 0, 1, 1)
1086 +#define MPP36_UA0_CTSn MPP(36, 0x2, 0, 0, 1)
1087 +#define MPP36_UA2_TDX MPP(36, 0x4, 0, 0, 1)
1088 +#define MPP36_TDM0_SCSn MPP(36, 0x6, 0, 0, 1)
1089 #define MPP36_UNUSED MPP(36, 0x3, 0, 0, 1)
1090
1091
1092 #define MPP37_GPIO MPP(37, 0x1, 1, 1, 1)
1093 -#define MPP37_UA0_RTSn MPP(37, 0x2, 0, 1, 1)
1094 -#define MPP37_UA2_RXD MPP(37, 0x4, 1, 0, 1)
1095 -#define MPP37_SYSRST_OUTn MPP(37, 0x5, 0, 1, 1)
1096 -#define MPP37_TDM_SCLK MPP(37, 0x6, 0, 1, 1)
1097 +#define MPP37_UA0_RTSn MPP(37, 0x2, 0, 0, 1)
1098 +#define MPP37_UA2_RXD MPP(37, 0x4, 0, 0, 1)
1099 +#define MPP37_SYSRST_OUTn MPP(37, 0x5, 0, 0, 1)
1100 +#define MPP37_TDM_SCLK MPP(37, 0x6, 0, 0, 1)
1101 #define MPP37_UNUSED MPP(37, 0x3, 0, 0, 1)
1102
1103
1104
1105
1106 #define MPP38_GPIO MPP(38, 0x1, 1, 1, 1)
1107 -#define MPP38_UA1_CTSn MPP(38, 0x2, 1, 0, 1)
1108 -#define MPP38_UA3_TXD MPP(38, 0x4, 0, 1, 1)
1109 -#define MPP38_SYSRST_OUTn MPP(38, 0x5, 0, 1, 1)
1110 -#define MPP38_TDM_SMOSI MPP(38, 0x6, 0, 1, 1)
1111 +#define MPP38_UA1_CTSn MPP(38, 0x2, 0, 0, 1)
1112 +#define MPP38_UA3_TXD MPP(38, 0x4, 0, 0, 1)
1113 +#define MPP38_SYSRST_OUTn MPP(38, 0x5, 0, 0, 1)
1114 +#define MPP38_TDM_SMOSI MPP(38, 0x6, 0, 0, 1)
1115 #define MPP38_UNUSED MPP(38, 0x3, 0, 0, 1)
1116
1117
1118
1119
1120 #define MPP39_GPIO MPP(39, 0x1, 1, 1, 1)
1121 -#define MPP39_UA1_RTSn MPP(39, 0x2, 0, 1, 1)
1122 -#define MPP39_UA3_RXD MPP(39, 0x4, 1, 0, 1)
1123 -#define MPP39_SYSRST_OUTn MPP(39, 0x5, 0, 1, 1)
1124 -#define MPP39_TDM_SMISO MPP(39, 0x6, 1, 0, 1)
1125 +#define MPP39_UA1_RTSn MPP(39, 0x2, 0, 0, 1)
1126 +#define MPP39_UA3_RXD MPP(39, 0x4, 0, 0, 1)
1127 +#define MPP39_SYSRST_OUTn MPP(39, 0x5, 0, 0, 1)
1128 +#define MPP39_TDM_SMISO MPP(39, 0x6, 0, 0, 1)
1129 #define MPP39_UNUSED MPP(39, 0x3, 0, 0, 1)
1130
1131
1132
1133 #define MPP40_GPIO MPP(40, 0x1, 1, 1, 1)
1134 -#define MPP40_TDM_INTn MPP(40, 0x6, 1, 0, 1)
1135 +#define MPP40_TDM_INTn MPP(40, 0x6, 0, 0, 1)
1136 #define MPP40_UNUSED MPP(40, 0x0, 0, 0, 1)
1137
1138
1139
1140 #define MPP41_GPIO MPP(41, 0x1, 1, 1, 1)
1141 -#define MPP41_TDM_RSTn MPP(41, 0x6, 0, 1, 1)
1142 +#define MPP41_TDM_RSTn MPP(41, 0x6, 0, 0, 1)
1143 #define MPP41_UNUSED MPP(41, 0x0, 0, 0, 1)
1144
1145
1146
1147 #define MPP42_GPIO MPP(42, 0x1, 1, 1, 1)
1148 -#define MPP42_TDM_PCLK MPP(42, 0x6, 1, 1, 1)
1149 +#define MPP42_TDM_PCLK MPP(42, 0x6, 0, 0, 1)
1150 #define MPP42_UNUSED MPP(42, 0x0, 0, 0, 1)
1151
1152
1153
1154 #define MPP43_GPIO MPP(43, 0x1, 1, 1, 1)
1155 -#define MPP43_TDM_FSYNC MPP(43, 0x6, 1, 1, 1)
1156 +#define MPP43_TDM_FSYNC MPP(43, 0x6, 0, 0, 1)
1157 #define MPP43_UNUSED MPP(43, 0x0, 0, 0, 1)
1158
1159
1160
1161 #define MPP44_GPIO MPP(44, 0x1, 1, 1, 1)
1162 -#define MPP44_TDM_DRX MPP(44, 0x6, 1, 0, 1)
1163 +#define MPP44_TDM_DRX MPP(44, 0x6, 0, 0, 1)
1164 #define MPP44_UNUSED MPP(44, 0x0, 0, 0, 1)
1165
1166
1167
1168 #define MPP45_GPIO MPP(45, 0x1, 1, 1, 1)
1169 -#define MPP45_SATA0_ACTn MPP(45, 0x3, 0, 1, 1)
1170 -#define MPP45_TDM_DRX MPP(45, 0x6, 0, 1, 1)
1171 +#define MPP45_SATA0_ACTn MPP(45, 0x3, 0, 0, 1)
1172 +#define MPP45_TDM_DRX MPP(45, 0x6, 0, 0, 1)
1173 #define MPP45_UNUSED MPP(45, 0x0, 0, 0, 1)
1174
1175
1176 #define MPP46_GPIO MPP(46, 0x1, 1, 1, 1)
1177 -#define MPP46_TDM_SCSn MPP(46, 0x6, 0, 1, 1)
1178 +#define MPP46_TDM_SCSn MPP(46, 0x6, 0, 0, 1)
1179 #define MPP46_UNUSED MPP(46, 0x0, 0, 0, 1)
1180
1181
1182 @@ -323,14 +323,14 @@
1183
1184
1185 #define MPP48_GPIO MPP(48, 0x1, 1, 1, 1)
1186 -#define MPP48_SATA1_ACTn MPP(48, 0x3, 0, 1, 1)
1187 +#define MPP48_SATA1_ACTn MPP(48, 0x3, 0, 0, 1)
1188 #define MPP48_UNUSED MPP(48, 0x2, 0, 0, 1)
1189
1190
1191
1192 #define MPP49_GPIO MPP(49, 0x1, 1, 1, 1)
1193 -#define MPP49_SATA0_ACTn MPP(49, 0x3, 0, 1, 1)
1194 -#define MPP49_M_BB MPP(49, 0x4, 1, 0, 1)
1195 +#define MPP49_SATA0_ACTn MPP(49, 0x3, 0, 0, 1)
1196 +#define MPP49_M_BB MPP(49, 0x4, 0, 0, 1)
1197 #define MPP49_UNUSED MPP(49, 0x2, 0, 0, 1)
1198
1199
1200 diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
1201 index 63de2d3..14a5971 100644
1202 --- a/arch/arm/mach-omap2/board-4430sdp.c
1203 +++ b/arch/arm/mach-omap2/board-4430sdp.c
1204 @@ -49,8 +49,9 @@
1205 #define ETH_KS8851_QUART 138
1206 #define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184
1207 #define OMAP4_SFH7741_ENABLE_GPIO 188
1208 -#define HDMI_GPIO_HPD 60 /* Hot plug pin for HDMI */
1209 +#define HDMI_GPIO_CT_CP_HPD 60 /* HPD mode enable/disable */
1210 #define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */
1211 +#define HDMI_GPIO_HPD 63 /* Hotplug detect */
1212
1213 static const int sdp4430_keymap[] = {
1214 KEY(0, 0, KEY_E),
1215 @@ -578,12 +579,8 @@ static void __init omap_sfh7741prox_init(void)
1216
1217 static void sdp4430_hdmi_mux_init(void)
1218 {
1219 - /* PAD0_HDMI_HPD_PAD1_HDMI_CEC */
1220 - omap_mux_init_signal("hdmi_hpd",
1221 - OMAP_PIN_INPUT_PULLUP);
1222 omap_mux_init_signal("hdmi_cec",
1223 OMAP_PIN_INPUT_PULLUP);
1224 - /* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */
1225 omap_mux_init_signal("hdmi_ddc_scl",
1226 OMAP_PIN_INPUT_PULLUP);
1227 omap_mux_init_signal("hdmi_ddc_sda",
1228 @@ -591,8 +588,9 @@ static void sdp4430_hdmi_mux_init(void)
1229 }
1230
1231 static struct gpio sdp4430_hdmi_gpios[] = {
1232 - { HDMI_GPIO_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_hpd" },
1233 + { HDMI_GPIO_CT_CP_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ct_cp_hpd" },
1234 { HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" },
1235 + { HDMI_GPIO_HPD, GPIOF_DIR_IN, "hdmi_gpio_hpd" },
1236 };
1237
1238 static int sdp4430_panel_enable_hdmi(struct omap_dss_device *dssdev)
1239 @@ -609,26 +607,21 @@ static int sdp4430_panel_enable_hdmi(struct omap_dss_device *dssdev)
1240
1241 static void sdp4430_panel_disable_hdmi(struct omap_dss_device *dssdev)
1242 {
1243 - gpio_free(HDMI_GPIO_LS_OE);
1244 - gpio_free(HDMI_GPIO_HPD);
1245 + gpio_free_array(sdp4430_hdmi_gpios, ARRAY_SIZE(sdp4430_hdmi_gpios));
1246 }
1247
1248 +static struct omap_dss_hdmi_data sdp4430_hdmi_data = {
1249 + .hpd_gpio = HDMI_GPIO_HPD,
1250 +};
1251 +
1252 static struct omap_dss_device sdp4430_hdmi_device = {
1253 .name = "hdmi",
1254 .driver_name = "hdmi_panel",
1255 .type = OMAP_DISPLAY_TYPE_HDMI,
1256 - .clocks = {
1257 - .dispc = {
1258 - .dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK,
1259 - },
1260 - .hdmi = {
1261 - .regn = 15,
1262 - .regm2 = 1,
1263 - },
1264 - },
1265 .platform_enable = sdp4430_panel_enable_hdmi,
1266 .platform_disable = sdp4430_panel_disable_hdmi,
1267 .channel = OMAP_DSS_CHANNEL_DIGIT,
1268 + .data = &sdp4430_hdmi_data,
1269 };
1270
1271 static struct omap_dss_device *sdp4430_dss_devices[] = {
1272 @@ -645,6 +638,10 @@ void omap_4430sdp_display_init(void)
1273 {
1274 sdp4430_hdmi_mux_init();
1275 omap_display_init(&sdp4430_dss_data);
1276 +
1277 + omap_mux_init_gpio(HDMI_GPIO_LS_OE, OMAP_PIN_OUTPUT);
1278 + omap_mux_init_gpio(HDMI_GPIO_CT_CP_HPD, OMAP_PIN_OUTPUT);
1279 + omap_mux_init_gpio(HDMI_GPIO_HPD, OMAP_PIN_INPUT_PULLDOWN);
1280 }
1281
1282 #ifdef CONFIG_OMAP_MUX
1283 diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
1284 index 0cfe200..107dfc3 100644
1285 --- a/arch/arm/mach-omap2/board-omap4panda.c
1286 +++ b/arch/arm/mach-omap2/board-omap4panda.c
1287 @@ -52,8 +52,9 @@
1288 #define GPIO_HUB_NRESET 62
1289 #define GPIO_WIFI_PMENA 43
1290 #define GPIO_WIFI_IRQ 53
1291 -#define HDMI_GPIO_HPD 60 /* Hot plug pin for HDMI */
1292 +#define HDMI_GPIO_CT_CP_HPD 60 /* HPD mode enable/disable */
1293 #define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */
1294 +#define HDMI_GPIO_HPD 63 /* Hotplug detect */
1295
1296 /* wl127x BT, FM, GPS connectivity chip */
1297 static int wl1271_gpios[] = {46, -1, -1};
1298 @@ -614,12 +615,8 @@ int __init omap4_panda_dvi_init(void)
1299
1300 static void omap4_panda_hdmi_mux_init(void)
1301 {
1302 - /* PAD0_HDMI_HPD_PAD1_HDMI_CEC */
1303 - omap_mux_init_signal("hdmi_hpd",
1304 - OMAP_PIN_INPUT_PULLUP);
1305 omap_mux_init_signal("hdmi_cec",
1306 OMAP_PIN_INPUT_PULLUP);
1307 - /* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */
1308 omap_mux_init_signal("hdmi_ddc_scl",
1309 OMAP_PIN_INPUT_PULLUP);
1310 omap_mux_init_signal("hdmi_ddc_sda",
1311 @@ -627,8 +624,9 @@ static void omap4_panda_hdmi_mux_init(void)
1312 }
1313
1314 static struct gpio panda_hdmi_gpios[] = {
1315 - { HDMI_GPIO_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_hpd" },
1316 + { HDMI_GPIO_CT_CP_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ct_cp_hpd" },
1317 { HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" },
1318 + { HDMI_GPIO_HPD, GPIOF_DIR_IN, "hdmi_gpio_hpd" },
1319 };
1320
1321 static int omap4_panda_panel_enable_hdmi(struct omap_dss_device *dssdev)
1322 @@ -645,10 +643,13 @@ static int omap4_panda_panel_enable_hdmi(struct omap_dss_device *dssdev)
1323
1324 static void omap4_panda_panel_disable_hdmi(struct omap_dss_device *dssdev)
1325 {
1326 - gpio_free(HDMI_GPIO_LS_OE);
1327 - gpio_free(HDMI_GPIO_HPD);
1328 + gpio_free_array(panda_hdmi_gpios, ARRAY_SIZE(panda_hdmi_gpios));
1329 }
1330
1331 +static struct omap_dss_hdmi_data omap4_panda_hdmi_data = {
1332 + .hpd_gpio = HDMI_GPIO_HPD,
1333 +};
1334 +
1335 static struct omap_dss_device omap4_panda_hdmi_device = {
1336 .name = "hdmi",
1337 .driver_name = "hdmi_panel",
1338 @@ -656,6 +657,7 @@ static struct omap_dss_device omap4_panda_hdmi_device = {
1339 .platform_enable = omap4_panda_panel_enable_hdmi,
1340 .platform_disable = omap4_panda_panel_disable_hdmi,
1341 .channel = OMAP_DSS_CHANNEL_DIGIT,
1342 + .data = &omap4_panda_hdmi_data,
1343 };
1344
1345 static struct omap_dss_device *omap4_panda_dss_devices[] = {
1346 @@ -679,6 +681,10 @@ void omap4_panda_display_init(void)
1347
1348 omap4_panda_hdmi_mux_init();
1349 omap_display_init(&omap4_panda_dss_data);
1350 +
1351 + omap_mux_init_gpio(HDMI_GPIO_LS_OE, OMAP_PIN_OUTPUT);
1352 + omap_mux_init_gpio(HDMI_GPIO_CT_CP_HPD, OMAP_PIN_OUTPUT);
1353 + omap_mux_init_gpio(HDMI_GPIO_HPD, OMAP_PIN_INPUT_PULLDOWN);
1354 }
1355
1356 static void __init omap4_panda_init(void)
1357 diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
1358 index 0ab531d..8a98da0 100644
1359 --- a/arch/arm/mach-orion5x/common.c
1360 +++ b/arch/arm/mach-orion5x/common.c
1361 @@ -29,6 +29,7 @@
1362 #include <mach/hardware.h>
1363 #include <mach/orion5x.h>
1364 #include <plat/orion_nand.h>
1365 +#include <plat/ehci-orion.h>
1366 #include <plat/time.h>
1367 #include <plat/common.h>
1368 #include "common.h"
1369 @@ -72,7 +73,8 @@ void __init orion5x_map_io(void)
1370 void __init orion5x_ehci0_init(void)
1371 {
1372 orion_ehci_init(&orion5x_mbus_dram_info,
1373 - ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL);
1374 + ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL,
1375 + EHCI_PHY_ORION);
1376 }
1377
1378
1379 diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
1380 index b6ba103..7e47888 100644
1381 --- a/arch/arm/mm/proc-v7.S
1382 +++ b/arch/arm/mm/proc-v7.S
1383 @@ -344,9 +344,7 @@ __v7_setup:
1384 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
1385 #endif
1386 #ifdef CONFIG_ARM_ERRATA_743622
1387 - teq r6, #0x20 @ present in r2p0
1388 - teqne r6, #0x21 @ present in r2p1
1389 - teqne r6, #0x22 @ present in r2p2
1390 + teq r5, #0x00200000 @ only present in r2p*
1391 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
1392 orreq r10, r10, #1 << 6 @ set bit #6
1393 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
1394 diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
1395 index 9e5451b..11dce87 100644
1396 --- a/arch/arm/plat-orion/common.c
1397 +++ b/arch/arm/plat-orion/common.c
1398 @@ -806,10 +806,7 @@ void __init orion_xor1_init(unsigned long mapbase_low,
1399 /*****************************************************************************
1400 * EHCI
1401 ****************************************************************************/
1402 -static struct orion_ehci_data orion_ehci_data = {
1403 - .phy_version = EHCI_PHY_NA,
1404 -};
1405 -
1406 +static struct orion_ehci_data orion_ehci_data;
1407 static u64 ehci_dmamask = DMA_BIT_MASK(32);
1408
1409
1410 @@ -830,9 +827,11 @@ static struct platform_device orion_ehci = {
1411
1412 void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info,
1413 unsigned long mapbase,
1414 - unsigned long irq)
1415 + unsigned long irq,
1416 + enum orion_ehci_phy_ver phy_version)
1417 {
1418 orion_ehci_data.dram = mbus_dram_info;
1419 + orion_ehci_data.phy_version = phy_version;
1420 fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1,
1421 irq);
1422
1423 diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h
1424 index a63c357..a2c0e31 100644
1425 --- a/arch/arm/plat-orion/include/plat/common.h
1426 +++ b/arch/arm/plat-orion/include/plat/common.h
1427 @@ -95,7 +95,8 @@ void __init orion_xor1_init(unsigned long mapbase_low,
1428
1429 void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info,
1430 unsigned long mapbase,
1431 - unsigned long irq);
1432 + unsigned long irq,
1433 + enum orion_ehci_phy_ver phy_version);
1434
1435 void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info,
1436 unsigned long mapbase,
1437 diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c
1438 index 9155343..3b1e17b 100644
1439 --- a/arch/arm/plat-orion/mpp.c
1440 +++ b/arch/arm/plat-orion/mpp.c
1441 @@ -64,8 +64,7 @@ void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
1442 gpio_mode |= GPIO_INPUT_OK;
1443 if (*mpp_list & MPP_OUTPUT_MASK)
1444 gpio_mode |= GPIO_OUTPUT_OK;
1445 - if (sel != 0)
1446 - gpio_mode = 0;
1447 +
1448 orion_gpio_set_valid(num, gpio_mode);
1449 }
1450
1451 diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
1452 index 539bd0e..0719f49 100644
1453 --- a/arch/arm/plat-s3c24xx/dma.c
1454 +++ b/arch/arm/plat-s3c24xx/dma.c
1455 @@ -1249,7 +1249,7 @@ static void s3c2410_dma_resume(void)
1456 struct s3c2410_dma_chan *cp = s3c2410_chans + dma_channels - 1;
1457 int channel;
1458
1459 - for (channel = dma_channels - 1; channel >= 0; cp++, channel--)
1460 + for (channel = dma_channels - 1; channel >= 0; cp--, channel--)
1461 s3c2410_dma_resume_chan(cp);
1462 }
1463
1464 diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig
1465 index e9d689b..c614484 100644
1466 --- a/arch/avr32/Kconfig
1467 +++ b/arch/avr32/Kconfig
1468 @@ -8,6 +8,7 @@ config AVR32
1469 select HAVE_KPROBES
1470 select HAVE_GENERIC_HARDIRQS
1471 select GENERIC_IRQ_PROBE
1472 + select GENERIC_ATOMIC64
1473 select HARDIRQS_SW_RESEND
1474 select GENERIC_IRQ_SHOW
1475 help
1476 diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
1477 index c03fef7..9b922b1 100644
1478 --- a/arch/s390/Kconfig
1479 +++ b/arch/s390/Kconfig
1480 @@ -228,6 +228,9 @@ config COMPAT
1481 config SYSVIPC_COMPAT
1482 def_bool y if COMPAT && SYSVIPC
1483
1484 +config KEYS_COMPAT
1485 + def_bool y if COMPAT && KEYS
1486 +
1487 config AUDIT_ARCH
1488 def_bool y
1489
1490 diff --git a/arch/s390/include/asm/compat.h b/arch/s390/include/asm/compat.h
1491 index da359ca..f7b74bc 100644
1492 --- a/arch/s390/include/asm/compat.h
1493 +++ b/arch/s390/include/asm/compat.h
1494 @@ -172,13 +172,6 @@ static inline int is_compat_task(void)
1495 return is_32bit_task();
1496 }
1497
1498 -#else
1499 -
1500 -static inline int is_compat_task(void)
1501 -{
1502 - return 0;
1503 -}
1504 -
1505 #endif
1506
1507 static inline void __user *arch_compat_alloc_user_space(long len)
1508 diff --git a/arch/s390/kernel/process.c b/arch/s390/kernel/process.c
1509 index 541a750..abdc2b1 100644
1510 --- a/arch/s390/kernel/process.c
1511 +++ b/arch/s390/kernel/process.c
1512 @@ -28,7 +28,6 @@
1513 #include <asm/irq.h>
1514 #include <asm/timer.h>
1515 #include <asm/nmi.h>
1516 -#include <asm/compat.h>
1517 #include <asm/smp.h>
1518 #include "entry.h"
1519
1520 diff --git a/arch/s390/kernel/ptrace.c b/arch/s390/kernel/ptrace.c
1521 index 5804cfa..5c55466 100644
1522 --- a/arch/s390/kernel/ptrace.c
1523 +++ b/arch/s390/kernel/ptrace.c
1524 @@ -20,8 +20,8 @@
1525 #include <linux/regset.h>
1526 #include <linux/tracehook.h>
1527 #include <linux/seccomp.h>
1528 +#include <linux/compat.h>
1529 #include <trace/syscall.h>
1530 -#include <asm/compat.h>
1531 #include <asm/segment.h>
1532 #include <asm/page.h>
1533 #include <asm/pgtable.h>
1534 diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c
1535 index 0c35dee..7547f57 100644
1536 --- a/arch/s390/kernel/setup.c
1537 +++ b/arch/s390/kernel/setup.c
1538 @@ -42,6 +42,7 @@
1539 #include <linux/reboot.h>
1540 #include <linux/topology.h>
1541 #include <linux/ftrace.h>
1542 +#include <linux/compat.h>
1543
1544 #include <asm/ipl.h>
1545 #include <asm/uaccess.h>
1546 @@ -55,7 +56,6 @@
1547 #include <asm/ptrace.h>
1548 #include <asm/sections.h>
1549 #include <asm/ebcdic.h>
1550 -#include <asm/compat.h>
1551 #include <asm/kvm_virtio.h>
1552
1553 long psw_kernel_bits = (PSW_BASE_BITS | PSW_MASK_DAT | PSW_ASC_PRIMARY |
1554 diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c
1555 index fe103e8..d814f79 100644
1556 --- a/arch/s390/mm/fault.c
1557 +++ b/arch/s390/mm/fault.c
1558 @@ -36,7 +36,6 @@
1559 #include <asm/pgtable.h>
1560 #include <asm/irq.h>
1561 #include <asm/mmu_context.h>
1562 -#include <asm/compat.h>
1563 #include "../kernel/entry.h"
1564
1565 #ifndef CONFIG_64BIT
1566 diff --git a/arch/s390/mm/mmap.c b/arch/s390/mm/mmap.c
1567 index c9a9f7f..c0cf9ce 100644
1568 --- a/arch/s390/mm/mmap.c
1569 +++ b/arch/s390/mm/mmap.c
1570 @@ -28,8 +28,8 @@
1571 #include <linux/mm.h>
1572 #include <linux/module.h>
1573 #include <linux/random.h>
1574 +#include <linux/compat.h>
1575 #include <asm/pgalloc.h>
1576 -#include <asm/compat.h>
1577
1578 static unsigned long stack_maxrandom_size(void)
1579 {
1580 diff --git a/block/bsg.c b/block/bsg.c
1581 index 0c8b64a..792ead6 100644
1582 --- a/block/bsg.c
1583 +++ b/block/bsg.c
1584 @@ -985,7 +985,8 @@ void bsg_unregister_queue(struct request_queue *q)
1585
1586 mutex_lock(&bsg_mutex);
1587 idr_remove(&bsg_minor_idr, bcd->minor);
1588 - sysfs_remove_link(&q->kobj, "bsg");
1589 + if (q->kobj.sd)
1590 + sysfs_remove_link(&q->kobj, "bsg");
1591 device_unregister(bcd->class_dev);
1592 bcd->class_dev = NULL;
1593 kref_put(&bcd->ref, bsg_kref_release_function);
1594 diff --git a/drivers/acpi/sleep.c b/drivers/acpi/sleep.c
1595 index 6c94960..0bd4832 100644
1596 --- a/drivers/acpi/sleep.c
1597 +++ b/drivers/acpi/sleep.c
1598 @@ -428,6 +428,22 @@ static struct dmi_system_id __initdata acpisleep_dmi_table[] = {
1599 DMI_MATCH(DMI_PRODUCT_NAME, "1000 Series"),
1600 },
1601 },
1602 + {
1603 + .callback = init_nvs_nosave,
1604 + .ident = "Asus K54C",
1605 + .matches = {
1606 + DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."),
1607 + DMI_MATCH(DMI_PRODUCT_NAME, "K54C"),
1608 + },
1609 + },
1610 + {
1611 + .callback = init_nvs_nosave,
1612 + .ident = "Asus K54HR",
1613 + .matches = {
1614 + DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."),
1615 + DMI_MATCH(DMI_PRODUCT_NAME, "K54HR"),
1616 + },
1617 + },
1618 {},
1619 };
1620 #endif /* CONFIG_SUSPEND */
1621 diff --git a/drivers/crypto/mv_cesa.c b/drivers/crypto/mv_cesa.c
1622 index 38a3297..f53dd83 100644
1623 --- a/drivers/crypto/mv_cesa.c
1624 +++ b/drivers/crypto/mv_cesa.c
1625 @@ -713,6 +713,7 @@ static int mv_hash_final(struct ahash_request *req)
1626 {
1627 struct mv_req_hash_ctx *ctx = ahash_request_ctx(req);
1628
1629 + ahash_request_set_crypt(req, NULL, req->result, 0);
1630 mv_update_hash_req_ctx(ctx, 1, 0);
1631 return mv_handle_req(&req->base);
1632 }
1633 diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
1634 index 673f0d2..56315cb 100644
1635 --- a/drivers/gpu/drm/i915/i915_reg.h
1636 +++ b/drivers/gpu/drm/i915/i915_reg.h
1637 @@ -2847,6 +2847,20 @@
1638 #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
1639 #define DISP_FBC_WM_DIS (1<<15)
1640
1641 +/* GEN7 chicken */
1642 +#define GEN7_COMMON_SLICE_CHICKEN1 0x7010
1643 +# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
1644 +
1645 +#define GEN7_L3CNTLREG1 0xB01C
1646 +#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C
1647 +
1648 +#define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
1649 +#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
1650 +
1651 +/* WaCatErrorRejectionIssue */
1652 +#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
1653 +#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
1654 +
1655 /* PCH */
1656
1657 /* south display engine interrupt */
1658 @@ -3371,6 +3385,7 @@
1659 #define GT_FIFO_FREE_ENTRIES 0x120008
1660
1661 #define GEN6_UCGCTL2 0x9404
1662 +# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
1663 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
1664 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
1665
1666 diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
1667 index fed87d6..57f9043 100644
1668 --- a/drivers/gpu/drm/i915/intel_display.c
1669 +++ b/drivers/gpu/drm/i915/intel_display.c
1670 @@ -5265,7 +5265,7 @@ void intel_crtc_load_lut(struct drm_crtc *crtc)
1671 int i;
1672
1673 /* The clocks have to be on to load the palette. */
1674 - if (!crtc->enabled)
1675 + if (!crtc->enabled || !intel_crtc->active)
1676 return;
1677
1678 /* use legacy palette for Ironlake */
1679 @@ -7457,8 +7457,28 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
1680 I915_WRITE(WM2_LP_ILK, 0);
1681 I915_WRITE(WM1_LP_ILK, 0);
1682
1683 + /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
1684 + * This implements the WaDisableRCZUnitClockGating workaround.
1685 + */
1686 + I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
1687 +
1688 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
1689
1690 + /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
1691 + I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
1692 + GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
1693 +
1694 + /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
1695 + I915_WRITE(GEN7_L3CNTLREG1,
1696 + GEN7_WA_FOR_GEN7_L3_CONTROL);
1697 + I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
1698 + GEN7_WA_L3_CHICKEN_MODE);
1699 +
1700 + /* This is required by WaCatErrorRejectionIssue */
1701 + I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
1702 + I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
1703 + GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
1704 +
1705 for_each_pipe(pipe)
1706 I915_WRITE(DSPCNTR(pipe),
1707 I915_READ(DSPCNTR(pipe)) |
1708 diff --git a/drivers/gpu/drm/radeon/r600_blit_shaders.c b/drivers/gpu/drm/radeon/r600_blit_shaders.c
1709 index 2d1f6c5..73e2c7c 100644
1710 --- a/drivers/gpu/drm/radeon/r600_blit_shaders.c
1711 +++ b/drivers/gpu/drm/radeon/r600_blit_shaders.c
1712 @@ -314,6 +314,10 @@ const u32 r6xx_default_state[] =
1713 0x00000000, /* VGT_VTX_CNT_EN */
1714
1715 0xc0016900,
1716 + 0x000000d4,
1717 + 0x00000000, /* SX_MISC */
1718 +
1719 + 0xc0016900,
1720 0x000002c8,
1721 0x00000000, /* VGT_STRMOUT_BUFFER_EN */
1722
1723 @@ -626,6 +630,10 @@ const u32 r7xx_default_state[] =
1724 0x00000000, /* VGT_VTX_CNT_EN */
1725
1726 0xc0016900,
1727 + 0x000000d4,
1728 + 0x00000000, /* SX_MISC */
1729 +
1730 + 0xc0016900,
1731 0x000002c8,
1732 0x00000000, /* VGT_STRMOUT_BUFFER_EN */
1733
1734 diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h
1735 index e0a28ad..6781fe0 100644
1736 --- a/drivers/hid/hid-ids.h
1737 +++ b/drivers/hid/hid-ids.h
1738 @@ -59,6 +59,9 @@
1739 #define USB_VENDOR_ID_AIRCABLE 0x16CA
1740 #define USB_DEVICE_ID_AIRCABLE1 0x1502
1741
1742 +#define USB_VENDOR_ID_AIREN 0x1a2c
1743 +#define USB_DEVICE_ID_AIREN_SLIMPLUS 0x0002
1744 +
1745 #define USB_VENDOR_ID_ALCOR 0x058f
1746 #define USB_DEVICE_ID_ALCOR_USBRS232 0x9720
1747
1748 diff --git a/drivers/hid/usbhid/hid-quirks.c b/drivers/hid/usbhid/hid-quirks.c
1749 index 3146fdc..85c845f 100644
1750 --- a/drivers/hid/usbhid/hid-quirks.c
1751 +++ b/drivers/hid/usbhid/hid-quirks.c
1752 @@ -52,6 +52,7 @@ static const struct hid_blacklist {
1753 { USB_VENDOR_ID_PLAYDOTCOM, USB_DEVICE_ID_PLAYDOTCOM_EMS_USBII, HID_QUIRK_MULTI_INPUT },
1754 { USB_VENDOR_ID_TOUCHPACK, USB_DEVICE_ID_TOUCHPACK_RTS, HID_QUIRK_MULTI_INPUT },
1755
1756 + { USB_VENDOR_ID_AIREN, USB_DEVICE_ID_AIREN_SLIMPLUS, HID_QUIRK_NOGET },
1757 { USB_VENDOR_ID_ATEN, USB_DEVICE_ID_ATEN_UC100KM, HID_QUIRK_NOGET },
1758 { USB_VENDOR_ID_ATEN, USB_DEVICE_ID_ATEN_CS124U, HID_QUIRK_NOGET },
1759 { USB_VENDOR_ID_ATEN, USB_DEVICE_ID_ATEN_2PORTKVM, HID_QUIRK_NOGET },
1760 diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
1761 index 5f888f7..6030f20 100644
1762 --- a/drivers/hwmon/Kconfig
1763 +++ b/drivers/hwmon/Kconfig
1764 @@ -474,8 +474,9 @@ config SENSORS_JC42
1765 If you say yes here, you get support for JEDEC JC42.4 compliant
1766 temperature sensors, which are used on many DDR3 memory modules for
1767 mobile devices and servers. Support will include, but not be limited
1768 - to, ADT7408, CAT34TS02, CAT6095, MAX6604, MCP9805, MCP98242, MCP98243,
1769 - MCP9843, SE97, SE98, STTS424(E), TSE2002B3, and TS3000B3.
1770 + to, ADT7408, AT30TS00, CAT34TS02, CAT6095, MAX6604, MCP9804, MCP9805,
1771 + MCP98242, MCP98243, MCP9843, SE97, SE98, STTS424(E), STTS2002,
1772 + STTS3000, TSE2002B3, TSE2002GB2, TS3000B3, and TS3000GB2.
1773
1774 This driver can also be built as a module. If so, the module
1775 will be called jc42.
1776 diff --git a/drivers/hwmon/jc42.c b/drivers/hwmon/jc42.c
1777 index 02cebb7..ed43924 100644
1778 --- a/drivers/hwmon/jc42.c
1779 +++ b/drivers/hwmon/jc42.c
1780 @@ -64,6 +64,7 @@ static const unsigned short normal_i2c[] = {
1781
1782 /* Manufacturer IDs */
1783 #define ADT_MANID 0x11d4 /* Analog Devices */
1784 +#define ATMEL_MANID 0x001f /* Atmel */
1785 #define MAX_MANID 0x004d /* Maxim */
1786 #define IDT_MANID 0x00b3 /* IDT */
1787 #define MCP_MANID 0x0054 /* Microchip */
1788 @@ -77,15 +78,25 @@ static const unsigned short normal_i2c[] = {
1789 #define ADT7408_DEVID 0x0801
1790 #define ADT7408_DEVID_MASK 0xffff
1791
1792 +/* Atmel */
1793 +#define AT30TS00_DEVID 0x8201
1794 +#define AT30TS00_DEVID_MASK 0xffff
1795 +
1796 /* IDT */
1797 #define TS3000B3_DEVID 0x2903 /* Also matches TSE2002B3 */
1798 #define TS3000B3_DEVID_MASK 0xffff
1799
1800 +#define TS3000GB2_DEVID 0x2912 /* Also matches TSE2002GB2 */
1801 +#define TS3000GB2_DEVID_MASK 0xffff
1802 +
1803 /* Maxim */
1804 #define MAX6604_DEVID 0x3e00
1805 #define MAX6604_DEVID_MASK 0xffff
1806
1807 /* Microchip */
1808 +#define MCP9804_DEVID 0x0200
1809 +#define MCP9804_DEVID_MASK 0xfffc
1810 +
1811 #define MCP98242_DEVID 0x2000
1812 #define MCP98242_DEVID_MASK 0xfffc
1813
1814 @@ -113,6 +124,12 @@ static const unsigned short normal_i2c[] = {
1815 #define STTS424E_DEVID 0x0000
1816 #define STTS424E_DEVID_MASK 0xfffe
1817
1818 +#define STTS2002_DEVID 0x0300
1819 +#define STTS2002_DEVID_MASK 0xffff
1820 +
1821 +#define STTS3000_DEVID 0x0200
1822 +#define STTS3000_DEVID_MASK 0xffff
1823 +
1824 static u16 jc42_hysteresis[] = { 0, 1500, 3000, 6000 };
1825
1826 struct jc42_chips {
1827 @@ -123,8 +140,11 @@ struct jc42_chips {
1828
1829 static struct jc42_chips jc42_chips[] = {
1830 { ADT_MANID, ADT7408_DEVID, ADT7408_DEVID_MASK },
1831 + { ATMEL_MANID, AT30TS00_DEVID, AT30TS00_DEVID_MASK },
1832 { IDT_MANID, TS3000B3_DEVID, TS3000B3_DEVID_MASK },
1833 + { IDT_MANID, TS3000GB2_DEVID, TS3000GB2_DEVID_MASK },
1834 { MAX_MANID, MAX6604_DEVID, MAX6604_DEVID_MASK },
1835 + { MCP_MANID, MCP9804_DEVID, MCP9804_DEVID_MASK },
1836 { MCP_MANID, MCP98242_DEVID, MCP98242_DEVID_MASK },
1837 { MCP_MANID, MCP98243_DEVID, MCP98243_DEVID_MASK },
1838 { MCP_MANID, MCP9843_DEVID, MCP9843_DEVID_MASK },
1839 @@ -133,6 +153,8 @@ static struct jc42_chips jc42_chips[] = {
1840 { NXP_MANID, SE98_DEVID, SE98_DEVID_MASK },
1841 { STM_MANID, STTS424_DEVID, STTS424_DEVID_MASK },
1842 { STM_MANID, STTS424E_DEVID, STTS424E_DEVID_MASK },
1843 + { STM_MANID, STTS2002_DEVID, STTS2002_DEVID_MASK },
1844 + { STM_MANID, STTS3000_DEVID, STTS3000_DEVID_MASK },
1845 };
1846
1847 /* Each client has this additional data */
1848 @@ -161,10 +183,12 @@ static struct jc42_data *jc42_update_device(struct device *dev);
1849
1850 static const struct i2c_device_id jc42_id[] = {
1851 { "adt7408", 0 },
1852 + { "at30ts00", 0 },
1853 { "cat94ts02", 0 },
1854 { "cat6095", 0 },
1855 { "jc42", 0 },
1856 { "max6604", 0 },
1857 + { "mcp9804", 0 },
1858 { "mcp9805", 0 },
1859 { "mcp98242", 0 },
1860 { "mcp98243", 0 },
1861 @@ -173,8 +197,10 @@ static const struct i2c_device_id jc42_id[] = {
1862 { "se97b", 0 },
1863 { "se98", 0 },
1864 { "stts424", 0 },
1865 - { "tse2002b3", 0 },
1866 - { "ts3000b3", 0 },
1867 + { "stts2002", 0 },
1868 + { "stts3000", 0 },
1869 + { "tse2002", 0 },
1870 + { "ts3000", 0 },
1871 { }
1872 };
1873 MODULE_DEVICE_TABLE(i2c, jc42_id);
1874 diff --git a/drivers/hwmon/pmbus_core.c b/drivers/hwmon/pmbus_core.c
1875 index 8e31a8e..ffa54dd 100644
1876 --- a/drivers/hwmon/pmbus_core.c
1877 +++ b/drivers/hwmon/pmbus_core.c
1878 @@ -50,7 +50,8 @@
1879 lcrit_alarm, crit_alarm */
1880 #define PMBUS_IOUT_BOOLEANS_PER_PAGE 3 /* alarm, lcrit_alarm,
1881 crit_alarm */
1882 -#define PMBUS_POUT_BOOLEANS_PER_PAGE 2 /* alarm, crit_alarm */
1883 +#define PMBUS_POUT_BOOLEANS_PER_PAGE 3 /* cap_alarm, alarm, crit_alarm
1884 + */
1885 #define PMBUS_MAX_BOOLEANS_PER_FAN 2 /* alarm, fault */
1886 #define PMBUS_MAX_BOOLEANS_PER_TEMP 4 /* min_alarm, max_alarm,
1887 lcrit_alarm, crit_alarm */
1888 diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c
1889 index 7e78f7c..3d471d5 100644
1890 --- a/drivers/i2c/busses/i2c-mxs.c
1891 +++ b/drivers/i2c/busses/i2c-mxs.c
1892 @@ -72,6 +72,7 @@
1893
1894 #define MXS_I2C_QUEUESTAT (0x70)
1895 #define MXS_I2C_QUEUESTAT_RD_QUEUE_EMPTY 0x00002000
1896 +#define MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK 0x0000001F
1897
1898 #define MXS_I2C_QUEUECMD (0x80)
1899
1900 @@ -219,14 +220,14 @@ static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
1901 int ret;
1902 int flags;
1903
1904 - init_completion(&i2c->cmd_complete);
1905 -
1906 dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
1907 msg->addr, msg->len, msg->flags, stop);
1908
1909 if (msg->len == 0)
1910 return -EINVAL;
1911
1912 + init_completion(&i2c->cmd_complete);
1913 +
1914 flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
1915
1916 if (msg->flags & I2C_M_RD)
1917 @@ -286,6 +287,7 @@ static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
1918 {
1919 struct mxs_i2c_dev *i2c = dev_id;
1920 u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK;
1921 + bool is_last_cmd;
1922
1923 if (!stat)
1924 return IRQ_NONE;
1925 @@ -300,9 +302,14 @@ static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
1926 else
1927 i2c->cmd_err = 0;
1928
1929 - complete(&i2c->cmd_complete);
1930 + is_last_cmd = (readl(i2c->regs + MXS_I2C_QUEUESTAT) &
1931 + MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK) == 0;
1932 +
1933 + if (is_last_cmd || i2c->cmd_err)
1934 + complete(&i2c->cmd_complete);
1935
1936 writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);
1937 +
1938 return IRQ_HANDLED;
1939 }
1940
1941 diff --git a/drivers/input/mouse/alps.c b/drivers/input/mouse/alps.c
1942 index 99d5876..0b99443 100644
1943 --- a/drivers/input/mouse/alps.c
1944 +++ b/drivers/input/mouse/alps.c
1945 @@ -426,7 +426,9 @@ static const struct alps_model_info *alps_get_model(struct psmouse *psmouse, int
1946
1947 /*
1948 * First try "E6 report".
1949 - * ALPS should return 0,0,10 or 0,0,100
1950 + * ALPS should return 0,0,10 or 0,0,100 if no buttons are pressed.
1951 + * The bits 0-2 of the first byte will be 1s if some buttons are
1952 + * pressed.
1953 */
1954 param[0] = 0;
1955 if (ps2_command(ps2dev, param, PSMOUSE_CMD_SETRES) ||
1956 @@ -441,7 +443,8 @@ static const struct alps_model_info *alps_get_model(struct psmouse *psmouse, int
1957
1958 dbg("E6 report: %2.2x %2.2x %2.2x", param[0], param[1], param[2]);
1959
1960 - if (param[0] != 0 || param[1] != 0 || (param[2] != 10 && param[2] != 100))
1961 + if ((param[0] & 0xf8) != 0 || param[1] != 0 ||
1962 + (param[2] != 10 && param[2] != 100))
1963 return NULL;
1964
1965 /*
1966 diff --git a/drivers/md/dm-io.c b/drivers/md/dm-io.c
1967 index ad2eba4..ea5dd28 100644
1968 --- a/drivers/md/dm-io.c
1969 +++ b/drivers/md/dm-io.c
1970 @@ -296,6 +296,8 @@ static void do_region(int rw, unsigned region, struct dm_io_region *where,
1971 unsigned offset;
1972 unsigned num_bvecs;
1973 sector_t remaining = where->count;
1974 + struct request_queue *q = bdev_get_queue(where->bdev);
1975 + sector_t discard_sectors;
1976
1977 /*
1978 * where->count may be zero if rw holds a flush and we need to
1979 @@ -305,9 +307,12 @@ static void do_region(int rw, unsigned region, struct dm_io_region *where,
1980 /*
1981 * Allocate a suitably sized-bio.
1982 */
1983 - num_bvecs = dm_sector_div_up(remaining,
1984 - (PAGE_SIZE >> SECTOR_SHIFT));
1985 - num_bvecs = min_t(int, bio_get_nr_vecs(where->bdev), num_bvecs);
1986 + if (rw & REQ_DISCARD)
1987 + num_bvecs = 1;
1988 + else
1989 + num_bvecs = min_t(int, bio_get_nr_vecs(where->bdev),
1990 + dm_sector_div_up(remaining, (PAGE_SIZE >> SECTOR_SHIFT)));
1991 +
1992 bio = bio_alloc_bioset(GFP_NOIO, num_bvecs, io->client->bios);
1993 bio->bi_sector = where->sector + (where->count - remaining);
1994 bio->bi_bdev = where->bdev;
1995 @@ -315,10 +320,14 @@ static void do_region(int rw, unsigned region, struct dm_io_region *where,
1996 bio->bi_destructor = dm_bio_destructor;
1997 store_io_and_region_in_bio(bio, io, region);
1998
1999 - /*
2000 - * Try and add as many pages as possible.
2001 - */
2002 - while (remaining) {
2003 + if (rw & REQ_DISCARD) {
2004 + discard_sectors = min_t(sector_t, q->limits.max_discard_sectors, remaining);
2005 + bio->bi_size = discard_sectors << SECTOR_SHIFT;
2006 + remaining -= discard_sectors;
2007 + } else while (remaining) {
2008 + /*
2009 + * Try and add as many pages as possible.
2010 + */
2011 dp->get_page(dp, &page, &len, &offset);
2012 len = min(len, to_bytes(remaining));
2013 if (!bio_add_page(bio, page, len, offset))
2014 diff --git a/drivers/md/dm-raid.c b/drivers/md/dm-raid.c
2015 index e5d8904..437ae18 100644
2016 --- a/drivers/md/dm-raid.c
2017 +++ b/drivers/md/dm-raid.c
2018 @@ -468,6 +468,7 @@ static int raid_ctr(struct dm_target *ti, unsigned argc, char **argv)
2019 INIT_WORK(&rs->md.event_work, do_table_event);
2020 ti->split_io = rs->md.chunk_sectors;
2021 ti->private = rs;
2022 + ti->num_flush_requests = 1;
2023
2024 mutex_lock(&rs->md.reconfig_mutex);
2025 ret = md_run(&rs->md);
2026 diff --git a/drivers/mfd/cs5535-mfd.c b/drivers/mfd/cs5535-mfd.c
2027 index 155fa04..e488a78 100644
2028 --- a/drivers/mfd/cs5535-mfd.c
2029 +++ b/drivers/mfd/cs5535-mfd.c
2030 @@ -179,7 +179,7 @@ static struct pci_device_id cs5535_mfd_pci_tbl[] = {
2031 };
2032 MODULE_DEVICE_TABLE(pci, cs5535_mfd_pci_tbl);
2033
2034 -static struct pci_driver cs5535_mfd_drv = {
2035 +static struct pci_driver cs5535_mfd_driver = {
2036 .name = DRV_NAME,
2037 .id_table = cs5535_mfd_pci_tbl,
2038 .probe = cs5535_mfd_probe,
2039 @@ -188,12 +188,12 @@ static struct pci_driver cs5535_mfd_drv = {
2040
2041 static int __init cs5535_mfd_init(void)
2042 {
2043 - return pci_register_driver(&cs5535_mfd_drv);
2044 + return pci_register_driver(&cs5535_mfd_driver);
2045 }
2046
2047 static void __exit cs5535_mfd_exit(void)
2048 {
2049 - pci_unregister_driver(&cs5535_mfd_drv);
2050 + pci_unregister_driver(&cs5535_mfd_driver);
2051 }
2052
2053 module_init(cs5535_mfd_init);
2054 diff --git a/drivers/mfd/mfd-core.c b/drivers/mfd/mfd-core.c
2055 index 0902523..acf9dad 100644
2056 --- a/drivers/mfd/mfd-core.c
2057 +++ b/drivers/mfd/mfd-core.c
2058 @@ -122,7 +122,7 @@ static int mfd_add_device(struct device *parent, int id,
2059 }
2060
2061 if (!cell->ignore_resource_conflicts) {
2062 - ret = acpi_check_resource_conflict(res);
2063 + ret = acpi_check_resource_conflict(&res[r]);
2064 if (ret)
2065 goto fail_res;
2066 }
2067 diff --git a/drivers/misc/cs5535-mfgpt.c b/drivers/misc/cs5535-mfgpt.c
2068 index bc685bf..87a390d 100644
2069 --- a/drivers/misc/cs5535-mfgpt.c
2070 +++ b/drivers/misc/cs5535-mfgpt.c
2071 @@ -262,7 +262,7 @@ static void __init reset_all_timers(void)
2072 * In other cases (such as with VSAless OpenFirmware), the system firmware
2073 * leaves timers available for us to use.
2074 */
2075 -static int __init scan_timers(struct cs5535_mfgpt_chip *mfgpt)
2076 +static int __devinit scan_timers(struct cs5535_mfgpt_chip *mfgpt)
2077 {
2078 struct cs5535_mfgpt_timer timer = { .chip = mfgpt };
2079 unsigned long flags;
2080 diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
2081 index ba31abe..92e5437 100644
2082 --- a/drivers/mmc/host/sdhci-esdhc-imx.c
2083 +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
2084 @@ -139,8 +139,9 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
2085 imx_data->scratchpad = val;
2086 return;
2087 case SDHCI_COMMAND:
2088 - if ((host->cmd->opcode == MMC_STOP_TRANSMISSION)
2089 - && (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
2090 + if ((host->cmd->opcode == MMC_STOP_TRANSMISSION ||
2091 + host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
2092 + (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
2093 val |= SDHCI_CMD_ABORTCMD;
2094 writel(val << 16 | imx_data->scratchpad,
2095 host->ioaddr + SDHCI_TRANSFER_MODE);
2096 diff --git a/drivers/net/usb/cdc_ether.c b/drivers/net/usb/cdc_ether.c
2097 index c924ea2..13919dd 100644
2098 --- a/drivers/net/usb/cdc_ether.c
2099 +++ b/drivers/net/usb/cdc_ether.c
2100 @@ -570,6 +570,13 @@ static const struct usb_device_id products [] = {
2101 .driver_info = (unsigned long)&wwan_info,
2102 },
2103
2104 +/* Logitech Harmony 900 - uses the pseudo-MDLM (BLAN) driver */
2105 +{
2106 + USB_DEVICE_AND_INTERFACE_INFO(0x046d, 0xc11f, USB_CLASS_COMM,
2107 + USB_CDC_SUBCLASS_MDLM, USB_CDC_PROTO_NONE),
2108 + .driver_info = 0,
2109 +},
2110 +
2111 /*
2112 * WHITELIST!!!
2113 *
2114 diff --git a/drivers/net/usb/usbnet.c b/drivers/net/usb/usbnet.c
2115 index ce395fe..4918cf5 100644
2116 --- a/drivers/net/usb/usbnet.c
2117 +++ b/drivers/net/usb/usbnet.c
2118 @@ -585,6 +585,7 @@ static int unlink_urbs (struct usbnet *dev, struct sk_buff_head *q)
2119 entry = (struct skb_data *) skb->cb;
2120 urb = entry->urb;
2121
2122 + spin_unlock_irqrestore(&q->lock, flags);
2123 // during some PM-driven resume scenarios,
2124 // these (async) unlinks complete immediately
2125 retval = usb_unlink_urb (urb);
2126 @@ -592,6 +593,7 @@ static int unlink_urbs (struct usbnet *dev, struct sk_buff_head *q)
2127 netdev_dbg(dev->net, "unlink urb err, %d\n", retval);
2128 else
2129 count++;
2130 + spin_lock_irqsave(&q->lock, flags);
2131 }
2132 spin_unlock_irqrestore (&q->lock, flags);
2133 return count;
2134 diff --git a/drivers/net/usb/zaurus.c b/drivers/net/usb/zaurus.c
2135 index 1a2234c..246b3bb 100644
2136 --- a/drivers/net/usb/zaurus.c
2137 +++ b/drivers/net/usb/zaurus.c
2138 @@ -349,6 +349,13 @@ static const struct usb_device_id products [] = {
2139 ZAURUS_MASTER_INTERFACE,
2140 .driver_info = OLYMPUS_MXL_INFO,
2141 },
2142 +
2143 +/* Logitech Harmony 900 - uses the pseudo-MDLM (BLAN) driver */
2144 +{
2145 + USB_DEVICE_AND_INTERFACE_INFO(0x046d, 0xc11f, USB_CLASS_COMM,
2146 + USB_CDC_SUBCLASS_MDLM, USB_CDC_PROTO_NONE),
2147 + .driver_info = (unsigned long) &bogus_mdlm_info,
2148 +},
2149 { }, // END
2150 };
2151 MODULE_DEVICE_TABLE(usb, products);
2152 diff --git a/drivers/net/wireless/ath/ath9k/ar5008_phy.c b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
2153 index 441bb33..0f23b1a 100644
2154 --- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c
2155 +++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
2156 @@ -489,8 +489,6 @@ static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
2157 ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
2158 ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
2159 ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
2160 - ATH_ALLOC_BANK(ah->addac5416_21,
2161 - ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
2162 ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
2163
2164 return 0;
2165 @@ -519,7 +517,6 @@ static void ar5008_hw_rf_free_ext_banks(struct ath_hw *ah)
2166 ATH_FREE_BANK(ah->analogBank6Data);
2167 ATH_FREE_BANK(ah->analogBank6TPCData);
2168 ATH_FREE_BANK(ah->analogBank7Data);
2169 - ATH_FREE_BANK(ah->addac5416_21);
2170 ATH_FREE_BANK(ah->bank6Temp);
2171
2172 #undef ATH_FREE_BANK
2173 @@ -799,27 +796,7 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
2174 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
2175 ah->eep_ops->set_addac(ah, chan);
2176
2177 - if (AR_SREV_5416_22_OR_LATER(ah)) {
2178 - REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
2179 - } else {
2180 - struct ar5416IniArray temp;
2181 - u32 addacSize =
2182 - sizeof(u32) * ah->iniAddac.ia_rows *
2183 - ah->iniAddac.ia_columns;
2184 -
2185 - /* For AR5416 2.0/2.1 */
2186 - memcpy(ah->addac5416_21,
2187 - ah->iniAddac.ia_array, addacSize);
2188 -
2189 - /* override CLKDRV value at [row, column] = [31, 1] */
2190 - (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
2191 -
2192 - temp.ia_array = ah->addac5416_21;
2193 - temp.ia_columns = ah->iniAddac.ia_columns;
2194 - temp.ia_rows = ah->iniAddac.ia_rows;
2195 - REG_WRITE_ARRAY(&temp, 1, regWrites);
2196 - }
2197 -
2198 + REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
2199 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
2200
2201 ENABLE_REGWRITE_BUFFER(ah);
2202 diff --git a/drivers/net/wireless/ath/ath9k/ar9002_hw.c b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
2203 index c32f9d1..30bf703 100644
2204 --- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
2205 +++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
2206 @@ -179,6 +179,25 @@ static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
2207 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
2208 ARRAY_SIZE(ar5416Addac), 2);
2209 }
2210 +
2211 + /* iniAddac needs to be modified for these chips */
2212 + if (AR_SREV_9160(ah) || !AR_SREV_5416_22_OR_LATER(ah)) {
2213 + struct ar5416IniArray *addac = &ah->iniAddac;
2214 + u32 size = sizeof(u32) * addac->ia_rows * addac->ia_columns;
2215 + u32 *data;
2216 +
2217 + data = kmalloc(size, GFP_KERNEL);
2218 + if (!data)
2219 + return;
2220 +
2221 + memcpy(data, addac->ia_array, size);
2222 + addac->ia_array = data;
2223 +
2224 + if (!AR_SREV_5416_22_OR_LATER(ah)) {
2225 + /* override CLKDRV value */
2226 + INI_RA(addac, 31,1) = 0;
2227 + }
2228 + }
2229 }
2230
2231 /* Support for Japan ch.14 (2484) spread */
2232 diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
2233 index 939cc9d..9dc2666 100644
2234 --- a/drivers/net/wireless/ath/ath9k/hw.h
2235 +++ b/drivers/net/wireless/ath/ath9k/hw.h
2236 @@ -763,7 +763,6 @@ struct ath_hw {
2237 u32 *analogBank6Data;
2238 u32 *analogBank6TPCData;
2239 u32 *analogBank7Data;
2240 - u32 *addac5416_21;
2241 u32 *bank6Temp;
2242
2243 u8 txpower_limit;
2244 diff --git a/drivers/net/wireless/ath/carl9170/tx.c b/drivers/net/wireless/ath/carl9170/tx.c
2245 index e94084f..f190f32 100644
2246 --- a/drivers/net/wireless/ath/carl9170/tx.c
2247 +++ b/drivers/net/wireless/ath/carl9170/tx.c
2248 @@ -1245,6 +1245,7 @@ static bool carl9170_tx_ps_drop(struct ar9170 *ar, struct sk_buff *skb)
2249 atomic_dec(&ar->tx_ampdu_upload);
2250
2251 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2252 + carl9170_release_dev_space(ar, skb);
2253 carl9170_tx_status(ar, skb, false);
2254 return true;
2255 }
2256 diff --git a/drivers/regulator/88pm8607.c b/drivers/regulator/88pm8607.c
2257 index d63fddb..acda58e 100644
2258 --- a/drivers/regulator/88pm8607.c
2259 +++ b/drivers/regulator/88pm8607.c
2260 @@ -195,7 +195,7 @@ static const unsigned int LDO12_suspend_table[] = {
2261 };
2262
2263 static const unsigned int LDO13_table[] = {
2264 - 1300000, 1800000, 2000000, 2500000, 2800000, 3000000, 0, 0,
2265 + 1200000, 1300000, 1800000, 2000000, 2500000, 2800000, 3000000, 0,
2266 };
2267
2268 static const unsigned int LDO13_suspend_table[] = {
2269 @@ -388,10 +388,10 @@ static struct pm8607_regulator_info pm8607_regulator_info[] = {
2270 PM8607_LDO( 7, LDO7, 0, 3, SUPPLIES_EN12, 1),
2271 PM8607_LDO( 8, LDO8, 0, 3, SUPPLIES_EN12, 2),
2272 PM8607_LDO( 9, LDO9, 0, 3, SUPPLIES_EN12, 3),
2273 - PM8607_LDO(10, LDO10, 0, 3, SUPPLIES_EN12, 4),
2274 + PM8607_LDO(10, LDO10, 0, 4, SUPPLIES_EN12, 4),
2275 PM8607_LDO(12, LDO12, 0, 4, SUPPLIES_EN12, 5),
2276 PM8607_LDO(13, VIBRATOR_SET, 1, 3, VIBRATOR_SET, 0),
2277 - PM8607_LDO(14, LDO14, 0, 4, SUPPLIES_EN12, 6),
2278 + PM8607_LDO(14, LDO14, 0, 3, SUPPLIES_EN12, 6),
2279 };
2280
2281 static int __devinit pm8607_regulator_probe(struct platform_device *pdev)
2282 diff --git a/drivers/s390/block/dasd_eckd.c b/drivers/s390/block/dasd_eckd.c
2283 index 30fb979..cc2dd7f 100644
2284 --- a/drivers/s390/block/dasd_eckd.c
2285 +++ b/drivers/s390/block/dasd_eckd.c
2286 @@ -18,12 +18,12 @@
2287 #include <linux/hdreg.h> /* HDIO_GETGEO */
2288 #include <linux/bio.h>
2289 #include <linux/module.h>
2290 +#include <linux/compat.h>
2291 #include <linux/init.h>
2292
2293 #include <asm/debug.h>
2294 #include <asm/idals.h>
2295 #include <asm/ebcdic.h>
2296 -#include <asm/compat.h>
2297 #include <asm/io.h>
2298 #include <asm/uaccess.h>
2299 #include <asm/cio.h>
2300 diff --git a/drivers/s390/block/dasd_ioctl.c b/drivers/s390/block/dasd_ioctl.c
2301 index 72261e4..9caeaea5 100644
2302 --- a/drivers/s390/block/dasd_ioctl.c
2303 +++ b/drivers/s390/block/dasd_ioctl.c
2304 @@ -13,6 +13,7 @@
2305 #define KMSG_COMPONENT "dasd"
2306
2307 #include <linux/interrupt.h>
2308 +#include <linux/compat.h>
2309 #include <linux/major.h>
2310 #include <linux/fs.h>
2311 #include <linux/blkpg.h>
2312 diff --git a/drivers/s390/char/fs3270.c b/drivers/s390/char/fs3270.c
2313 index f6489eb..e197fd7 100644
2314 --- a/drivers/s390/char/fs3270.c
2315 +++ b/drivers/s390/char/fs3270.c
2316 @@ -14,8 +14,8 @@
2317 #include <linux/list.h>
2318 #include <linux/slab.h>
2319 #include <linux/types.h>
2320 +#include <linux/compat.h>
2321
2322 -#include <asm/compat.h>
2323 #include <asm/ccwdev.h>
2324 #include <asm/cio.h>
2325 #include <asm/ebcdic.h>
2326 diff --git a/drivers/s390/char/vmcp.c b/drivers/s390/char/vmcp.c
2327 index 31a3ccb..84e569c 100644
2328 --- a/drivers/s390/char/vmcp.c
2329 +++ b/drivers/s390/char/vmcp.c
2330 @@ -13,6 +13,7 @@
2331
2332 #include <linux/fs.h>
2333 #include <linux/init.h>
2334 +#include <linux/compat.h>
2335 #include <linux/kernel.h>
2336 #include <linux/miscdevice.h>
2337 #include <linux/slab.h>
2338 diff --git a/drivers/s390/cio/chsc_sch.c b/drivers/s390/cio/chsc_sch.c
2339 index e950f1a..ec76029 100644
2340 --- a/drivers/s390/cio/chsc_sch.c
2341 +++ b/drivers/s390/cio/chsc_sch.c
2342 @@ -8,6 +8,7 @@
2343 */
2344
2345 #include <linux/slab.h>
2346 +#include <linux/compat.h>
2347 #include <linux/device.h>
2348 #include <linux/module.h>
2349 #include <linux/uaccess.h>
2350 diff --git a/drivers/s390/scsi/zfcp_cfdc.c b/drivers/s390/scsi/zfcp_cfdc.c
2351 index 303dde0..fab2c25 100644
2352 --- a/drivers/s390/scsi/zfcp_cfdc.c
2353 +++ b/drivers/s390/scsi/zfcp_cfdc.c
2354 @@ -11,6 +11,7 @@
2355 #define KMSG_COMPONENT "zfcp"
2356 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
2357
2358 +#include <linux/compat.h>
2359 #include <linux/slab.h>
2360 #include <linux/types.h>
2361 #include <linux/miscdevice.h>
2362 diff --git a/drivers/scsi/osd/osd_uld.c b/drivers/scsi/osd/osd_uld.c
2363 index b31a8e3..d4ed9eb 100644
2364 --- a/drivers/scsi/osd/osd_uld.c
2365 +++ b/drivers/scsi/osd/osd_uld.c
2366 @@ -69,10 +69,10 @@
2367 #ifndef SCSI_OSD_MAJOR
2368 # define SCSI_OSD_MAJOR 260
2369 #endif
2370 -#define SCSI_OSD_MAX_MINOR 64
2371 +#define SCSI_OSD_MAX_MINOR MINORMASK
2372
2373 static const char osd_name[] = "osd";
2374 -static const char *osd_version_string = "open-osd 0.2.0";
2375 +static const char *osd_version_string = "open-osd 0.2.1";
2376
2377 MODULE_AUTHOR("Boaz Harrosh <bharrosh@panasas.com>");
2378 MODULE_DESCRIPTION("open-osd Upper-Layer-Driver osd.ko");
2379 diff --git a/drivers/staging/lirc/lirc_serial.c b/drivers/staging/lirc/lirc_serial.c
2380 index 805df91..21cbc9a 100644
2381 --- a/drivers/staging/lirc/lirc_serial.c
2382 +++ b/drivers/staging/lirc/lirc_serial.c
2383 @@ -836,25 +836,22 @@ static int hardware_init_port(void)
2384 return 0;
2385 }
2386
2387 -static int init_port(void)
2388 +static int __devinit lirc_serial_probe(struct platform_device *dev)
2389 {
2390 int i, nlow, nhigh, result;
2391
2392 result = request_irq(irq, irq_handler,
2393 IRQF_DISABLED | (share_irq ? IRQF_SHARED : 0),
2394 LIRC_DRIVER_NAME, (void *)&hardware);
2395 -
2396 - switch (result) {
2397 - case -EBUSY:
2398 - printk(KERN_ERR LIRC_DRIVER_NAME ": IRQ %d busy\n", irq);
2399 - return -EBUSY;
2400 - case -EINVAL:
2401 - printk(KERN_ERR LIRC_DRIVER_NAME
2402 - ": Bad irq number or handler\n");
2403 - return -EINVAL;
2404 - default:
2405 - break;
2406 - };
2407 + if (result < 0) {
2408 + if (result == -EBUSY)
2409 + printk(KERN_ERR LIRC_DRIVER_NAME ": IRQ %d busy\n",
2410 + irq);
2411 + else if (result == -EINVAL)
2412 + printk(KERN_ERR LIRC_DRIVER_NAME
2413 + ": Bad irq number or handler\n");
2414 + return result;
2415 + }
2416
2417 /* Reserve io region. */
2418 /*
2419 @@ -875,11 +872,14 @@ static int init_port(void)
2420 ": or compile the serial port driver as module and\n");
2421 printk(KERN_WARNING LIRC_DRIVER_NAME
2422 ": make sure this module is loaded first\n");
2423 - return -EBUSY;
2424 + result = -EBUSY;
2425 + goto exit_free_irq;
2426 }
2427
2428 - if (hardware_init_port() < 0)
2429 - return -EINVAL;
2430 + if (hardware_init_port() < 0) {
2431 + result = -EINVAL;
2432 + goto exit_release_region;
2433 + }
2434
2435 /* Initialize pulse/space widths */
2436 init_timing_params(duty_cycle, freq);
2437 @@ -911,6 +911,28 @@ static int init_port(void)
2438
2439 dprintk("Interrupt %d, port %04x obtained\n", irq, io);
2440 return 0;
2441 +
2442 +exit_release_region:
2443 + if (iommap != 0)
2444 + release_mem_region(iommap, 8 << ioshift);
2445 + else
2446 + release_region(io, 8);
2447 +exit_free_irq:
2448 + free_irq(irq, (void *)&hardware);
2449 +
2450 + return result;
2451 +}
2452 +
2453 +static int __devexit lirc_serial_remove(struct platform_device *dev)
2454 +{
2455 + free_irq(irq, (void *)&hardware);
2456 +
2457 + if (iommap != 0)
2458 + release_mem_region(iommap, 8 << ioshift);
2459 + else
2460 + release_region(io, 8);
2461 +
2462 + return 0;
2463 }
2464
2465 static int set_use_inc(void *data)
2466 @@ -1076,16 +1098,6 @@ static struct lirc_driver driver = {
2467
2468 static struct platform_device *lirc_serial_dev;
2469
2470 -static int __devinit lirc_serial_probe(struct platform_device *dev)
2471 -{
2472 - return 0;
2473 -}
2474 -
2475 -static int __devexit lirc_serial_remove(struct platform_device *dev)
2476 -{
2477 - return 0;
2478 -}
2479 -
2480 static int lirc_serial_suspend(struct platform_device *dev,
2481 pm_message_t state)
2482 {
2483 @@ -1112,10 +1124,8 @@ static int lirc_serial_resume(struct platform_device *dev)
2484 {
2485 unsigned long flags;
2486
2487 - if (hardware_init_port() < 0) {
2488 - lirc_serial_exit();
2489 + if (hardware_init_port() < 0)
2490 return -EINVAL;
2491 - }
2492
2493 spin_lock_irqsave(&hardware[type].lock, flags);
2494 /* Enable Interrupt */
2495 @@ -1188,10 +1198,6 @@ static int __init lirc_serial_init_module(void)
2496 {
2497 int result;
2498
2499 - result = lirc_serial_init();
2500 - if (result)
2501 - return result;
2502 -
2503 switch (type) {
2504 case LIRC_HOMEBREW:
2505 case LIRC_IRDEO:
2506 @@ -1211,8 +1217,7 @@ static int __init lirc_serial_init_module(void)
2507 break;
2508 #endif
2509 default:
2510 - result = -EINVAL;
2511 - goto exit_serial_exit;
2512 + return -EINVAL;
2513 }
2514 if (!softcarrier) {
2515 switch (type) {
2516 @@ -1228,37 +1233,26 @@ static int __init lirc_serial_init_module(void)
2517 }
2518 }
2519
2520 - result = init_port();
2521 - if (result < 0)
2522 - goto exit_serial_exit;
2523 + result = lirc_serial_init();
2524 + if (result)
2525 + return result;
2526 +
2527 driver.features = hardware[type].features;
2528 driver.dev = &lirc_serial_dev->dev;
2529 driver.minor = lirc_register_driver(&driver);
2530 if (driver.minor < 0) {
2531 printk(KERN_ERR LIRC_DRIVER_NAME
2532 ": register_chrdev failed!\n");
2533 - result = -EIO;
2534 - goto exit_release;
2535 + lirc_serial_exit();
2536 + return -EIO;
2537 }
2538 return 0;
2539 -exit_release:
2540 - release_region(io, 8);
2541 -exit_serial_exit:
2542 - lirc_serial_exit();
2543 - return result;
2544 }
2545
2546 static void __exit lirc_serial_exit_module(void)
2547 {
2548 - lirc_serial_exit();
2549 -
2550 - free_irq(irq, (void *)&hardware);
2551 -
2552 - if (iommap != 0)
2553 - release_mem_region(iommap, 8 << ioshift);
2554 - else
2555 - release_region(io, 8);
2556 lirc_unregister_driver(driver.minor);
2557 + lirc_serial_exit();
2558 dprintk("cleaned up module\n");
2559 }
2560
2561 diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c
2562 index b0555f4..fadd6a0 100644
2563 --- a/drivers/video/omap2/dss/hdmi.c
2564 +++ b/drivers/video/omap2/dss/hdmi.c
2565 @@ -29,6 +29,7 @@
2566 #include <linux/mutex.h>
2567 #include <linux/delay.h>
2568 #include <linux/string.h>
2569 +#include <linux/gpio.h>
2570 #include <video/omapdss.h>
2571 #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
2572 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
2573 @@ -40,6 +41,9 @@
2574 #include "hdmi.h"
2575 #include "dss_features.h"
2576
2577 +#define HDMI_DEFAULT_REGN 15
2578 +#define HDMI_DEFAULT_REGM2 1
2579 +
2580 static struct {
2581 struct mutex lock;
2582 struct omap_display_platform_data *pdata;
2583 @@ -51,6 +55,9 @@ static struct {
2584 u8 edid_set;
2585 bool custom_set;
2586 struct hdmi_config cfg;
2587 +
2588 + int hpd_gpio;
2589 + bool phy_tx_enabled;
2590 } hdmi;
2591
2592 /*
2593 @@ -275,6 +282,47 @@ static int hdmi_pll_reset(void)
2594 return 0;
2595 }
2596
2597 +static int hdmi_check_hpd_state(void)
2598 +{
2599 + unsigned long flags;
2600 + bool hpd;
2601 + int r;
2602 + /* this should be in ti_hdmi_4xxx_ip private data */
2603 + static DEFINE_SPINLOCK(phy_tx_lock);
2604 +
2605 + spin_lock_irqsave(&phy_tx_lock, flags);
2606 +
2607 + hpd = gpio_get_value(hdmi.hpd_gpio);
2608 +
2609 + if (hpd == hdmi.phy_tx_enabled) {
2610 + spin_unlock_irqrestore(&phy_tx_lock, flags);
2611 + return 0;
2612 + }
2613 +
2614 + if (hpd)
2615 + r = hdmi_set_phy_pwr(HDMI_PHYPWRCMD_TXON);
2616 + else
2617 + r = hdmi_set_phy_pwr(HDMI_PHYPWRCMD_LDOON);
2618 +
2619 + if (r) {
2620 + DSSERR("Failed to %s PHY TX power\n",
2621 + hpd ? "enable" : "disable");
2622 + goto err;
2623 + }
2624 +
2625 + hdmi.phy_tx_enabled = hpd;
2626 +err:
2627 + spin_unlock_irqrestore(&phy_tx_lock, flags);
2628 + return r;
2629 +}
2630 +
2631 +static irqreturn_t hpd_irq_handler(int irq, void *data)
2632 +{
2633 + hdmi_check_hpd_state();
2634 +
2635 + return IRQ_HANDLED;
2636 +}
2637 +
2638 static int hdmi_phy_init(void)
2639 {
2640 u16 r = 0;
2641 @@ -283,10 +331,6 @@ static int hdmi_phy_init(void)
2642 if (r)
2643 return r;
2644
2645 - r = hdmi_set_phy_pwr(HDMI_PHYPWRCMD_TXON);
2646 - if (r)
2647 - return r;
2648 -
2649 /*
2650 * Read address 0 in order to get the SCP reset done completed
2651 * Dummy access performed to make sure reset is done
2652 @@ -308,6 +352,23 @@ static int hdmi_phy_init(void)
2653 /* Write to phy address 3 to change the polarity control */
2654 REG_FLD_MOD(HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27);
2655
2656 + r = request_threaded_irq(gpio_to_irq(hdmi.hpd_gpio),
2657 + NULL, hpd_irq_handler,
2658 + IRQF_DISABLED | IRQF_TRIGGER_RISING |
2659 + IRQF_TRIGGER_FALLING, "hpd", NULL);
2660 + if (r) {
2661 + DSSERR("HPD IRQ request failed\n");
2662 + hdmi_set_phy_pwr(HDMI_PHYPWRCMD_OFF);
2663 + return r;
2664 + }
2665 +
2666 + r = hdmi_check_hpd_state();
2667 + if (r) {
2668 + free_irq(gpio_to_irq(hdmi.hpd_gpio), NULL);
2669 + hdmi_set_phy_pwr(HDMI_PHYPWRCMD_OFF);
2670 + return r;
2671 + }
2672 +
2673 return 0;
2674 }
2675
2676 @@ -358,7 +419,9 @@ static int hdmi_pll_program(struct hdmi_pll_info *fmt)
2677
2678 static void hdmi_phy_off(void)
2679 {
2680 + free_irq(gpio_to_irq(hdmi.hpd_gpio), NULL);
2681 hdmi_set_phy_pwr(HDMI_PHYPWRCMD_OFF);
2682 + hdmi.phy_tx_enabled = false;
2683 }
2684
2685 static int hdmi_core_ddc_edid(u8 *pedid, int ext)
2686 @@ -1069,7 +1132,11 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
2687 * Input clock is predivided by N + 1
2688 * out put of which is reference clk
2689 */
2690 - pi->regn = dssdev->clocks.hdmi.regn;
2691 + if (dssdev->clocks.hdmi.regn == 0)
2692 + pi->regn = HDMI_DEFAULT_REGN;
2693 + else
2694 + pi->regn = dssdev->clocks.hdmi.regn;
2695 +
2696 refclk = clkin / (pi->regn + 1);
2697
2698 /*
2699 @@ -1077,7 +1144,11 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
2700 * Multiplying by 100 to avoid fractional part removal
2701 */
2702 pi->regm = (phy * 100 / (refclk)) / 100;
2703 - pi->regm2 = dssdev->clocks.hdmi.regm2;
2704 +
2705 + if (dssdev->clocks.hdmi.regm2 == 0)
2706 + pi->regm2 = HDMI_DEFAULT_REGM2;
2707 + else
2708 + pi->regm2 = dssdev->clocks.hdmi.regm2;
2709
2710 /*
2711 * fractional multiplier is remainder of the difference between
2712 @@ -1225,12 +1296,15 @@ void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev)
2713
2714 int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev)
2715 {
2716 + struct omap_dss_hdmi_data *priv = dssdev->data;
2717 int r = 0;
2718
2719 DSSDBG("ENTER hdmi_display_enable\n");
2720
2721 mutex_lock(&hdmi.lock);
2722
2723 + hdmi.hpd_gpio = priv->hpd_gpio;
2724 +
2725 r = omap_dss_start_device(dssdev);
2726 if (r) {
2727 DSSERR("failed to start device\n");
2728 diff --git a/drivers/watchdog/hpwdt.c b/drivers/watchdog/hpwdt.c
2729 index 9cb60df..d4ab797 100644
2730 --- a/drivers/watchdog/hpwdt.c
2731 +++ b/drivers/watchdog/hpwdt.c
2732 @@ -216,7 +216,7 @@ static int __devinit cru_detect(unsigned long map_entry,
2733
2734 cmn_regs.u1.reax = CRU_BIOS_SIGNATURE_VALUE;
2735
2736 - set_memory_x((unsigned long)bios32_entrypoint, (2 * PAGE_SIZE));
2737 + set_memory_x((unsigned long)bios32_map, 2);
2738 asminline_call(&cmn_regs, bios32_entrypoint);
2739
2740 if (cmn_regs.u1.ral != 0) {
2741 @@ -235,7 +235,8 @@ static int __devinit cru_detect(unsigned long map_entry,
2742 cru_rom_addr =
2743 ioremap(cru_physical_address, cru_length);
2744 if (cru_rom_addr) {
2745 - set_memory_x((unsigned long)cru_rom_addr, cru_length);
2746 + set_memory_x((unsigned long)cru_rom_addr & PAGE_MASK,
2747 + (cru_length + PAGE_SIZE - 1) >> PAGE_SHIFT);
2748 retval = 0;
2749 }
2750 }
2751 diff --git a/fs/autofs4/autofs_i.h b/fs/autofs4/autofs_i.h
2752 index 475f9c5..10cc45a 100644
2753 --- a/fs/autofs4/autofs_i.h
2754 +++ b/fs/autofs4/autofs_i.h
2755 @@ -120,6 +120,7 @@ struct autofs_sb_info {
2756 int sub_version;
2757 int min_proto;
2758 int max_proto;
2759 + int compat_daemon;
2760 unsigned long exp_timeout;
2761 unsigned int type;
2762 int reghost_enabled;
2763 diff --git a/fs/autofs4/dev-ioctl.c b/fs/autofs4/dev-ioctl.c
2764 index 509fe1e..56bac70 100644
2765 --- a/fs/autofs4/dev-ioctl.c
2766 +++ b/fs/autofs4/dev-ioctl.c
2767 @@ -385,6 +385,7 @@ static int autofs_dev_ioctl_setpipefd(struct file *fp,
2768 sbi->pipefd = pipefd;
2769 sbi->pipe = pipe;
2770 sbi->catatonic = 0;
2771 + sbi->compat_daemon = is_compat_task();
2772 }
2773 out:
2774 mutex_unlock(&sbi->wq_mutex);
2775 diff --git a/fs/autofs4/inode.c b/fs/autofs4/inode.c
2776 index 180fa24..eb1e45c 100644
2777 --- a/fs/autofs4/inode.c
2778 +++ b/fs/autofs4/inode.c
2779 @@ -19,6 +19,7 @@
2780 #include <linux/parser.h>
2781 #include <linux/bitops.h>
2782 #include <linux/magic.h>
2783 +#include <linux/compat.h>
2784 #include "autofs_i.h"
2785 #include <linux/module.h>
2786
2787 @@ -224,6 +225,7 @@ int autofs4_fill_super(struct super_block *s, void *data, int silent)
2788 set_autofs_type_indirect(&sbi->type);
2789 sbi->min_proto = 0;
2790 sbi->max_proto = 0;
2791 + sbi->compat_daemon = is_compat_task();
2792 mutex_init(&sbi->wq_mutex);
2793 spin_lock_init(&sbi->fs_lock);
2794 sbi->queues = NULL;
2795 diff --git a/fs/autofs4/waitq.c b/fs/autofs4/waitq.c
2796 index 2543598..fbbb749 100644
2797 --- a/fs/autofs4/waitq.c
2798 +++ b/fs/autofs4/waitq.c
2799 @@ -90,7 +90,24 @@ static int autofs4_write(struct file *file, const void *addr, int bytes)
2800
2801 return (bytes > 0);
2802 }
2803 -
2804 +
2805 +/*
2806 + * The autofs_v5 packet was misdesigned.
2807 + *
2808 + * The packets are identical on x86-32 and x86-64, but have different
2809 + * alignment. Which means that 'sizeof()' will give different results.
2810 + * Fix it up for the case of running 32-bit user mode on a 64-bit kernel.
2811 + */
2812 +static noinline size_t autofs_v5_packet_size(struct autofs_sb_info *sbi)
2813 +{
2814 + size_t pktsz = sizeof(struct autofs_v5_packet);
2815 +#if defined(CONFIG_X86_64) && defined(CONFIG_COMPAT)
2816 + if (sbi->compat_daemon > 0)
2817 + pktsz -= 4;
2818 +#endif
2819 + return pktsz;
2820 +}
2821 +
2822 static void autofs4_notify_daemon(struct autofs_sb_info *sbi,
2823 struct autofs_wait_queue *wq,
2824 int type)
2825 @@ -147,8 +164,7 @@ static void autofs4_notify_daemon(struct autofs_sb_info *sbi,
2826 {
2827 struct autofs_v5_packet *packet = &pkt.v5_pkt.v5_packet;
2828
2829 - pktsz = sizeof(*packet);
2830 -
2831 + pktsz = autofs_v5_packet_size(sbi);
2832 packet->wait_queue_token = wq->wait_queue_token;
2833 packet->len = wq->name.len;
2834 memcpy(packet->name, wq->name.name, wq->name.len);
2835 diff --git a/fs/binfmt_elf.c b/fs/binfmt_elf.c
2836 index 9ba2ac7..618493e 100644
2837 --- a/fs/binfmt_elf.c
2838 +++ b/fs/binfmt_elf.c
2839 @@ -1422,7 +1422,7 @@ static int fill_thread_core_info(struct elf_thread_core_info *t,
2840 for (i = 1; i < view->n; ++i) {
2841 const struct user_regset *regset = &view->regsets[i];
2842 do_thread_regset_writeback(t->task, regset);
2843 - if (regset->core_note_type &&
2844 + if (regset->core_note_type && regset->get &&
2845 (!regset->active || regset->active(t->task, regset))) {
2846 int ret;
2847 size_t size = regset->n * regset->size;
2848 diff --git a/fs/cifs/dir.c b/fs/cifs/dir.c
2849 index 16cdd6d..ed5c07b 100644
2850 --- a/fs/cifs/dir.c
2851 +++ b/fs/cifs/dir.c
2852 @@ -583,10 +583,26 @@ cifs_lookup(struct inode *parent_dir_inode, struct dentry *direntry,
2853 * If either that or op not supported returned, follow
2854 * the normal lookup.
2855 */
2856 - if ((rc == 0) || (rc == -ENOENT))
2857 + switch (rc) {
2858 + case 0:
2859 + /*
2860 + * The server may allow us to open things like
2861 + * FIFOs, but the client isn't set up to deal
2862 + * with that. If it's not a regular file, just
2863 + * close it and proceed as if it were a normal
2864 + * lookup.
2865 + */
2866 + if (newInode && !S_ISREG(newInode->i_mode)) {
2867 + CIFSSMBClose(xid, pTcon, fileHandle);
2868 + break;
2869 + }
2870 + case -ENOENT:
2871 posix_open = true;
2872 - else if ((rc == -EINVAL) || (rc != -EOPNOTSUPP))
2873 + case -EOPNOTSUPP:
2874 + break;
2875 + default:
2876 pTcon->broken_posix_open = true;
2877 + }
2878 }
2879 if (!posix_open)
2880 rc = cifs_get_inode_info_unix(&newInode, full_path,
2881 diff --git a/include/linux/compat.h b/include/linux/compat.h
2882 index 846bb17..edaf390 100644
2883 --- a/include/linux/compat.h
2884 +++ b/include/linux/compat.h
2885 @@ -561,5 +561,9 @@ extern ssize_t compat_rw_copy_check_uvector(int type,
2886
2887 extern void __user *compat_alloc_user_space(unsigned long len);
2888
2889 +#else
2890 +
2891 +#define is_compat_task() (0)
2892 +
2893 #endif /* CONFIG_COMPAT */
2894 #endif /* _LINUX_COMPAT_H */
2895 diff --git a/include/linux/regset.h b/include/linux/regset.h
2896 index 8abee65..686f373 100644
2897 --- a/include/linux/regset.h
2898 +++ b/include/linux/regset.h
2899 @@ -335,8 +335,11 @@ static inline int copy_regset_to_user(struct task_struct *target,
2900 {
2901 const struct user_regset *regset = &view->regsets[setno];
2902
2903 + if (!regset->get)
2904 + return -EOPNOTSUPP;
2905 +
2906 if (!access_ok(VERIFY_WRITE, data, size))
2907 - return -EIO;
2908 + return -EFAULT;
2909
2910 return regset->get(target, regset, offset, size, NULL, data);
2911 }
2912 @@ -358,8 +361,11 @@ static inline int copy_regset_from_user(struct task_struct *target,
2913 {
2914 const struct user_regset *regset = &view->regsets[setno];
2915
2916 + if (!regset->set)
2917 + return -EOPNOTSUPP;
2918 +
2919 if (!access_ok(VERIFY_READ, data, size))
2920 - return -EIO;
2921 + return -EFAULT;
2922
2923 return regset->set(target, regset, offset, size, NULL, data);
2924 }
2925 diff --git a/include/video/omapdss.h b/include/video/omapdss.h
2926 index 892b97f..c0d8014 100644
2927 --- a/include/video/omapdss.h
2928 +++ b/include/video/omapdss.h
2929 @@ -514,6 +514,11 @@ struct omap_dss_device {
2930 int (*get_backlight)(struct omap_dss_device *dssdev);
2931 };
2932
2933 +struct omap_dss_hdmi_data
2934 +{
2935 + int hpd_gpio;
2936 +};
2937 +
2938 struct omap_dss_driver {
2939 struct device_driver driver;
2940
2941 diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c
2942 index def3406..e4eedb1 100644
2943 --- a/kernel/irq/manage.c
2944 +++ b/kernel/irq/manage.c
2945 @@ -976,6 +976,11 @@ __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new)
2946
2947 /* add new interrupt at end of irq queue */
2948 do {
2949 + /*
2950 + * Or all existing action->thread_mask bits,
2951 + * so we can find the next zero bit for this
2952 + * new action.
2953 + */
2954 thread_mask |= old->thread_mask;
2955 old_ptr = &old->next;
2956 old = *old_ptr;
2957 @@ -984,14 +989,41 @@ __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new)
2958 }
2959
2960 /*
2961 - * Setup the thread mask for this irqaction. Unlikely to have
2962 - * 32 resp 64 irqs sharing one line, but who knows.
2963 + * Setup the thread mask for this irqaction for ONESHOT. For
2964 + * !ONESHOT irqs the thread mask is 0 so we can avoid a
2965 + * conditional in irq_wake_thread().
2966 */
2967 - if (new->flags & IRQF_ONESHOT && thread_mask == ~0UL) {
2968 - ret = -EBUSY;
2969 - goto out_mask;
2970 + if (new->flags & IRQF_ONESHOT) {
2971 + /*
2972 + * Unlikely to have 32 resp 64 irqs sharing one line,
2973 + * but who knows.
2974 + */
2975 + if (thread_mask == ~0UL) {
2976 + ret = -EBUSY;
2977 + goto out_mask;
2978 + }
2979 + /*
2980 + * The thread_mask for the action is or'ed to
2981 + * desc->thread_active to indicate that the
2982 + * IRQF_ONESHOT thread handler has been woken, but not
2983 + * yet finished. The bit is cleared when a thread
2984 + * completes. When all threads of a shared interrupt
2985 + * line have completed desc->threads_active becomes
2986 + * zero and the interrupt line is unmasked. See
2987 + * handle.c:irq_wake_thread() for further information.
2988 + *
2989 + * If no thread is woken by primary (hard irq context)
2990 + * interrupt handlers, then desc->threads_active is
2991 + * also checked for zero to unmask the irq line in the
2992 + * affected hard irq flow handlers
2993 + * (handle_[fasteoi|level]_irq).
2994 + *
2995 + * The new action gets the first zero bit of
2996 + * thread_mask assigned. See the loop above which or's
2997 + * all existing action->thread_mask bits.
2998 + */
2999 + new->thread_mask = 1 << ffz(thread_mask);
3000 }
3001 - new->thread_mask = 1 << ffz(thread_mask);
3002
3003 if (!shared) {
3004 init_waitqueue_head(&desc->wait_for_threads);
3005 diff --git a/kernel/kprobes.c b/kernel/kprobes.c
3006 index 749340c..f1dcde4 100644
3007 --- a/kernel/kprobes.c
3008 +++ b/kernel/kprobes.c
3009 @@ -1661,9 +1661,9 @@ static int __kprobes pre_handler_kretprobe(struct kprobe *p,
3010 ri->task = current;
3011
3012 if (rp->entry_handler && rp->entry_handler(ri, regs)) {
3013 - raw_spin_lock_irqsave(&rp->lock, flags);
3014 + spin_lock_irqsave(&rp->lock, flags);
3015 hlist_add_head(&ri->hlist, &rp->free_instances);
3016 - raw_spin_unlock_irqrestore(&rp->lock, flags);
3017 + spin_unlock_irqrestore(&rp->lock, flags);
3018 return 0;
3019 }
3020
3021 diff --git a/mm/huge_memory.c b/mm/huge_memory.c
3022 index 78a83e7..8cc11dd 100644
3023 --- a/mm/huge_memory.c
3024 +++ b/mm/huge_memory.c
3025 @@ -641,6 +641,7 @@ static int __do_huge_pmd_anonymous_page(struct mm_struct *mm,
3026 set_pmd_at(mm, haddr, pmd, entry);
3027 prepare_pmd_huge_pte(pgtable, mm);
3028 add_mm_counter(mm, MM_ANONPAGES, HPAGE_PMD_NR);
3029 + mm->nr_ptes++;
3030 spin_unlock(&mm->page_table_lock);
3031 }
3032
3033 @@ -759,6 +760,7 @@ int copy_huge_pmd(struct mm_struct *dst_mm, struct mm_struct *src_mm,
3034 pmd = pmd_mkold(pmd_wrprotect(pmd));
3035 set_pmd_at(dst_mm, addr, dst_pmd, pmd);
3036 prepare_pmd_huge_pte(pgtable, dst_mm);
3037 + dst_mm->nr_ptes++;
3038
3039 ret = 0;
3040 out_unlock:
3041 @@ -857,7 +859,6 @@ static int do_huge_pmd_wp_page_fallback(struct mm_struct *mm,
3042 }
3043 kfree(pages);
3044
3045 - mm->nr_ptes++;
3046 smp_wmb(); /* make pte visible before pmd */
3047 pmd_populate(mm, pmd, pgtable);
3048 page_remove_rmap(page);
3049 @@ -1016,6 +1017,7 @@ int zap_huge_pmd(struct mmu_gather *tlb, struct vm_area_struct *vma,
3050 VM_BUG_ON(page_mapcount(page) < 0);
3051 add_mm_counter(tlb->mm, MM_ANONPAGES, -HPAGE_PMD_NR);
3052 VM_BUG_ON(!PageHead(page));
3053 + tlb->mm->nr_ptes--;
3054 spin_unlock(&tlb->mm->page_table_lock);
3055 tlb_remove_page(tlb, page);
3056 pte_free(tlb->mm, pgtable);
3057 @@ -1310,7 +1312,6 @@ static int __split_huge_page_map(struct page *page,
3058 pte_unmap(pte);
3059 }
3060
3061 - mm->nr_ptes++;
3062 smp_wmb(); /* make pte visible before pmd */
3063 /*
3064 * Up to this point the pmd is present and huge and
3065 @@ -1925,7 +1926,6 @@ static void collapse_huge_page(struct mm_struct *mm,
3066 set_pmd_at(mm, address, pmd, _pmd);
3067 update_mmu_cache(vma, address, entry);
3068 prepare_pmd_huge_pte(pgtable, mm);
3069 - mm->nr_ptes--;
3070 spin_unlock(&mm->page_table_lock);
3071
3072 #ifndef CONFIG_NUMA
3073 diff --git a/mm/memcontrol.c b/mm/memcontrol.c
3074 index 3791581..45059db 100644
3075 --- a/mm/memcontrol.c
3076 +++ b/mm/memcontrol.c
3077 @@ -4558,6 +4558,9 @@ static void mem_cgroup_usage_unregister_event(struct cgroup *cgrp,
3078 */
3079 BUG_ON(!thresholds);
3080
3081 + if (!thresholds->primary)
3082 + goto unlock;
3083 +
3084 usage = mem_cgroup_usage(memcg, type == _MEMSWAP);
3085
3086 /* Check if a threshold crossed before removing */
3087 @@ -4606,7 +4609,7 @@ swap_buffers:
3088
3089 /* To be sure that nobody uses thresholds */
3090 synchronize_rcu();
3091 -
3092 +unlock:
3093 mutex_unlock(&memcg->thresholds_lock);
3094 }
3095
3096 diff --git a/mm/nommu.c b/mm/nommu.c
3097 index 8397758..5ff9b35 100644
3098 --- a/mm/nommu.c
3099 +++ b/mm/nommu.c
3100 @@ -780,8 +780,6 @@ static void delete_vma_from_mm(struct vm_area_struct *vma)
3101
3102 if (vma->vm_next)
3103 vma->vm_next->vm_prev = vma->vm_prev;
3104 -
3105 - vma->vm_mm = NULL;
3106 }
3107
3108 /*
3109 diff --git a/net/mac80211/rate.c b/net/mac80211/rate.c
3110 index 3d5a2cb..816590b 100644
3111 --- a/net/mac80211/rate.c
3112 +++ b/net/mac80211/rate.c
3113 @@ -314,7 +314,7 @@ void rate_control_get_rate(struct ieee80211_sub_if_data *sdata,
3114 for (i = 0; i < IEEE80211_TX_MAX_RATES; i++) {
3115 info->control.rates[i].idx = -1;
3116 info->control.rates[i].flags = 0;
3117 - info->control.rates[i].count = 1;
3118 + info->control.rates[i].count = 0;
3119 }
3120
3121 if (sdata->local->hw.flags & IEEE80211_HW_HAS_RATE_CONTROL)
3122 diff --git a/sound/pci/hda/hda_codec.c b/sound/pci/hda/hda_codec.c
3123 index 67d341f..39e1a6a 100644
3124 --- a/sound/pci/hda/hda_codec.c
3125 +++ b/sound/pci/hda/hda_codec.c
3126 @@ -1651,7 +1651,11 @@ static void put_vol_mute(struct hda_codec *codec, struct hda_amp_info *info,
3127 parm = ch ? AC_AMP_SET_RIGHT : AC_AMP_SET_LEFT;
3128 parm |= direction == HDA_OUTPUT ? AC_AMP_SET_OUTPUT : AC_AMP_SET_INPUT;
3129 parm |= index << AC_AMP_SET_INDEX_SHIFT;
3130 - parm |= val;
3131 + if ((val & HDA_AMP_MUTE) && !(info->amp_caps & AC_AMPCAP_MUTE) &&
3132 + (info->amp_caps & AC_AMPCAP_MIN_MUTE))
3133 + ; /* set the zero value as a fake mute */
3134 + else
3135 + parm |= val;
3136 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_AMP_GAIN_MUTE, parm);
3137 info->vol[ch] = val;
3138 }
3139 @@ -1918,7 +1922,7 @@ int snd_hda_mixer_amp_tlv(struct snd_kcontrol *kcontrol, int op_flag,
3140 val1 = -((caps & AC_AMPCAP_OFFSET) >> AC_AMPCAP_OFFSET_SHIFT);
3141 val1 += ofs;
3142 val1 = ((int)val1) * ((int)val2);
3143 - if (min_mute)
3144 + if (min_mute || (caps & AC_AMPCAP_MIN_MUTE))
3145 val2 |= TLV_DB_SCALE_MUTE;
3146 if (put_user(SNDRV_CTL_TLVT_DB_SCALE, _tlv))
3147 return -EFAULT;
3148 diff --git a/sound/pci/hda/hda_codec.h b/sound/pci/hda/hda_codec.h
3149 index 59c9730..eff1fc5 100644
3150 --- a/sound/pci/hda/hda_codec.h
3151 +++ b/sound/pci/hda/hda_codec.h
3152 @@ -302,6 +302,9 @@ enum {
3153 #define AC_AMPCAP_MUTE (1<<31) /* mute capable */
3154 #define AC_AMPCAP_MUTE_SHIFT 31
3155
3156 +/* driver-specific amp-caps: using bits 24-30 */
3157 +#define AC_AMPCAP_MIN_MUTE (1 << 30) /* min-volume = mute */
3158 +
3159 /* Connection list */
3160 #define AC_CLIST_LENGTH (0x7f<<0)
3161 #define AC_CLIST_LONG (1<<7)
3162 diff --git a/sound/pci/hda/patch_conexant.c b/sound/pci/hda/patch_conexant.c
3163 index 81ecd6c..4ad20a6 100644
3164 --- a/sound/pci/hda/patch_conexant.c
3165 +++ b/sound/pci/hda/patch_conexant.c
3166 @@ -4127,7 +4127,8 @@ static int cx_auto_add_volume_idx(struct hda_codec *codec, const char *basename,
3167 err = snd_hda_ctl_add(codec, nid, kctl);
3168 if (err < 0)
3169 return err;
3170 - if (!(query_amp_caps(codec, nid, hda_dir) & AC_AMPCAP_MUTE))
3171 + if (!(query_amp_caps(codec, nid, hda_dir) &
3172 + (AC_AMPCAP_MUTE | AC_AMPCAP_MIN_MUTE)))
3173 break;
3174 }
3175 return 0;
3176 @@ -4372,6 +4373,22 @@ static const struct hda_codec_ops cx_auto_patch_ops = {
3177 .reboot_notify = snd_hda_shutup_pins,
3178 };
3179
3180 +/* add "fake" mute amp-caps to DACs on cx5051 so that mixer mute switches
3181 + * can be created (bko#42825)
3182 + */
3183 +static void add_cx5051_fake_mutes(struct hda_codec *codec)
3184 +{
3185 + static hda_nid_t out_nids[] = {
3186 + 0x10, 0x11, 0
3187 + };
3188 + hda_nid_t *p;
3189 +
3190 + for (p = out_nids; *p; p++)
3191 + snd_hda_override_amp_caps(codec, *p, HDA_OUTPUT,
3192 + AC_AMPCAP_MIN_MUTE |
3193 + query_amp_caps(codec, *p, HDA_OUTPUT));
3194 +}
3195 +
3196 static int patch_conexant_auto(struct hda_codec *codec)
3197 {
3198 struct conexant_spec *spec;
3199 @@ -4390,6 +4407,9 @@ static int patch_conexant_auto(struct hda_codec *codec)
3200 case 0x14f15045:
3201 spec->single_adc_amp = 1;
3202 break;
3203 + case 0x14f15051:
3204 + add_cx5051_fake_mutes(codec);
3205 + break;
3206 }
3207
3208 err = cx_auto_search_adcs(codec);
3209 diff --git a/sound/pci/hda/patch_sigmatel.c b/sound/pci/hda/patch_sigmatel.c
3210 index 43d88c7..8670682 100644
3211 --- a/sound/pci/hda/patch_sigmatel.c
3212 +++ b/sound/pci/hda/patch_sigmatel.c
3213 @@ -4589,7 +4589,7 @@ static void stac92xx_hp_detect(struct hda_codec *codec)
3214 unsigned int val = AC_PINCTL_OUT_EN | AC_PINCTL_HP_EN;
3215 if (no_hp_sensing(spec, i))
3216 continue;
3217 - if (presence)
3218 + if (1 /*presence*/)
3219 stac92xx_set_pinctl(codec, cfg->hp_pins[i], val);
3220 #if 0 /* FIXME */
3221 /* Resetting the pinctl like below may lead to (a sort of) regressions
3222 diff --git a/sound/soc/imx/imx-ssi.c b/sound/soc/imx/imx-ssi.c
3223 index 61fceb0..3b56254 100644
3224 --- a/sound/soc/imx/imx-ssi.c
3225 +++ b/sound/soc/imx/imx-ssi.c
3226 @@ -112,7 +112,7 @@ static int imx_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
3227 break;
3228 case SND_SOC_DAIFMT_DSP_A:
3229 /* data on rising edge of bclk, frame high 1clk before data */
3230 - strcr |= SSI_STCR_TFSL | SSI_STCR_TEFS;
3231 + strcr |= SSI_STCR_TFSL | SSI_STCR_TXBIT0 | SSI_STCR_TEFS;
3232 break;
3233 }
3234
3235 diff --git a/sound/soc/soc-dapm.c b/sound/soc/soc-dapm.c
3236 index 32ab7fc..058c0a8 100644
3237 --- a/sound/soc/soc-dapm.c
3238 +++ b/sound/soc/soc-dapm.c
3239 @@ -2615,9 +2615,13 @@ static void soc_dapm_shutdown_codec(struct snd_soc_dapm_context *dapm)
3240 * standby.
3241 */
3242 if (powerdown) {
3243 - snd_soc_dapm_set_bias_level(dapm, SND_SOC_BIAS_PREPARE);
3244 + if (dapm->bias_level == SND_SOC_BIAS_ON)
3245 + snd_soc_dapm_set_bias_level(dapm,
3246 + SND_SOC_BIAS_PREPARE);
3247 dapm_seq_run(dapm, &down_list, 0, false);
3248 - snd_soc_dapm_set_bias_level(dapm, SND_SOC_BIAS_STANDBY);
3249 + if (dapm->bias_level == SND_SOC_BIAS_PREPARE)
3250 + snd_soc_dapm_set_bias_level(dapm,
3251 + SND_SOC_BIAS_STANDBY);
3252 }
3253 }
3254
3255 @@ -2630,7 +2634,9 @@ void snd_soc_dapm_shutdown(struct snd_soc_card *card)
3256
3257 list_for_each_entry(codec, &card->codec_dev_list, list) {
3258 soc_dapm_shutdown_codec(&codec->dapm);
3259 - snd_soc_dapm_set_bias_level(&codec->dapm, SND_SOC_BIAS_OFF);
3260 + if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
3261 + snd_soc_dapm_set_bias_level(&codec->dapm,
3262 + SND_SOC_BIAS_OFF);
3263 }
3264 }
3265

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