| 1 |
From: Francois Romieu <romieu@fr.zoreil.com>
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| 2 |
Date: Wed, 26 Jul 2006 21:14:13 +0000 (+0200)
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| 3 |
Subject: r8169: sync with vendor's driver
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| 4 |
X-Git-Tag: v2.6.18-rc3
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| 5 |
X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=bcf0bf90cd9e9242b66e0563b6a8c8db2e4c262c
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| 6 |
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| 7 |
r8169: sync with vendor's driver
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| 8 |
|
| 9 |
- add several PCI ID for the PCI-E adapters ;
|
| 10 |
- new identification strings ;
|
| 11 |
- the RTL_GIGA_MAC_VER_ defines have been renamed to closely match the
|
| 12 |
out-of-tree driver. It makes the comparison less hairy ;
|
| 13 |
- various magic ;
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| 14 |
- the PCI region for the device with PCI ID 0x8136 is guessed.
|
| 15 |
Explanation: the in-kernel Linux driver is written to allow MM register
|
| 16 |
accesses and avoid the IO tax. The relevant BAR register was found at
|
| 17 |
base address 1 for the plain-old PCI 8169. User reported lspci show that
|
| 18 |
it is found at base address 2 for the new Gigabit PCI-E 816{8/9}.
|
| 19 |
Typically:
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| 20 |
01:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd.: Unknown device 8168 (rev 01)
|
| 21 |
Subsystem: Unknown device 1631:e015
|
| 22 |
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
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| 23 |
Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
|
| 24 |
Latency: 0, cache line size 20
|
| 25 |
Interrupt: pin A routed to IRQ 16
|
| 26 |
Region 0: I/O ports at b800 [size=256]
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| 27 |
Region 2: Memory at ff7ff000 (64-bit, non-prefetchable) [size=4K]
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| 28 |
^^^^^^^^
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| 29 |
So far I have not received any lspci report for the 0x8136 and
|
| 30 |
Realtek's driver do not help: be it under BSD or Linux, their r1000 driver
|
| 31 |
include a USE_IO_SPACE #define but the bar address is always hardcoded
|
| 32 |
to 1 in the MM case. :o/
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| 33 |
- the 8168 has been reported to require an extra alignment for its receive
|
| 34 |
buffers. The status of the 8167 and 8136 is not known in this regard.
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| 35 |
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| 36 |
Signed-off-by: Francois Romieu <romieu@fr.zoreil.com>
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| 37 |
Rediffed for 2.6.18 by Daniel Drake <dsd@gentoo.org>
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| 38 |
Also includes commits d2eed8cff9a1a5d7e12ec9ddf71432c466b104d0 and
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| 39 |
d81bf551103cc3bc9e4f7ddf337511d6da0d088f
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| 40 |
---
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| 41 |
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| 42 |
Index: linux-2.6.18/drivers/net/r8169.c
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| 43 |
===================================================================
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| 44 |
--- linux-2.6.18.orig/drivers/net/r8169.c
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| 45 |
+++ linux-2.6.18/drivers/net/r8169.c
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| 46 |
@@ -150,11 +150,16 @@ static const int multicast_filter_limit
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| 47 |
#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
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| 48 |
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| 49 |
enum mac_version {
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| 50 |
- RTL_GIGA_MAC_VER_B = 0x00,
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| 51 |
- /* RTL_GIGA_MAC_VER_C = 0x03, */
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| 52 |
- RTL_GIGA_MAC_VER_D = 0x01,
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| 53 |
- RTL_GIGA_MAC_VER_E = 0x02,
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| 54 |
- RTL_GIGA_MAC_VER_X = 0x04 /* Greater than RTL_GIGA_MAC_VER_E */
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| 55 |
+ RTL_GIGA_MAC_VER_01 = 0x00,
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| 56 |
+ RTL_GIGA_MAC_VER_02 = 0x01,
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| 57 |
+ RTL_GIGA_MAC_VER_03 = 0x02,
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| 58 |
+ RTL_GIGA_MAC_VER_04 = 0x03,
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| 59 |
+ RTL_GIGA_MAC_VER_05 = 0x04,
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| 60 |
+ RTL_GIGA_MAC_VER_11 = 0x0b,
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+ RTL_GIGA_MAC_VER_12 = 0x0c,
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+ RTL_GIGA_MAC_VER_13 = 0x0d,
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| 63 |
+ RTL_GIGA_MAC_VER_14 = 0x0e,
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| 64 |
+ RTL_GIGA_MAC_VER_15 = 0x0f
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| 65 |
};
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| 66 |
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| 67 |
enum phy_version {
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@@ -166,7 +171,6 @@ enum phy_version {
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| 69 |
RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
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| 70 |
};
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| 71 |
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| 72 |
-
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| 73 |
#define _R(NAME,MAC,MASK) \
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| 74 |
{ .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
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| 75 |
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| 76 |
@@ -175,19 +179,44 @@ static const struct {
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| 77 |
u8 mac_version;
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| 78 |
u32 RxConfigMask; /* Clears the bits supported by this chip */
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| 79 |
} rtl_chip_info[] = {
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| 80 |
- _R("RTL8169", RTL_GIGA_MAC_VER_B, 0xff7e1880),
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- _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_D, 0xff7e1880),
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- _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_E, 0xff7e1880),
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| 83 |
- _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_X, 0xff7e1880),
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+ _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880),
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| 85 |
+ _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_02, 0xff7e1880),
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| 86 |
+ _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880),
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| 87 |
+ _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880),
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| 88 |
+ _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880),
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| 89 |
+ _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
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| 90 |
+ _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
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| 91 |
+ _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
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| 92 |
+ _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
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| 93 |
+ _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880) // PCI-E 8139
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| 94 |
};
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| 95 |
#undef _R
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| 96 |
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| 97 |
+enum cfg_version {
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| 98 |
+ RTL_CFG_0 = 0x00,
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| 99 |
+ RTL_CFG_1,
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+ RTL_CFG_2
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| 101 |
+};
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| 102 |
+
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| 103 |
+static const struct {
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| 104 |
+ unsigned int region;
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+ unsigned int align;
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+} rtl_cfg_info[] = {
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| 107 |
+ [RTL_CFG_0] = { 1, NET_IP_ALIGN },
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+ [RTL_CFG_1] = { 2, NET_IP_ALIGN },
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+ [RTL_CFG_2] = { 2, 8 }
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| 110 |
+};
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| 111 |
+
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| 112 |
static struct pci_device_id rtl8169_pci_tbl[] = {
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| 113 |
- { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), },
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| 114 |
- { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), },
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| 115 |
- { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), },
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| 116 |
- { PCI_DEVICE(0x16ec, 0x0116), },
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| 117 |
- { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024, },
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| 118 |
+ { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
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| 119 |
+ { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
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| 120 |
+ { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
|
| 121 |
+ { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_2 },
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| 122 |
+ { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
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| 123 |
+ { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
|
| 124 |
+ { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
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| 125 |
+ { PCI_VENDOR_ID_LINKSYS, 0x1032,
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| 126 |
+ PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
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| 127 |
{0,},
|
| 128 |
};
|
| 129 |
|
| 130 |
@@ -346,6 +375,7 @@ enum RTL8169_register_content {
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| 131 |
PHY_Cap_100_Full = 0x0100,
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| 132 |
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| 133 |
/* PHY_1000_CTRL_REG = 9 */
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| 134 |
+ PHY_Cap_1000_Half = 0x0100,
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| 135 |
PHY_Cap_1000_Full = 0x0200,
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| 136 |
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| 137 |
PHY_Cap_Null = 0x0,
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| 138 |
@@ -433,6 +463,7 @@ struct rtl8169_private {
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| 139 |
dma_addr_t RxPhyAddr;
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| 140 |
struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
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| 141 |
struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
|
| 142 |
+ unsigned align;
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| 143 |
unsigned rx_buf_sz;
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| 144 |
struct timer_list timer;
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| 145 |
u16 cp_cmd;
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| 146 |
@@ -749,25 +780,43 @@ static int rtl8169_set_speed_xmii(struct
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| 147 |
auto_nego &= ~(PHY_Cap_10_Half | PHY_Cap_10_Full |
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| 148 |
PHY_Cap_100_Half | PHY_Cap_100_Full);
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| 149 |
giga_ctrl = mdio_read(ioaddr, PHY_1000_CTRL_REG);
|
| 150 |
- giga_ctrl &= ~(PHY_Cap_1000_Full | PHY_Cap_Null);
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| 151 |
+ giga_ctrl &= ~(PHY_Cap_1000_Full | PHY_Cap_1000_Half | PHY_Cap_Null);
|
| 152 |
|
| 153 |
if (autoneg == AUTONEG_ENABLE) {
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| 154 |
auto_nego |= (PHY_Cap_10_Half | PHY_Cap_10_Full |
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| 155 |
PHY_Cap_100_Half | PHY_Cap_100_Full);
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| 156 |
- giga_ctrl |= PHY_Cap_1000_Full;
|
| 157 |
+ giga_ctrl |= PHY_Cap_1000_Full | PHY_Cap_1000_Half;
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| 158 |
} else {
|
| 159 |
if (speed == SPEED_10)
|
| 160 |
auto_nego |= PHY_Cap_10_Half | PHY_Cap_10_Full;
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| 161 |
else if (speed == SPEED_100)
|
| 162 |
auto_nego |= PHY_Cap_100_Half | PHY_Cap_100_Full;
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| 163 |
else if (speed == SPEED_1000)
|
| 164 |
- giga_ctrl |= PHY_Cap_1000_Full;
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| 165 |
+ giga_ctrl |= PHY_Cap_1000_Full | PHY_Cap_1000_Half;
|
| 166 |
|
| 167 |
if (duplex == DUPLEX_HALF)
|
| 168 |
auto_nego &= ~(PHY_Cap_10_Full | PHY_Cap_100_Full);
|
| 169 |
|
| 170 |
if (duplex == DUPLEX_FULL)
|
| 171 |
auto_nego &= ~(PHY_Cap_10_Half | PHY_Cap_100_Half);
|
| 172 |
+
|
| 173 |
+ /* This tweak comes straight from Realtek's driver. */
|
| 174 |
+ if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
|
| 175 |
+ (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
|
| 176 |
+ auto_nego = PHY_Cap_100_Half | 0x01;
|
| 177 |
+ }
|
| 178 |
+ }
|
| 179 |
+
|
| 180 |
+ /* The 8100e/8101e do Fast Ethernet only. */
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| 181 |
+ if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
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| 182 |
+ (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
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| 183 |
+ (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
|
| 184 |
+ if ((giga_ctrl & (PHY_Cap_1000_Full | PHY_Cap_1000_Half)) &&
|
| 185 |
+ netif_msg_link(tp)) {
|
| 186 |
+ printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
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| 187 |
+ dev->name);
|
| 188 |
+ }
|
| 189 |
+ giga_ctrl &= ~(PHY_Cap_1000_Full | PHY_Cap_1000_Half);
|
| 190 |
}
|
| 191 |
|
| 192 |
tp->phy_auto_nego_reg = auto_nego;
|
| 193 |
@@ -1140,10 +1189,16 @@ static void rtl8169_get_mac_version(stru
|
| 194 |
u32 mask;
|
| 195 |
int mac_version;
|
| 196 |
} mac_info[] = {
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| 197 |
- { 0x1 << 28, RTL_GIGA_MAC_VER_X },
|
| 198 |
- { 0x1 << 26, RTL_GIGA_MAC_VER_E },
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| 199 |
- { 0x1 << 23, RTL_GIGA_MAC_VER_D },
|
| 200 |
- { 0x00000000, RTL_GIGA_MAC_VER_B } /* Catch-all */
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| 201 |
+ { 0x38800000, RTL_GIGA_MAC_VER_15 },
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| 202 |
+ { 0x38000000, RTL_GIGA_MAC_VER_12 },
|
| 203 |
+ { 0x34000000, RTL_GIGA_MAC_VER_13 },
|
| 204 |
+ { 0x30800000, RTL_GIGA_MAC_VER_14 },
|
| 205 |
+ { 0x30000000, RTL_GIGA_MAC_VER_11 },
|
| 206 |
+ { 0x18000000, RTL_GIGA_MAC_VER_05 },
|
| 207 |
+ { 0x10000000, RTL_GIGA_MAC_VER_04 },
|
| 208 |
+ { 0x04000000, RTL_GIGA_MAC_VER_03 },
|
| 209 |
+ { 0x00800000, RTL_GIGA_MAC_VER_02 },
|
| 210 |
+ { 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
|
| 211 |
}, *p = mac_info;
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| 212 |
u32 reg;
|
| 213 |
|
| 214 |
@@ -1155,24 +1210,7 @@ static void rtl8169_get_mac_version(stru
|
| 215 |
|
| 216 |
static void rtl8169_print_mac_version(struct rtl8169_private *tp)
|
| 217 |
{
|
| 218 |
- struct {
|
| 219 |
- int version;
|
| 220 |
- char *msg;
|
| 221 |
- } mac_print[] = {
|
| 222 |
- { RTL_GIGA_MAC_VER_E, "RTL_GIGA_MAC_VER_E" },
|
| 223 |
- { RTL_GIGA_MAC_VER_D, "RTL_GIGA_MAC_VER_D" },
|
| 224 |
- { RTL_GIGA_MAC_VER_B, "RTL_GIGA_MAC_VER_B" },
|
| 225 |
- { 0, NULL }
|
| 226 |
- }, *p;
|
| 227 |
-
|
| 228 |
- for (p = mac_print; p->msg; p++) {
|
| 229 |
- if (tp->mac_version == p->version) {
|
| 230 |
- dprintk("mac_version == %s (%04d)\n", p->msg,
|
| 231 |
- p->version);
|
| 232 |
- return;
|
| 233 |
- }
|
| 234 |
- }
|
| 235 |
- dprintk("mac_version == Unknown\n");
|
| 236 |
+ dprintk("mac_version = 0x%02x\n", tp->mac_version);
|
| 237 |
}
|
| 238 |
|
| 239 |
static void rtl8169_get_phy_version(struct rtl8169_private *tp, void __iomem *ioaddr)
|
| 240 |
@@ -1257,7 +1295,7 @@ static void rtl8169_hw_phy_config(struct
|
| 241 |
rtl8169_print_mac_version(tp);
|
| 242 |
rtl8169_print_phy_version(tp);
|
| 243 |
|
| 244 |
- if (tp->mac_version <= RTL_GIGA_MAC_VER_B)
|
| 245 |
+ if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
|
| 246 |
return;
|
| 247 |
if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
|
| 248 |
return;
|
| 249 |
@@ -1267,7 +1305,7 @@ static void rtl8169_hw_phy_config(struct
|
| 250 |
|
| 251 |
/* Shazam ! */
|
| 252 |
|
| 253 |
- if (tp->mac_version == RTL_GIGA_MAC_VER_X) {
|
| 254 |
+ if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
|
| 255 |
mdio_write(ioaddr, 31, 0x0001);
|
| 256 |
mdio_write(ioaddr, 9, 0x273a);
|
| 257 |
mdio_write(ioaddr, 14, 0x7bfb);
|
| 258 |
@@ -1306,7 +1344,7 @@ static void rtl8169_phy_timer(unsigned l
|
| 259 |
void __iomem *ioaddr = tp->mmio_addr;
|
| 260 |
unsigned long timeout = RTL8169_PHY_TIMEOUT;
|
| 261 |
|
| 262 |
- assert(tp->mac_version > RTL_GIGA_MAC_VER_B);
|
| 263 |
+ assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
|
| 264 |
assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
|
| 265 |
|
| 266 |
if (!(tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full))
|
| 267 |
@@ -1342,7 +1380,7 @@ static inline void rtl8169_delete_timer(
|
| 268 |
struct rtl8169_private *tp = netdev_priv(dev);
|
| 269 |
struct timer_list *timer = &tp->timer;
|
| 270 |
|
| 271 |
- if ((tp->mac_version <= RTL_GIGA_MAC_VER_B) ||
|
| 272 |
+ if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
|
| 273 |
(tp->phy_version >= RTL_GIGA_PHY_VER_H))
|
| 274 |
return;
|
| 275 |
|
| 276 |
@@ -1354,7 +1392,7 @@ static inline void rtl8169_request_timer
|
| 277 |
struct rtl8169_private *tp = netdev_priv(dev);
|
| 278 |
struct timer_list *timer = &tp->timer;
|
| 279 |
|
| 280 |
- if ((tp->mac_version <= RTL_GIGA_MAC_VER_B) ||
|
| 281 |
+ if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
|
| 282 |
(tp->phy_version >= RTL_GIGA_PHY_VER_H))
|
| 283 |
return;
|
| 284 |
|
| 285 |
@@ -1393,8 +1431,9 @@ static void rtl8169_release_board(struct
|
| 286 |
|
| 287 |
static int __devinit
|
| 288 |
rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
|
| 289 |
- void __iomem **ioaddr_out)
|
| 290 |
+ void __iomem **ioaddr_out, const struct pci_device_id *ent)
|
| 291 |
{
|
| 292 |
+ const unsigned int region = rtl_cfg_info[ent->driver_data].region;
|
| 293 |
void __iomem *ioaddr;
|
| 294 |
struct net_device *dev;
|
| 295 |
struct rtl8169_private *tp;
|
| 296 |
@@ -1441,7 +1480,7 @@ rtl8169_init_board(struct pci_dev *pdev,
|
| 297 |
}
|
| 298 |
|
| 299 |
/* make sure PCI base addr 1 is MMIO */
|
| 300 |
- if (!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
|
| 301 |
+ if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
|
| 302 |
if (netif_msg_probe(tp))
|
| 303 |
dev_err(&pdev->dev,
|
| 304 |
"region #1 not an MMIO resource, aborting\n");
|
| 305 |
@@ -1449,7 +1488,7 @@ rtl8169_init_board(struct pci_dev *pdev,
|
| 306 |
goto err_out_mwi;
|
| 307 |
}
|
| 308 |
/* check for weird/broken PCI region reporting */
|
| 309 |
- if (pci_resource_len(pdev, 1) < R8169_REGS_SIZE) {
|
| 310 |
+ if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
|
| 311 |
if (netif_msg_probe(tp))
|
| 312 |
dev_err(&pdev->dev,
|
| 313 |
"Invalid PCI region size(s), aborting\n");
|
| 314 |
@@ -1483,7 +1522,7 @@ rtl8169_init_board(struct pci_dev *pdev,
|
| 315 |
pci_set_master(pdev);
|
| 316 |
|
| 317 |
/* ioremap MMIO region */
|
| 318 |
- ioaddr = ioremap(pci_resource_start(pdev, 1), R8169_REGS_SIZE);
|
| 319 |
+ ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
|
| 320 |
if (ioaddr == NULL) {
|
| 321 |
if (netif_msg_probe(tp))
|
| 322 |
dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
|
| 323 |
@@ -1574,7 +1613,7 @@ rtl8169_init_one(struct pci_dev *pdev, c
|
| 324 |
MODULENAME, RTL8169_VERSION);
|
| 325 |
}
|
| 326 |
|
| 327 |
- rc = rtl8169_init_board(pdev, &dev, &ioaddr);
|
| 328 |
+ rc = rtl8169_init_board(pdev, &dev, &ioaddr, ent);
|
| 329 |
if (rc)
|
| 330 |
return rc;
|
| 331 |
|
| 332 |
@@ -1632,6 +1671,7 @@ rtl8169_init_one(struct pci_dev *pdev, c
|
| 333 |
tp->intr_mask = 0xffff;
|
| 334 |
tp->pci_dev = pdev;
|
| 335 |
tp->mmio_addr = ioaddr;
|
| 336 |
+ tp->align = rtl_cfg_info[ent->driver_data].align;
|
| 337 |
|
| 338 |
spin_lock_init(&tp->lock);
|
| 339 |
|
| 340 |
@@ -1641,11 +1681,6 @@ rtl8169_init_one(struct pci_dev *pdev, c
|
| 341 |
return rc;
|
| 342 |
}
|
| 343 |
|
| 344 |
- if (netif_msg_probe(tp)) {
|
| 345 |
- printk(KERN_DEBUG "%s: Identified chip type is '%s'.\n",
|
| 346 |
- dev->name, rtl_chip_info[tp->chipset].name);
|
| 347 |
- }
|
| 348 |
-
|
| 349 |
pci_set_drvdata(pdev, dev);
|
| 350 |
|
| 351 |
if (netif_msg_probe(tp)) {
|
| 352 |
@@ -1653,7 +1688,7 @@ rtl8169_init_one(struct pci_dev *pdev, c
|
| 353 |
"%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
|
| 354 |
"IRQ %d\n",
|
| 355 |
dev->name,
|
| 356 |
- rtl_chip_info[ent->driver_data].name,
|
| 357 |
+ rtl_chip_info[tp->chipset].name,
|
| 358 |
dev->base_addr,
|
| 359 |
dev->dev_addr[0], dev->dev_addr[1],
|
| 360 |
dev->dev_addr[2], dev->dev_addr[3],
|
| 361 |
@@ -1665,12 +1700,12 @@ rtl8169_init_one(struct pci_dev *pdev, c
|
| 362 |
dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
|
| 363 |
RTL_W8(0x82, 0x01);
|
| 364 |
|
| 365 |
- if (tp->mac_version < RTL_GIGA_MAC_VER_E) {
|
| 366 |
+ if (tp->mac_version < RTL_GIGA_MAC_VER_03) {
|
| 367 |
dprintk("Set PCI Latency=0x40\n");
|
| 368 |
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
|
| 369 |
}
|
| 370 |
|
| 371 |
- if (tp->mac_version == RTL_GIGA_MAC_VER_D) {
|
| 372 |
+ if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
|
| 373 |
dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
|
| 374 |
RTL_W8(0x82, 0x01);
|
| 375 |
dprintk("Set PHY Reg 0x0bh = 0x00h\n");
|
| 376 |
@@ -1780,6 +1815,7 @@ rtl8169_hw_start(struct net_device *dev)
|
| 377 |
{
|
| 378 |
struct rtl8169_private *tp = netdev_priv(dev);
|
| 379 |
void __iomem *ioaddr = tp->mmio_addr;
|
| 380 |
+ struct pci_dev *pdev = tp->pci_dev;
|
| 381 |
u32 i;
|
| 382 |
|
| 383 |
/* Soft reset the chip. */
|
| 384 |
@@ -1792,8 +1828,28 @@ rtl8169_hw_start(struct net_device *dev)
|
| 385 |
udelay(10);
|
| 386 |
}
|
| 387 |
|
| 388 |
+ if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
|
| 389 |
+ pci_write_config_word(pdev, 0x68, 0x00);
|
| 390 |
+ pci_write_config_word(pdev, 0x69, 0x08);
|
| 391 |
+ }
|
| 392 |
+
|
| 393 |
+ /* Undocumented stuff. */
|
| 394 |
+ if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
|
| 395 |
+ u16 cmd;
|
| 396 |
+
|
| 397 |
+ /* Realtek's r1000_n.c driver uses '&& 0x01' here. Well... */
|
| 398 |
+ if ((RTL_R8(Config2) & 0x07) & 0x01)
|
| 399 |
+ RTL_W32(0x7c, 0x0007ffff);
|
| 400 |
+
|
| 401 |
+ RTL_W32(0x7c, 0x0007ff00);
|
| 402 |
+
|
| 403 |
+ pci_read_config_word(pdev, PCI_COMMAND, &cmd);
|
| 404 |
+ cmd = cmd & 0xef;
|
| 405 |
+ pci_write_config_word(pdev, PCI_COMMAND, cmd);
|
| 406 |
+ }
|
| 407 |
+
|
| 408 |
+
|
| 409 |
RTL_W8(Cfg9346, Cfg9346_Unlock);
|
| 410 |
- RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
|
| 411 |
RTL_W8(EarlyTxThres, EarlyTxThld);
|
| 412 |
|
| 413 |
/* Low hurts. Let's disable the filtering. */
|
| 414 |
@@ -1808,17 +1864,18 @@ rtl8169_hw_start(struct net_device *dev)
|
| 415 |
RTL_W32(TxConfig,
|
| 416 |
(TX_DMA_BURST << TxDMAShift) | (InterFrameGap <<
|
| 417 |
TxInterFrameGapShift));
|
| 418 |
- tp->cp_cmd |= RTL_R16(CPlusCmd);
|
| 419 |
- RTL_W16(CPlusCmd, tp->cp_cmd);
|
| 420 |
|
| 421 |
- if ((tp->mac_version == RTL_GIGA_MAC_VER_D) ||
|
| 422 |
- (tp->mac_version == RTL_GIGA_MAC_VER_E)) {
|
| 423 |
+ tp->cp_cmd |= RTL_R16(CPlusCmd) | PCIMulRW;
|
| 424 |
+
|
| 425 |
+ if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
|
| 426 |
+ (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
|
| 427 |
dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
|
| 428 |
"Bit-3 and bit-14 MUST be 1\n");
|
| 429 |
- tp->cp_cmd |= (1 << 14) | PCIMulRW;
|
| 430 |
- RTL_W16(CPlusCmd, tp->cp_cmd);
|
| 431 |
+ tp->cp_cmd |= (1 << 14);
|
| 432 |
}
|
| 433 |
|
| 434 |
+ RTL_W16(CPlusCmd, tp->cp_cmd);
|
| 435 |
+
|
| 436 |
/*
|
| 437 |
* Undocumented corner. Supposedly:
|
| 438 |
* (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
|
| 439 |
@@ -1829,6 +1886,7 @@ rtl8169_hw_start(struct net_device *dev)
|
| 440 |
RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32));
|
| 441 |
RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK));
|
| 442 |
RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));
|
| 443 |
+ RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
|
| 444 |
RTL_W8(Cfg9346, Cfg9346_Lock);
|
| 445 |
udelay(10);
|
| 446 |
|
| 447 |
@@ -1910,17 +1968,18 @@ static inline void rtl8169_map_to_asic(s
|
| 448 |
}
|
| 449 |
|
| 450 |
static int rtl8169_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
|
| 451 |
- struct RxDesc *desc, int rx_buf_sz)
|
| 452 |
+ struct RxDesc *desc, int rx_buf_sz,
|
| 453 |
+ unsigned int align)
|
| 454 |
{
|
| 455 |
struct sk_buff *skb;
|
| 456 |
dma_addr_t mapping;
|
| 457 |
int ret = 0;
|
| 458 |
|
| 459 |
- skb = dev_alloc_skb(rx_buf_sz + NET_IP_ALIGN);
|
| 460 |
+ skb = dev_alloc_skb(rx_buf_sz + align);
|
| 461 |
if (!skb)
|
| 462 |
goto err_out;
|
| 463 |
|
| 464 |
- skb_reserve(skb, NET_IP_ALIGN);
|
| 465 |
+ skb_reserve(skb, align);
|
| 466 |
*sk_buff = skb;
|
| 467 |
|
| 468 |
mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
|
| 469 |
@@ -1959,9 +2018,9 @@ static u32 rtl8169_rx_fill(struct rtl816
|
| 470 |
|
| 471 |
if (tp->Rx_skbuff[i])
|
| 472 |
continue;
|
| 473 |
-
|
| 474 |
+
|
| 475 |
ret = rtl8169_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i,
|
| 476 |
- tp->RxDescArray + i, tp->rx_buf_sz);
|
| 477 |
+ tp->RxDescArray + i, tp->rx_buf_sz, tp->align);
|
| 478 |
if (ret < 0)
|
| 479 |
break;
|
| 480 |
}
|
| 481 |
@@ -2372,16 +2431,17 @@ static inline void rtl8169_rx_csum(struc
|
| 482 |
}
|
| 483 |
|
| 484 |
static inline int rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
|
| 485 |
- struct RxDesc *desc, int rx_buf_sz)
|
| 486 |
+ struct RxDesc *desc, int rx_buf_sz,
|
| 487 |
+ unsigned int align)
|
| 488 |
{
|
| 489 |
int ret = -1;
|
| 490 |
|
| 491 |
if (pkt_size < rx_copybreak) {
|
| 492 |
struct sk_buff *skb;
|
| 493 |
|
| 494 |
- skb = dev_alloc_skb(pkt_size + NET_IP_ALIGN);
|
| 495 |
+ skb = dev_alloc_skb(pkt_size + align);
|
| 496 |
if (skb) {
|
| 497 |
- skb_reserve(skb, NET_IP_ALIGN);
|
| 498 |
+ skb_reserve(skb, align);
|
| 499 |
eth_copy_and_sum(skb, sk_buff[0]->data, pkt_size, 0);
|
| 500 |
*sk_buff = skb;
|
| 501 |
rtl8169_mark_to_asic(desc, rx_buf_sz);
|
| 502 |
@@ -2447,13 +2507,13 @@ rtl8169_rx_interrupt(struct net_device *
|
| 503 |
}
|
| 504 |
|
| 505 |
rtl8169_rx_csum(skb, desc);
|
| 506 |
-
|
| 507 |
+
|
| 508 |
pci_dma_sync_single_for_cpu(tp->pci_dev,
|
| 509 |
le64_to_cpu(desc->addr), tp->rx_buf_sz,
|
| 510 |
PCI_DMA_FROMDEVICE);
|
| 511 |
|
| 512 |
if (rtl8169_try_rx_copy(&skb, pkt_size, desc,
|
| 513 |
- tp->rx_buf_sz)) {
|
| 514 |
+ tp->rx_buf_sz, tp->align)) {
|
| 515 |
pci_action = pci_unmap_single;
|
| 516 |
tp->Rx_skbuff[entry] = NULL;
|
| 517 |
}
|
| 518 |
@@ -2716,6 +2776,15 @@ rtl8169_set_rx_mode(struct net_device *d
|
| 519 |
tmp = rtl8169_rx_config | rx_mode |
|
| 520 |
(RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
|
| 521 |
|
| 522 |
+ if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
|
| 523 |
+ (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
|
| 524 |
+ (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
|
| 525 |
+ (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
|
| 526 |
+ (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
|
| 527 |
+ mc_filter[0] = 0xffffffff;
|
| 528 |
+ mc_filter[1] = 0xffffffff;
|
| 529 |
+ }
|
| 530 |
+
|
| 531 |
RTL_W32(RxConfig, tmp);
|
| 532 |
RTL_W32(MAR0 + 0, mc_filter[0]);
|
| 533 |
RTL_W32(MAR0 + 4, mc_filter[1]);
|
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| 
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