/[linux-patches]/genpatches-2.6/historical/2.6.10/4315_promise-pdc2027x.patch
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Contents of /genpatches-2.6/historical/2.6.10/4315_promise-pdc2027x.patch

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Revision 2 - (hide annotations) (download) (as text)
Sat Jun 11 23:16:54 2005 UTC (15 years, 1 month ago) by dsd
File MIME type: text/x-diff
File size: 23135 byte(s)
Import historical releases
1 dsd 2 Promise PATA 2027x driver
2     Taken from libata-dev-2.6 tree
3    
4     Changesets:
5     1.1938.160.2
6     1.1938.256.2
7     1.1938.256.3
8     1.1938.371.2
9    
10     diff -X dontdiff -urNp linux-2.6.10/drivers/scsi/Kconfig linux-dsd/drivers/scsi/Kconfig
11     --- linux-2.6.10/drivers/scsi/Kconfig 2004-12-24 21:35:28.000000000 +0000
12     +++ linux-dsd/drivers/scsi/Kconfig 2005-01-12 23:27:08.348165384 +0000
13     @@ -441,6 +441,14 @@ config SCSI_SATA_NV
14    
15     If unsure, say N.
16    
17     +config SCSI_PATA_PDC2027X
18     + tristate "Promise PATA 2027x support"
19     + depends on SCSI_SATA && PCI
20     + help
21     + This option enables support for Promise PATA pdc20268 to pdc20277 host adapters.
22     +
23     + If unsure, say N.
24     +
25     config SCSI_SATA_PROMISE
26     tristate "Promise SATA TX2/TX4 support"
27     depends on SCSI_SATA && PCI
28     diff -X dontdiff -urNp linux-2.6.10/drivers/scsi/Makefile linux-dsd/drivers/scsi/Makefile
29     --- linux-2.6.10/drivers/scsi/Makefile 2004-12-24 21:35:24.000000000 +0000
30     +++ linux-dsd/drivers/scsi/Makefile 2005-01-12 23:27:08.351164928 +0000
31     @@ -124,6 +124,7 @@ obj-$(CONFIG_SCSI_IBMVSCSI) += ibmvscsi/
32     obj-$(CONFIG_SCSI_SATA_AHCI) += libata.o ahci.o
33     obj-$(CONFIG_SCSI_SATA_SVW) += libata.o sata_svw.o
34     obj-$(CONFIG_SCSI_ATA_PIIX) += libata.o ata_piix.o
35     +obj-$(CONFIG_SCSI_PATA_PDC2027X)+= libata.o pata_pdc2027x.o
36     obj-$(CONFIG_SCSI_SATA_PROMISE) += libata.o sata_promise.o
37     obj-$(CONFIG_SCSI_SATA_SIL) += libata.o sata_sil.o
38     obj-$(CONFIG_SCSI_SATA_VIA) += libata.o sata_via.o
39     diff -X dontdiff -urNp linux-2.6.10/drivers/scsi/pata_pdc2027x.c linux-dsd/drivers/scsi/pata_pdc2027x.c
40     --- linux-2.6.10/drivers/scsi/pata_pdc2027x.c 1970-01-01 01:00:00.000000000 +0100
41     +++ linux-dsd/drivers/scsi/pata_pdc2027x.c 2005-01-12 23:28:21.473048712 +0000
42     @@ -0,0 +1,694 @@
43     +/*
44     + * Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277.
45     + *
46     + * This program is free software; you can redistribute it and/or
47     + * modify it under the terms of the GNU General Public License
48     + * as published by the Free Software Foundation; either version
49     + * 2 of the License, or (at your option) any later version.
50     + *
51     + * Ported to libata by:
52     + * Albert Lee <albertcc@tw.ibm.com> IBM Corporation
53     + *
54     + * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
55     + * Portions Copyright (C) 1999 Promise Technology, Inc.
56     + *
57     + * Author: Frank Tiernan (frankt@promise.com)
58     + * Released under terms of General Public License
59     + *
60     + *
61     + */
62     +#include <linux/kernel.h>
63     +#include <linux/module.h>
64     +#include <linux/pci.h>
65     +#include <linux/init.h>
66     +#include <linux/blkdev.h>
67     +#include <linux/delay.h>
68     +#include "scsi.h"
69     +#include <scsi/scsi_host.h>
70     +#include <linux/libata.h>
71     +#include <asm/io.h>
72     +
73     +#define DRV_NAME "pata_pdc2027x"
74     +#define DRV_VERSION "0.53"
75     +#undef PDC_DEBUG
76     +
77     +#ifdef PDC_DEBUG
78     +#define PDPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__, ## args)
79     +#else
80     +#define PDPRINTK(fmt, args...)
81     +#endif
82     +
83     +enum {
84     + PDC_UDMA_100 = 0,
85     + PDC_UDMA_133 = 1,
86     +
87     + PDC_100_MHZ = 100000000,
88     + PDC_133_MHZ = 133333333,
89     +};
90     +
91     +static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
92     +static void pdc2027x_remove_one(struct pci_dev *pdev);
93     +static void pdc2027x_phy_reset(struct ata_port *ap);
94     +static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev);
95     +static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev);
96     +
97     +/*
98     + * ATA Timing Tables based on 133MHz controller clock.
99     + * These tables are only used when the controller is in 133MHz clock.
100     + * If the controller is in 100MHz clock, the ASIC hardware will
101     + * set the timing registers automatically when "set feature" command
102     + * is issued to the device. However, if the controller clock is 133MHz,
103     + * the following tables must be used.
104     + */
105     +static struct pdc2027x_pio_timing {
106     + u8 value0, value1, value2;
107     +} pdc2027x_pio_timing_tbl [] = {
108     + { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
109     + { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
110     + { 0x23, 0x26, 0x64 }, /* PIO mode 2 */
111     + { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
112     + { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
113     +};
114     +
115     +static struct pdc2027x_mdma_timing {
116     + u8 value0, value1;
117     +} pdc2027x_mdma_timing_tbl [] = {
118     + { 0xdf, 0x5f }, /* MDMA mode 0 */
119     + { 0x6b, 0x27 }, /* MDMA mode 1 */
120     + { 0x69, 0x25 }, /* MDMA mode 2 */
121     +};
122     +
123     +static struct pdc2027x_udma_timing {
124     + u8 value0, value1, value2;
125     +} pdc2027x_udma_timing_tbl [] = {
126     + { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
127     + { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
128     + { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
129     + { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
130     + { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
131     + { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
132     + { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
133     +};
134     +
135     +static struct pci_device_id pdc2027x_pci_tbl[] = {
136     +#ifdef ATA_ENABLE_PATA
137     + { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20268, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_100 },
138     + { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20269, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_133 },
139     + { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20270, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_100 },
140     + { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20271, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_133 },
141     + { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20275, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_133 },
142     + { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20276, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_133 },
143     + { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20277, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_133 },
144     +#endif
145     + { } /* terminate list */
146     +};
147     +
148     +static struct pci_driver pdc2027x_pci_driver = {
149     + .name = DRV_NAME,
150     + .id_table = pdc2027x_pci_tbl,
151     + .probe = pdc2027x_init_one,
152     + .remove = __devexit_p(pdc2027x_remove_one),
153     +};
154     +
155     +static Scsi_Host_Template pdc2027x_sht = {
156     + .module = THIS_MODULE,
157     + .name = DRV_NAME,
158     + .queuecommand = ata_scsi_queuecmd,
159     + .eh_strategy_handler = ata_scsi_error,
160     + .can_queue = ATA_DEF_QUEUE,
161     + .this_id = ATA_SHT_THIS_ID,
162     + .sg_tablesize = LIBATA_MAX_PRD,
163     + .max_sectors = ATA_MAX_SECTORS,
164     + .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
165     + .emulated = ATA_SHT_EMULATED,
166     + .use_clustering = ATA_SHT_USE_CLUSTERING,
167     + .proc_name = DRV_NAME,
168     + .dma_boundary = ATA_DMA_BOUNDARY,
169     + .slave_configure = ata_scsi_slave_config,
170     + .bios_param = ata_std_bios_param,
171     +};
172     +
173     +static struct ata_port_operations pdc2027x_pata_ops = {
174     + .port_disable = ata_port_disable,
175     + .set_piomode = pdc2027x_set_piomode,
176     + .set_dmamode = pdc2027x_set_dmamode,
177     +
178     + .tf_load = ata_tf_load,
179     + .tf_read = ata_tf_read,
180     + .check_status = ata_check_status,
181     + .exec_command = ata_exec_command,
182     + .dev_select = ata_std_dev_select,
183     +
184     + .phy_reset = pdc2027x_phy_reset,
185     +
186     + .bmdma_setup = ata_bmdma_setup,
187     + .bmdma_start = ata_bmdma_start,
188     + .qc_prep = ata_qc_prep,
189     + .qc_issue = ata_qc_issue_prot,
190     + .eng_timeout = ata_eng_timeout,
191     +
192     + .irq_handler = ata_interrupt,
193     + .irq_clear = ata_bmdma_irq_clear,
194     +
195     + .port_start = ata_port_start,
196     + .port_stop = ata_port_stop,
197     +};
198     +
199     +static struct ata_port_info pdc2027x_port_info[] = {
200     + /* PDC_UDMA_100 */
201     + {
202     + .sht = &pdc2027x_sht,
203     + .host_flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS |
204     + ATA_FLAG_SRST,
205     + .pio_mask = 0x1f, /* pio0-4 */
206     + .mwdma_mask = 0x07, /* mwdma0-2 */
207     + .udma_mask = ATA_UDMA5, /* udma0-5 */
208     + .port_ops = &pdc2027x_pata_ops,
209     + },
210     + /* PDC_UDMA_133 */
211     + {
212     + .sht = &pdc2027x_sht,
213     + .host_flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS |
214     + ATA_FLAG_SRST,
215     + .pio_mask = 0x1f, /* pio0-4 */
216     + .mwdma_mask = 0x07, /* mwdma0-2 */
217     + .udma_mask = ATA_UDMA6, /* udma0-6 */
218     + .port_ops = &pdc2027x_pata_ops,
219     + },
220     +};
221     +
222     +MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee");
223     +MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277");
224     +MODULE_LICENSE("GPL");
225     +MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl);
226     +
227     +/**
228     + * pdc_get_indexed_reg - Set pdc202xx extended register
229     + * @ap: Port to which the extended register is set
230     + * @index: index of the extended register
231     + */
232     +static u8 pdc_get_indexed_reg(struct ata_port *ap, u8 index)
233     +{
234     + u8 tmp8;
235     +
236     + outb(index, ap->ioaddr.bmdma_addr + 1);
237     + tmp8 = inb(ap->ioaddr.bmdma_addr + 3);
238     +
239     + PDPRINTK("Get index reg%X[%X] \n", index, tmp8);
240     + return tmp8;
241     +}
242     +/**
243     + * pdc_set_indexed_reg - Read pdc202xx extended register
244     + * @ap: Port to which the extended register is read
245     + * @index: index of the extended register
246     + */
247     +static void pdc_set_indexed_reg(struct ata_port *ap, u8 index, u8 value)
248     +{
249     + outb(index, ap->ioaddr.bmdma_addr + 1);
250     + outb(value, ap->ioaddr.bmdma_addr + 3);
251     + PDPRINTK("Set index reg%X[%X] \n", index, value);
252     +}
253     +/**
254     + * pdc2027x_pata_cbl_detect - Probe host controller cable detect info
255     + * @ap: Port for which cable detect info is desired
256     + *
257     + * Read 80c cable indicator from Promise extended register.
258     + * This register is latched when the system is reset.
259     + *
260     + * LOCKING:
261     + * None (inherited from caller).
262     + */
263     +static void pdc2027x_cbl_detect(struct ata_port *ap)
264     +{
265     + u8 cbl40c;
266     +
267     + /* check cable detect results */
268     + cbl40c = pdc_get_indexed_reg(ap, 0x0b) & 0x04;
269     +
270     + if (cbl40c)
271     + goto cbl40;
272     +
273     + PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no);
274     +
275     + ap->cbl = ATA_CBL_PATA80;
276     + return;
277     +
278     +cbl40:
279     + printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no);
280     + ap->cbl = ATA_CBL_PATA40;
281     + ap->udma_mask &= ATA_UDMA_MASK_40C;
282     +}
283     +/**
284     + * pdc2027x_port_enabled - Check extended register at 0x04 to see whether the port is enabled.
285     + * @ap: Port to check
286     + */
287     +static inline int pdc2027x_port_enabled(struct ata_port *ap)
288     +{
289     + return pdc_get_indexed_reg(ap, 0x04) & 0x02;
290     +}
291     +/**
292     + * pdc2027x_phy_reset - Probe specified port on PATA host controller
293     + * @ap: Port to probe
294     + *
295     + * Probe PATA phy.
296     + *
297     + * LOCKING:
298     + * None (inherited from caller).
299     + */
300     +static void pdc2027x_phy_reset(struct ata_port *ap)
301     +{
302     + /* Check whether port enabled */
303     + if (!pdc2027x_port_enabled(ap)) {
304     + ata_port_disable(ap);
305     + printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
306     + return;
307     + }
308     +
309     + pdc2027x_cbl_detect(ap);
310     + ata_port_probe(ap);
311     + ata_bus_reset(ap);
312     +}
313     +/**
314     + * pdc2027x_set_piomode - Initialize host controller PATA PIO timings
315     + * @ap: Port to configure
316     + * @adev: um
317     + * @pio: PIO mode, 0 - 4
318     + *
319     + * Set PIO mode for device.
320     + *
321     + * LOCKING:
322     + * None (inherited from caller).
323     + */
324     +static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev)
325     +{
326     + unsigned int pio = adev->pio_mode - XFER_PIO_0;
327     + unsigned int drive_dn = (ap->port_no ? 2 : 0) + adev->devno;
328     + u8 adj = (drive_dn%2) ? 0x08 : 0x00;
329     + u8 tmp8;
330     +
331     +
332     + PDPRINTK("adev->pio_mode[%X]\n", adev->pio_mode);
333     +
334     + /* Sanity check */
335     + if(pio > 4) {
336     + printk(KERN_ERR DRV_NAME ": Unknown pio mode [%d] ignored\n", pio);
337     + return;
338     +
339     + }
340     +
341     + /* Set the PIO timing registers using value table for 133MHz */
342     + PDPRINTK("Set pio regs... \n");
343     +
344     + pdc_set_indexed_reg(ap, 0x0c + adj, pdc2027x_pio_timing_tbl[pio].value0);
345     + pdc_set_indexed_reg(ap, 0x0d + adj, pdc2027x_pio_timing_tbl[pio].value1);
346     + pdc_set_indexed_reg(ap, 0x13 + adj, pdc2027x_pio_timing_tbl[pio].value2);
347     +
348     + PDPRINTK("Set pio regs done\n");
349     +
350     + /*
351     + * Check whether the device supports turning off IORDY.
352     + * For PIO3 and above, the device must support IORDY and set bit 10
353     + */
354     + if (adev->id[49] & 0x400) {
355     + /* IORDY_EN & PREFETCH_EN */
356     + /* Turn on Prefetch */
357     + tmp8 = pdc_get_indexed_reg(ap, 0x13 + adj);
358     + pdc_set_indexed_reg(ap, 0x13 + adj, tmp8 | 0x03);
359     +
360     + PDPRINTK("Turn on prefetch\n");
361     + }
362     +
363     + printk(KERN_INFO DRV_NAME ": Set to pio mode[%u] \n", pio);
364     +}
365     +/**
366     + * pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings
367     + * @ap: Port to configure
368     + * @adev: um
369     + * @udma: udma mode, XFER_UDMA_0 to XFER_UDMA_6
370     + *
371     + * Set UDMA mode for device.
372     + *
373     + * LOCKING:
374     + * None (inherited from caller).
375     + */
376     +static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
377     +{
378     + unsigned int dma_mode = adev->dma_mode;
379     + unsigned int drive_dn = (ap->port_no ? 2 : 0) + adev->devno;
380     + u8 adj = (drive_dn%2) ? 0x08 : 0x00;
381     + u8 tmp8;
382     +
383     + if((dma_mode >= XFER_UDMA_0) &&
384     + (dma_mode <= XFER_UDMA_6)) {
385     + /* Set the UDMA timing registers with value table for 133MHz */
386     + unsigned int udma_mode = dma_mode & 0x07;
387     +
388     + if (dma_mode == XFER_UDMA_2) {
389     + /*
390     + * Turn off tHOLD.
391     + * If tHOLD is '1', the hardware will add half clock for data hold time.
392     + * This code segment seems to be no effect. tHOLD will be overwritten below.
393     + */
394     + tmp8 = pdc_get_indexed_reg(ap, 0x10 + adj);
395     + pdc_set_indexed_reg(ap, 0x10 + adj, tmp8 & 0x7f);
396     + }
397     +
398     + PDPRINTK("Set udma regs... \n");
399     + pdc_set_indexed_reg(ap, 0x10 + adj, pdc2027x_udma_timing_tbl[udma_mode].value0);
400     + pdc_set_indexed_reg(ap, 0x11 + adj, pdc2027x_udma_timing_tbl[udma_mode].value1);
401     + pdc_set_indexed_reg(ap, 0x12 + adj, pdc2027x_udma_timing_tbl[udma_mode].value2);
402     + PDPRINTK("Set udma regs done\n");
403     +
404     + printk(KERN_INFO DRV_NAME ": Set to udma mode[%u] \n", udma_mode);
405     +
406     + } else if((dma_mode >= XFER_MW_DMA_0) &&
407     + (dma_mode <= XFER_MW_DMA_2)) {
408     + /* Set the MDMA timing registers with value table for 133MHz */
409     + unsigned int mdma_mode = dma_mode & 0x07;
410     +
411     + PDPRINTK("Set mdma regs... \n");
412     + pdc_set_indexed_reg(ap, 0x0e + adj, pdc2027x_mdma_timing_tbl[mdma_mode].value0);
413     + pdc_set_indexed_reg(ap, 0x0f + adj, pdc2027x_mdma_timing_tbl[mdma_mode].value1);
414     + PDPRINTK("Set mdma regs done\n");
415     +
416     + printk(KERN_INFO DRV_NAME ": Set to mdma mode[%u] \n", mdma_mode);
417     + } else {
418     + printk(KERN_ERR DRV_NAME ": Unknown dma mode [%u] ignored\n", dma_mode);
419     + }
420     +}
421     +/**
422     + * adjust_pll - Adjust the PLL input clock in Hz.
423     + *
424     + * @pdc_controller: controller specific information
425     + * @probe_ent: For the port address
426     + * @pll_clock: The input of PLL in HZ
427     + */
428     +static void pdc_adjust_pll(struct ata_probe_ent *probe_ent, long pll_clock, unsigned int board_idx)
429     +{
430     +
431     + u8 pll_ctl0, pll_ctl1;
432     + long pll_clock_khz = pll_clock / 1000;
433     + long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ;
434     + long ratio = pout_required / pll_clock_khz;
435     + int F, R;
436     +
437     +
438     + /* Sanity check */
439     + if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) {
440     + printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz);
441     + return;
442     + }
443     +
444     +#ifdef PDC_DEBUG
445     + PDPRINTK("pout_required is %ld\n", pout_required);
446     +
447     + /* Show the current clock value of PLL control register
448     + * (maybe already configured by the firmware)
449     + */
450     + outb(0x02, probe_ent->port[1].bmdma_addr + 0x01);
451     + pll_ctl0 = inb(probe_ent->port[1].bmdma_addr + 0x03);
452     + outb(0x03, probe_ent->port[1].bmdma_addr + 0x01);
453     + pll_ctl1 = inb(probe_ent->port[1].bmdma_addr + 0x03);
454     +
455     + PDPRINTK("pll_ctl[%X][%X]\n", pll_ctl0, pll_ctl1);
456     +#endif
457     +
458     + /*
459     + * Calculate the ratio of F, R and OD
460     + * POUT = (F + 2) / (( R + 2) * NO)
461     + */
462     + if (ratio < 8600L) { // 8.6x
463     + /* Using NO = 0x01, R = 0x0D */
464     + R = 0x0d;
465     + } else if (ratio < 12900L) { // 12.9x
466     + /* Using NO = 0x01, R = 0x08 */
467     + R = 0x08;
468     + } else if (ratio < 16100L) { // 16.1x
469     + /* Using NO = 0x01, R = 0x06 */
470     + R = 0x06;
471     + } else if (ratio < 64000L) { // 64x
472     + R = 0x00;
473     + } else {
474     + /* Invalid ratio */
475     + printk(KERN_ERR DRV_NAME ": Invalid ratio %ld, give up!\n", ratio);
476     + return;
477     + }
478     +
479     + F = (ratio * (R+2)) / 1000 - 2;
480     +
481     + if (unlikely(F < 0 || F > 127)) {
482     + /* Invalid F */
483     + printk(KERN_ERR DRV_NAME ": F[%d] invalid!\n", F);
484     + return;
485     + }
486     +
487     + PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio);
488     +
489     + pll_ctl0 = (u8) F;
490     + pll_ctl1 = (u8) R;
491     +
492     + PDPRINTK("Writing pll_ctl[%X][%X]\n", pll_ctl0, pll_ctl1);
493     +
494     + outb(0x02, probe_ent->port[1].bmdma_addr + 0x01);
495     + outb(pll_ctl0, probe_ent->port[1].bmdma_addr + 0x03);
496     + outb(0x03, probe_ent->port[1].bmdma_addr + 0x01);
497     + outb(pll_ctl1, probe_ent->port[1].bmdma_addr + 0x03);
498     +
499     + /* Wait the PLL circuit to be stable */
500     + mdelay(30);
501     +
502     +#ifdef PDC_DEBUG
503     + /*
504     + * Show the current clock value of PLL control register
505     + * (maybe configured by the firmware)
506     + */
507     + outb(0x02, probe_ent->port[1].bmdma_addr + 0x01);
508     + pll_ctl0 = inb(probe_ent->port[1].bmdma_addr + 0x03);
509     + outb(0x03, probe_ent->port[1].bmdma_addr + 0x01);
510     + pll_ctl1 = inb(probe_ent->port[1].bmdma_addr + 0x03);
511     +
512     + PDPRINTK("pll_ctl[%X][%X]\n", pll_ctl0, pll_ctl1);
513     +#endif
514     +
515     + return;
516     +}
517     +/**
518     + * detect_pll_input_clock - Detect the PLL input clock in Hz.
519     + * @probe_ent: for the port address
520     + * Ex. 16949000 on 33MHz PCI bus for pdc20275.
521     + * Half of the PCI clock.
522     + */
523     +static long pdc_detect_pll_input_clock(struct ata_probe_ent *probe_ent)
524     +{
525     + u8 scr1;
526     + unsigned long ctr0;
527     + unsigned long ctr1;
528     + unsigned long ctr2 = 0;
529     + unsigned long ctr3 = 0;
530     +
531     + unsigned long start_count, end_count;
532     + long pll_clock;
533     +
534     + /* Read current counter value */
535     + outb(0x20, probe_ent->port[0].bmdma_addr + 0x01);
536     + ctr0 = inb(probe_ent->port[0].bmdma_addr + 0x03);
537     + outb(0x21, probe_ent->port[0].bmdma_addr + 0x01);
538     + ctr1 = inb(probe_ent->port[0].bmdma_addr + 0x03);
539     +
540     + outb(0x20, probe_ent->port[1].bmdma_addr + 0x01);
541     + ctr2 = inb(probe_ent->port[1].bmdma_addr + 0x03);
542     + outb(0x21, probe_ent->port[1].bmdma_addr + 0x01);
543     + ctr3 = inb(probe_ent->port[1].bmdma_addr + 0x03);
544     +
545     + start_count = (ctr3 << 23 ) | (ctr2 << 15) | (ctr1 << 8) | ctr0;
546     +
547     + PDPRINTK("ctr0[%lX] ctr1[%lX] ctr2 [%lX] ctr3 [%lX]\n", ctr0, ctr1, ctr2, ctr3);
548     +
549     + /* Start the test mode */
550     + outb(0x01, probe_ent->port[0].bmdma_addr + 0x01);
551     + scr1 = inb(probe_ent->port[0].bmdma_addr + 0x03);
552     + PDPRINTK("scr1[%X]\n", scr1);
553     + outb(scr1 | 0x40, probe_ent->port[0].bmdma_addr + 0x03);
554     +
555     + /* Let the counter run for 1000 us. */
556     + udelay(1000);
557     +
558     + /* Read the counter values again */
559     + outb(0x20, probe_ent->port[0].bmdma_addr + 0x01);
560     + ctr0 = inb(probe_ent->port[0].bmdma_addr + 0x03);
561     + outb(0x21, probe_ent->port[0].bmdma_addr + 0x01);
562     + ctr1 = inb(probe_ent->port[0].bmdma_addr + 0x03);
563     +
564     + outb(0x20, probe_ent->port[1].bmdma_addr + 0x01);
565     + ctr2 = inb(probe_ent->port[1].bmdma_addr + 0x03);
566     + outb(0x21, probe_ent->port[1].bmdma_addr + 0x01);
567     + ctr3 = inb(probe_ent->port[1].bmdma_addr + 0x03);
568     +
569     + end_count = (ctr3 << 23 ) | (ctr2 << 15) | (ctr1 << 8) | ctr0;
570     +
571     + PDPRINTK("ctr0[%lX] ctr1[%lX] ctr2 [%lX] ctr3 [%lX]\n", ctr0, ctr1, ctr2, ctr3);
572     +
573     + /* Stop the test mode */
574     + outb(0x01, probe_ent->port[0].bmdma_addr + 0x01);
575     + scr1 = inb(probe_ent->port[0].bmdma_addr + 0x03);
576     + PDPRINTK("scr1[%X]\n", scr1);
577     + outb(scr1 & 0xBF, probe_ent->port[0].bmdma_addr + 0x03);
578     +
579     + /* calculate the input clock in Hz */
580     + pll_clock = (long) ((start_count - end_count) * 1000);
581     +
582     + PDPRINTK("start[%lu] end[%lu] \n", start_count, end_count);
583     + PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock);
584     +
585     + return pll_clock;
586     +}
587     +/**
588     + * pdc_hardware_init - Initialize the hardware.
589     + * @pdev: instance of pci_dev found
590     + * @pdc_controller: controller specific information
591     + * @pe: for the port address
592     + */
593     +static int pdc_hardware_init(struct pci_dev *pdev, struct ata_probe_ent *pe, unsigned int board_idx)
594     +{
595     + long pll_clock;
596     +
597     + /*
598     + * Detect PLL input clock rate.
599     + * On some system, where PCI bus is running at non-standard clock rate.
600     + * Ex. 25MHz or 40MHz, we have to adjust the cycle_time.
601     + * The pdc20275 controller employs PLL circuit to help correct timing registers setting.
602     + */
603     + pll_clock = pdc_detect_pll_input_clock(pe);
604     +
605     + if(pll_clock < 0) /* counter overflow? Try again. */
606     + pll_clock = pdc_detect_pll_input_clock(pe);
607     +
608     + printk(KERN_INFO DRV_NAME ": PLL input clock %ld kHz\n", pll_clock/1000);
609     +
610     + /* Adjust PLL control register */
611     + pdc_adjust_pll(pe, pll_clock, board_idx);
612     +
613     + return 0;
614     +}
615     +/**
616     + * pdc2027x_init_one - PCI probe function
617     + * Called when an instance of PCI adapter is inserted.
618     + * This function checks whether the hardware is supported,
619     + * initialize hardware and register an instance of ata_host_set to
620     + * libata by providing struct ata_probe_ent and ata_device_add().
621     + * (implements struct pci_driver.probe() )
622     + *
623     + * @pdev: instance of pci_dev found
624     + * @ent: matching entry in the id_tbl[]
625     + */
626     +static int __devinit pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
627     +{
628     + static int printed_version;
629     + unsigned int board_idx = (unsigned int) ent->driver_data;
630     +
631     + struct ata_probe_ent *probe_ent = NULL;
632     + int rc;
633     +
634     + if (!printed_version++)
635     + printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
636     +
637     + rc = pci_enable_device(pdev);
638     + if (rc)
639     + return rc;
640     +
641     + rc = pci_request_regions(pdev, DRV_NAME);
642     + if (rc)
643     + goto err_out;
644     +
645     + rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
646     + if (rc)
647     + goto err_out_regions;
648     +
649     + rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
650     + if (rc)
651     + goto err_out_regions;
652     +
653     + /* Prepare the probe entry */
654     + probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
655     + if (probe_ent == NULL) {
656     + rc = -ENOMEM;
657     + goto err_out_regions;
658     + }
659     +
660     + memset(probe_ent, 0, sizeof(*probe_ent));
661     + probe_ent->dev = pci_dev_to_dev(pdev);
662     + INIT_LIST_HEAD(&probe_ent->node);
663     +
664     + probe_ent->sht = pdc2027x_port_info[board_idx].sht;
665     + probe_ent->host_flags = pdc2027x_port_info[board_idx].host_flags;
666     + probe_ent->pio_mask = pdc2027x_port_info[board_idx].pio_mask;
667     + probe_ent->udma_mask = pdc2027x_port_info[board_idx].udma_mask;
668     + probe_ent->port_ops = pdc2027x_port_info[board_idx].port_ops;
669     +
670     + probe_ent->irq = pdev->irq;
671     + probe_ent->irq_flags = SA_SHIRQ;
672     +
673     + probe_ent->port[0].cmd_addr = pci_resource_start(pdev, 0);
674     + ata_std_ports(&probe_ent->port[0]);
675     + probe_ent->port[0].altstatus_addr =
676     + probe_ent->port[0].ctl_addr =
677     + pci_resource_start(pdev, 1) | ATA_PCI_CTL_OFS;
678     + probe_ent->port[0].bmdma_addr = pci_resource_start(pdev, 4);
679     +
680     + probe_ent->port[1].cmd_addr = pci_resource_start(pdev, 2);
681     + ata_std_ports(&probe_ent->port[1]);
682     + probe_ent->port[1].altstatus_addr =
683     + probe_ent->port[1].ctl_addr =
684     + pci_resource_start(pdev, 3) | ATA_PCI_CTL_OFS;
685     + probe_ent->port[1].bmdma_addr = pci_resource_start(pdev, 4) + 8;
686     +
687     + probe_ent->n_ports = 2;
688     +
689     + pci_set_master(pdev);
690     + //pci_enable_intx(pdev);
691     +
692     + /* initialize adapter */
693     + if(pdc_hardware_init(pdev, probe_ent, board_idx) != 0)
694     + goto err_out_free_ent;
695     +
696     + ata_device_add(probe_ent);
697     + kfree(probe_ent);
698     +
699     + return 0;
700     +
701     +err_out_free_ent:
702     + kfree(probe_ent);
703     +err_out_regions:
704     + pci_release_regions(pdev);
705     +err_out:
706     + pci_disable_device(pdev);
707     + return rc;
708     +}
709     +/**
710     + * pdc2027x_remove_one - Called to remove a single instance of the
711     + * adapter.
712     + *
713     + * @dev: The PCI device to remove.
714     + * FIXME: module load/unload not working yet
715     + */
716     +static void __devexit pdc2027x_remove_one(struct pci_dev *pdev)
717     +{
718     + ata_pci_remove_one(pdev);
719     +}
720     +/**
721     + * pdc2027x_init - Called after this module is loaded into the kernel.
722     + */
723     +static int __init pdc2027x_init(void)
724     +{
725     + return pci_module_init(&pdc2027x_pci_driver);
726     +}
727     +/**
728     + * pdc2027x_exit - Called before this module unloaded from the kernel
729     + */
730     +static void __exit pdc2027x_exit(void)
731     +{
732     + pci_unregister_driver(&pdc2027x_pci_driver);
733     +}
734     +
735     +module_init(pdc2027x_init);
736     +module_exit(pdc2027x_exit);

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