/[linux-patches]/genpatches-2.6/tags/2.6.12-12/4100_skge-20050628.patch
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Contents of /genpatches-2.6/tags/2.6.12-12/4100_skge-20050628.patch

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Revision 137 - (show annotations) (download)
Tue Aug 9 21:23:12 2005 UTC (12 years, 10 months ago) by dsd
File size: 202121 byte(s)
2.6.12-12 release
1 From upstream 2.6.13 and netdev-2.6 tree skge branch as of 20050628
2
3 diff -urNpX dontdiff linux-2.6.12/drivers/net/Kconfig linux-dsd/drivers/net/Kconfig
4 --- linux-2.6.12/drivers/net/Kconfig 2005-06-17 20:48:29.000000000 +0100
5 +++ linux-dsd/drivers/net/Kconfig 2005-06-28 00:58:14.000000000 +0100
6 @@ -1932,6 +1932,18 @@ config R8169_VLAN
7
8 If in doubt, say Y.
9
10 +config SKGE
11 + tristate "New SysKonnect GigaEthernet support (EXPERIMENTAL)"
12 + depends on PCI && EXPERIMENTAL
13 + select CRC32
14 + ---help---
15 + This driver support the Marvell Yukon or SysKonnect SK-98xx/SK-95xx
16 + and related Gigabit Ethernet adapters. It is a new smaller driver
17 + driver with better performance and more complete ethtool support.
18 +
19 + It does not support the link failover and network management
20 + features that "portable" vendor supplied sk98lin driver does.
21 +
22 config SK98LIN
23 tristate "Marvell Yukon Chipset / SysKonnect SK-98xx Support"
24 depends on PCI
25 diff -urNpX dontdiff linux-2.6.12/drivers/net/Makefile linux-dsd/drivers/net/Makefile
26 --- linux-2.6.12/drivers/net/Makefile 2005-06-17 20:48:29.000000000 +0100
27 +++ linux-dsd/drivers/net/Makefile 2005-06-28 00:58:14.000000000 +0100
28 @@ -53,6 +53,7 @@ obj-$(CONFIG_FEALNX) += fealnx.o
29 obj-$(CONFIG_TIGON3) += tg3.o
30 obj-$(CONFIG_BNX2) += bnx2.o
31 obj-$(CONFIG_TC35815) += tc35815.o
32 +obj-$(CONFIG_SKGE) += skge.o
33 obj-$(CONFIG_SK98LIN) += sk98lin/
34 obj-$(CONFIG_SKFP) += skfp/
35 obj-$(CONFIG_VIA_RHINE) += via-rhine.o
36 diff -urNpX dontdiff linux-2.6.12/drivers/net/skge.c linux-dsd/drivers/net/skge.c
37 --- linux-2.6.12/drivers/net/skge.c 1970-01-01 01:00:00.000000000 +0100
38 +++ linux-dsd/drivers/net/skge.c 2005-06-28 00:59:57.000000000 +0100
39 @@ -0,0 +1,3334 @@
40 +/*
41 + * New driver for Marvell Yukon chipset and SysKonnect Gigabit
42 + * Ethernet adapters. Based on earlier sk98lin, e100 and
43 + * FreeBSD if_sk drivers.
44 + *
45 + * This driver intentionally does not support all the features
46 + * of the original driver such as link fail-over and link management because
47 + * those should be done at higher levels.
48 + *
49 + * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
50 + *
51 + * This program is free software; you can redistribute it and/or modify
52 + * it under the terms of the GNU General Public License as published by
53 + * the Free Software Foundation; either version 2 of the License, or
54 + * (at your option) any later version.
55 + *
56 + * This program is distributed in the hope that it will be useful,
57 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
58 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
59 + * GNU General Public License for more details.
60 + *
61 + * You should have received a copy of the GNU General Public License
62 + * along with this program; if not, write to the Free Software
63 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
64 + */
65 +
66 +#include <linux/config.h>
67 +#include <linux/kernel.h>
68 +#include <linux/module.h>
69 +#include <linux/moduleparam.h>
70 +#include <linux/netdevice.h>
71 +#include <linux/etherdevice.h>
72 +#include <linux/ethtool.h>
73 +#include <linux/pci.h>
74 +#include <linux/if_vlan.h>
75 +#include <linux/ip.h>
76 +#include <linux/delay.h>
77 +#include <linux/crc32.h>
78 +#include <linux/dma-mapping.h>
79 +#include <asm/irq.h>
80 +
81 +#include "skge.h"
82 +
83 +#define DRV_NAME "skge"
84 +#define DRV_VERSION "0.7"
85 +#define PFX DRV_NAME " "
86 +
87 +#define DEFAULT_TX_RING_SIZE 128
88 +#define DEFAULT_RX_RING_SIZE 512
89 +#define MAX_TX_RING_SIZE 1024
90 +#define MAX_RX_RING_SIZE 4096
91 +#define RX_COPY_THRESHOLD 128
92 +#define RX_BUF_SIZE 1536
93 +#define PHY_RETRIES 1000
94 +#define ETH_JUMBO_MTU 9000
95 +#define TX_WATCHDOG (5 * HZ)
96 +#define NAPI_WEIGHT 64
97 +#define BLINK_HZ (HZ/4)
98 +
99 +MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
100 +MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
101 +MODULE_LICENSE("GPL");
102 +MODULE_VERSION(DRV_VERSION);
103 +
104 +static const u32 default_msg
105 + = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
106 + | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
107 +
108 +static int debug = -1; /* defaults above */
109 +module_param(debug, int, 0);
110 +MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
111 +
112 +static const struct pci_device_id skge_id_table[] = {
113 + { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
114 + { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
115 + { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
116 + { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
117 + { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
118 + { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
119 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
120 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
121 + { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
122 + { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1032) },
123 + { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
124 + { 0 }
125 +};
126 +MODULE_DEVICE_TABLE(pci, skge_id_table);
127 +
128 +static int skge_up(struct net_device *dev);
129 +static int skge_down(struct net_device *dev);
130 +static void skge_tx_clean(struct skge_port *skge);
131 +static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
132 +static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
133 +static void genesis_get_stats(struct skge_port *skge, u64 *data);
134 +static void yukon_get_stats(struct skge_port *skge, u64 *data);
135 +static void yukon_init(struct skge_hw *hw, int port);
136 +static void yukon_reset(struct skge_hw *hw, int port);
137 +static void genesis_mac_init(struct skge_hw *hw, int port);
138 +static void genesis_reset(struct skge_hw *hw, int port);
139 +static void genesis_link_up(struct skge_port *skge);
140 +
141 +/* Avoid conditionals by using array */
142 +static const int txqaddr[] = { Q_XA1, Q_XA2 };
143 +static const int rxqaddr[] = { Q_R1, Q_R2 };
144 +static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
145 +static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
146 +static const u32 portirqmask[] = { IS_PORT_1, IS_PORT_2 };
147 +
148 +/* Don't need to look at whole 16K.
149 + * last interesting register is descriptor poll timer.
150 + */
151 +#define SKGE_REGS_LEN (29*128)
152 +
153 +static int skge_get_regs_len(struct net_device *dev)
154 +{
155 + return SKGE_REGS_LEN;
156 +}
157 +
158 +/*
159 + * Returns copy of control register region
160 + * I/O region is divided into banks and certain regions are unreadable
161 + */
162 +static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
163 + void *p)
164 +{
165 + const struct skge_port *skge = netdev_priv(dev);
166 + unsigned long offs;
167 + const void __iomem *io = skge->hw->regs;
168 + static const unsigned long bankmap
169 + = (1<<0) | (1<<2) | (1<<8) | (1<<9)
170 + | (1<<12) | (1<<13) | (1<<14) | (1<<15) | (1<<16)
171 + | (1<<17) | (1<<20) | (1<<21) | (1<<22) | (1<<23)
172 + | (1<<24) | (1<<25) | (1<<26) | (1<<27) | (1<<28);
173 +
174 + regs->version = 1;
175 + for (offs = 0; offs < regs->len; offs += 128) {
176 + u32 len = min_t(u32, 128, regs->len - offs);
177 +
178 + if (bankmap & (1<<(offs/128)))
179 + memcpy_fromio(p + offs, io + offs, len);
180 + else
181 + memset(p + offs, 0, len);
182 + }
183 +}
184 +
185 +/* Wake on Lan only supported on Yukon chps with rev 1 or above */
186 +static int wol_supported(const struct skge_hw *hw)
187 +{
188 + return !((hw->chip_id == CHIP_ID_GENESIS ||
189 + (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
190 +}
191 +
192 +static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
193 +{
194 + struct skge_port *skge = netdev_priv(dev);
195 +
196 + wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
197 + wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
198 +}
199 +
200 +static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
201 +{
202 + struct skge_port *skge = netdev_priv(dev);
203 + struct skge_hw *hw = skge->hw;
204 +
205 + if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
206 + return -EOPNOTSUPP;
207 +
208 + if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
209 + return -EOPNOTSUPP;
210 +
211 + skge->wol = wol->wolopts == WAKE_MAGIC;
212 +
213 + if (skge->wol) {
214 + memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
215 +
216 + skge_write16(hw, WOL_CTRL_STAT,
217 + WOL_CTL_ENA_PME_ON_MAGIC_PKT |
218 + WOL_CTL_ENA_MAGIC_PKT_UNIT);
219 + } else
220 + skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
221 +
222 + return 0;
223 +}
224 +
225 +/* Determine supported/adverised modes based on hardware.
226 + * Note: ethtoool ADVERTISED_xxx == SUPPORTED_xxx
227 + */
228 +static u32 skge_supported_modes(const struct skge_hw *hw)
229 +{
230 + u32 supported;
231 +
232 + if (iscopper(hw)) {
233 + supported = SUPPORTED_10baseT_Half
234 + | SUPPORTED_10baseT_Full
235 + | SUPPORTED_100baseT_Half
236 + | SUPPORTED_100baseT_Full
237 + | SUPPORTED_1000baseT_Half
238 + | SUPPORTED_1000baseT_Full
239 + | SUPPORTED_Autoneg| SUPPORTED_TP;
240 +
241 + if (hw->chip_id == CHIP_ID_GENESIS)
242 + supported &= ~(SUPPORTED_10baseT_Half
243 + | SUPPORTED_10baseT_Full
244 + | SUPPORTED_100baseT_Half
245 + | SUPPORTED_100baseT_Full);
246 +
247 + else if (hw->chip_id == CHIP_ID_YUKON)
248 + supported &= ~SUPPORTED_1000baseT_Half;
249 + } else
250 + supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
251 + | SUPPORTED_Autoneg;
252 +
253 + return supported;
254 +}
255 +
256 +static int skge_get_settings(struct net_device *dev,
257 + struct ethtool_cmd *ecmd)
258 +{
259 + struct skge_port *skge = netdev_priv(dev);
260 + struct skge_hw *hw = skge->hw;
261 +
262 + ecmd->transceiver = XCVR_INTERNAL;
263 + ecmd->supported = skge_supported_modes(hw);
264 +
265 + if (iscopper(hw)) {
266 + ecmd->port = PORT_TP;
267 + ecmd->phy_address = hw->phy_addr;
268 + } else
269 + ecmd->port = PORT_FIBRE;
270 +
271 + ecmd->advertising = skge->advertising;
272 + ecmd->autoneg = skge->autoneg;
273 + ecmd->speed = skge->speed;
274 + ecmd->duplex = skge->duplex;
275 + return 0;
276 +}
277 +
278 +static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
279 +{
280 + struct skge_port *skge = netdev_priv(dev);
281 + const struct skge_hw *hw = skge->hw;
282 + u32 supported = skge_supported_modes(hw);
283 +
284 + if (ecmd->autoneg == AUTONEG_ENABLE) {
285 + ecmd->advertising = supported;
286 + skge->duplex = -1;
287 + skge->speed = -1;
288 + } else {
289 + u32 setting;
290 +
291 + switch(ecmd->speed) {
292 + case SPEED_1000:
293 + if (ecmd->duplex == DUPLEX_FULL)
294 + setting = SUPPORTED_1000baseT_Full;
295 + else if (ecmd->duplex == DUPLEX_HALF)
296 + setting = SUPPORTED_1000baseT_Half;
297 + else
298 + return -EINVAL;
299 + break;
300 + case SPEED_100:
301 + if (ecmd->duplex == DUPLEX_FULL)
302 + setting = SUPPORTED_100baseT_Full;
303 + else if (ecmd->duplex == DUPLEX_HALF)
304 + setting = SUPPORTED_100baseT_Half;
305 + else
306 + return -EINVAL;
307 + break;
308 +
309 + case SPEED_10:
310 + if (ecmd->duplex == DUPLEX_FULL)
311 + setting = SUPPORTED_10baseT_Full;
312 + else if (ecmd->duplex == DUPLEX_HALF)
313 + setting = SUPPORTED_10baseT_Half;
314 + else
315 + return -EINVAL;
316 + break;
317 + default:
318 + return -EINVAL;
319 + }
320 +
321 + if ((setting & supported) == 0)
322 + return -EINVAL;
323 +
324 + skge->speed = ecmd->speed;
325 + skge->duplex = ecmd->duplex;
326 + }
327 +
328 + skge->autoneg = ecmd->autoneg;
329 + skge->advertising = ecmd->advertising;
330 +
331 + if (netif_running(dev)) {
332 + skge_down(dev);
333 + skge_up(dev);
334 + }
335 + return (0);
336 +}
337 +
338 +static void skge_get_drvinfo(struct net_device *dev,
339 + struct ethtool_drvinfo *info)
340 +{
341 + struct skge_port *skge = netdev_priv(dev);
342 +
343 + strcpy(info->driver, DRV_NAME);
344 + strcpy(info->version, DRV_VERSION);
345 + strcpy(info->fw_version, "N/A");
346 + strcpy(info->bus_info, pci_name(skge->hw->pdev));
347 +}
348 +
349 +static const struct skge_stat {
350 + char name[ETH_GSTRING_LEN];
351 + u16 xmac_offset;
352 + u16 gma_offset;
353 +} skge_stats[] = {
354 + { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
355 + { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
356 +
357 + { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
358 + { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
359 + { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
360 + { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
361 + { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
362 + { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
363 + { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
364 + { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
365 +
366 + { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
367 + { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
368 + { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
369 + { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
370 + { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
371 + { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
372 +
373 + { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
374 + { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
375 + { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
376 + { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
377 + { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
378 +};
379 +
380 +static int skge_get_stats_count(struct net_device *dev)
381 +{
382 + return ARRAY_SIZE(skge_stats);
383 +}
384 +
385 +static void skge_get_ethtool_stats(struct net_device *dev,
386 + struct ethtool_stats *stats, u64 *data)
387 +{
388 + struct skge_port *skge = netdev_priv(dev);
389 +
390 + if (skge->hw->chip_id == CHIP_ID_GENESIS)
391 + genesis_get_stats(skge, data);
392 + else
393 + yukon_get_stats(skge, data);
394 +}
395 +
396 +/* Use hardware MIB variables for critical path statistics and
397 + * transmit feedback not reported at interrupt.
398 + * Other errors are accounted for in interrupt handler.
399 + */
400 +static struct net_device_stats *skge_get_stats(struct net_device *dev)
401 +{
402 + struct skge_port *skge = netdev_priv(dev);
403 + u64 data[ARRAY_SIZE(skge_stats)];
404 +
405 + if (skge->hw->chip_id == CHIP_ID_GENESIS)
406 + genesis_get_stats(skge, data);
407 + else
408 + yukon_get_stats(skge, data);
409 +
410 + skge->net_stats.tx_bytes = data[0];
411 + skge->net_stats.rx_bytes = data[1];
412 + skge->net_stats.tx_packets = data[2] + data[4] + data[6];
413 + skge->net_stats.rx_packets = data[3] + data[5] + data[7];
414 + skge->net_stats.multicast = data[5] + data[7];
415 + skge->net_stats.collisions = data[10];
416 + skge->net_stats.tx_aborted_errors = data[12];
417 +
418 + return &skge->net_stats;
419 +}
420 +
421 +static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
422 +{
423 + int i;
424 +
425 + switch (stringset) {
426 + case ETH_SS_STATS:
427 + for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
428 + memcpy(data + i * ETH_GSTRING_LEN,
429 + skge_stats[i].name, ETH_GSTRING_LEN);
430 + break;
431 + }
432 +}
433 +
434 +static void skge_get_ring_param(struct net_device *dev,
435 + struct ethtool_ringparam *p)
436 +{
437 + struct skge_port *skge = netdev_priv(dev);
438 +
439 + p->rx_max_pending = MAX_RX_RING_SIZE;
440 + p->tx_max_pending = MAX_TX_RING_SIZE;
441 + p->rx_mini_max_pending = 0;
442 + p->rx_jumbo_max_pending = 0;
443 +
444 + p->rx_pending = skge->rx_ring.count;
445 + p->tx_pending = skge->tx_ring.count;
446 + p->rx_mini_pending = 0;
447 + p->rx_jumbo_pending = 0;
448 +}
449 +
450 +static int skge_set_ring_param(struct net_device *dev,
451 + struct ethtool_ringparam *p)
452 +{
453 + struct skge_port *skge = netdev_priv(dev);
454 +
455 + if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
456 + p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
457 + return -EINVAL;
458 +
459 + skge->rx_ring.count = p->rx_pending;
460 + skge->tx_ring.count = p->tx_pending;
461 +
462 + if (netif_running(dev)) {
463 + skge_down(dev);
464 + skge_up(dev);
465 + }
466 +
467 + return 0;
468 +}
469 +
470 +static u32 skge_get_msglevel(struct net_device *netdev)
471 +{
472 + struct skge_port *skge = netdev_priv(netdev);
473 + return skge->msg_enable;
474 +}
475 +
476 +static void skge_set_msglevel(struct net_device *netdev, u32 value)
477 +{
478 + struct skge_port *skge = netdev_priv(netdev);
479 + skge->msg_enable = value;
480 +}
481 +
482 +static int skge_nway_reset(struct net_device *dev)
483 +{
484 + struct skge_port *skge = netdev_priv(dev);
485 + struct skge_hw *hw = skge->hw;
486 + int port = skge->port;
487 +
488 + if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
489 + return -EINVAL;
490 +
491 + spin_lock_bh(&hw->phy_lock);
492 + if (hw->chip_id == CHIP_ID_GENESIS) {
493 + genesis_reset(hw, port);
494 + genesis_mac_init(hw, port);
495 + } else {
496 + yukon_reset(hw, port);
497 + yukon_init(hw, port);
498 + }
499 + spin_unlock_bh(&hw->phy_lock);
500 + return 0;
501 +}
502 +
503 +static int skge_set_sg(struct net_device *dev, u32 data)
504 +{
505 + struct skge_port *skge = netdev_priv(dev);
506 + struct skge_hw *hw = skge->hw;
507 +
508 + if (hw->chip_id == CHIP_ID_GENESIS && data)
509 + return -EOPNOTSUPP;
510 + return ethtool_op_set_sg(dev, data);
511 +}
512 +
513 +static int skge_set_tx_csum(struct net_device *dev, u32 data)
514 +{
515 + struct skge_port *skge = netdev_priv(dev);
516 + struct skge_hw *hw = skge->hw;
517 +
518 + if (hw->chip_id == CHIP_ID_GENESIS && data)
519 + return -EOPNOTSUPP;
520 +
521 + return ethtool_op_set_tx_csum(dev, data);
522 +}
523 +
524 +static u32 skge_get_rx_csum(struct net_device *dev)
525 +{
526 + struct skge_port *skge = netdev_priv(dev);
527 +
528 + return skge->rx_csum;
529 +}
530 +
531 +/* Only Yukon supports checksum offload. */
532 +static int skge_set_rx_csum(struct net_device *dev, u32 data)
533 +{
534 + struct skge_port *skge = netdev_priv(dev);
535 +
536 + if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
537 + return -EOPNOTSUPP;
538 +
539 + skge->rx_csum = data;
540 + return 0;
541 +}
542 +
543 +static void skge_get_pauseparam(struct net_device *dev,
544 + struct ethtool_pauseparam *ecmd)
545 +{
546 + struct skge_port *skge = netdev_priv(dev);
547 +
548 + ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
549 + || (skge->flow_control == FLOW_MODE_SYMMETRIC);
550 + ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
551 + || (skge->flow_control == FLOW_MODE_SYMMETRIC);
552 +
553 + ecmd->autoneg = skge->autoneg;
554 +}
555 +
556 +static int skge_set_pauseparam(struct net_device *dev,
557 + struct ethtool_pauseparam *ecmd)
558 +{
559 + struct skge_port *skge = netdev_priv(dev);
560 +
561 + skge->autoneg = ecmd->autoneg;
562 + if (ecmd->rx_pause && ecmd->tx_pause)
563 + skge->flow_control = FLOW_MODE_SYMMETRIC;
564 + else if (ecmd->rx_pause && !ecmd->tx_pause)
565 + skge->flow_control = FLOW_MODE_REM_SEND;
566 + else if (!ecmd->rx_pause && ecmd->tx_pause)
567 + skge->flow_control = FLOW_MODE_LOC_SEND;
568 + else
569 + skge->flow_control = FLOW_MODE_NONE;
570 +
571 + if (netif_running(dev)) {
572 + skge_down(dev);
573 + skge_up(dev);
574 + }
575 + return 0;
576 +}
577 +
578 +/* Chip internal frequency for clock calculations */
579 +static inline u32 hwkhz(const struct skge_hw *hw)
580 +{
581 + if (hw->chip_id == CHIP_ID_GENESIS)
582 + return 53215; /* or: 53.125 MHz */
583 + else
584 + return 78215; /* or: 78.125 MHz */
585 +}
586 +
587 +/* Chip hz to microseconds */
588 +static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
589 +{
590 + return (ticks * 1000) / hwkhz(hw);
591 +}
592 +
593 +/* Microseconds to chip hz */
594 +static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
595 +{
596 + return hwkhz(hw) * usec / 1000;
597 +}
598 +
599 +static int skge_get_coalesce(struct net_device *dev,
600 + struct ethtool_coalesce *ecmd)
601 +{
602 + struct skge_port *skge = netdev_priv(dev);
603 + struct skge_hw *hw = skge->hw;
604 + int port = skge->port;
605 +
606 + ecmd->rx_coalesce_usecs = 0;
607 + ecmd->tx_coalesce_usecs = 0;
608 +
609 + if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
610 + u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
611 + u32 msk = skge_read32(hw, B2_IRQM_MSK);
612 +
613 + if (msk & rxirqmask[port])
614 + ecmd->rx_coalesce_usecs = delay;
615 + if (msk & txirqmask[port])
616 + ecmd->tx_coalesce_usecs = delay;
617 + }
618 +
619 + return 0;
620 +}
621 +
622 +/* Note: interrupt timer is per board, but can turn on/off per port */
623 +static int skge_set_coalesce(struct net_device *dev,
624 + struct ethtool_coalesce *ecmd)
625 +{
626 + struct skge_port *skge = netdev_priv(dev);
627 + struct skge_hw *hw = skge->hw;
628 + int port = skge->port;
629 + u32 msk = skge_read32(hw, B2_IRQM_MSK);
630 + u32 delay = 25;
631 +
632 + if (ecmd->rx_coalesce_usecs == 0)
633 + msk &= ~rxirqmask[port];
634 + else if (ecmd->rx_coalesce_usecs < 25 ||
635 + ecmd->rx_coalesce_usecs > 33333)
636 + return -EINVAL;
637 + else {
638 + msk |= rxirqmask[port];
639 + delay = ecmd->rx_coalesce_usecs;
640 + }
641 +
642 + if (ecmd->tx_coalesce_usecs == 0)
643 + msk &= ~txirqmask[port];
644 + else if (ecmd->tx_coalesce_usecs < 25 ||
645 + ecmd->tx_coalesce_usecs > 33333)
646 + return -EINVAL;
647 + else {
648 + msk |= txirqmask[port];
649 + delay = min(delay, ecmd->rx_coalesce_usecs);
650 + }
651 +
652 + skge_write32(hw, B2_IRQM_MSK, msk);
653 + if (msk == 0)
654 + skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
655 + else {
656 + skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
657 + skge_write32(hw, B2_IRQM_CTRL, TIM_START);
658 + }
659 + return 0;
660 +}
661 +
662 +static void skge_led_on(struct skge_hw *hw, int port)
663 +{
664 + if (hw->chip_id == CHIP_ID_GENESIS) {
665 + skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
666 + skge_write8(hw, B0_LED, LED_STAT_ON);
667 +
668 + skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
669 + skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
670 + skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
671 +
672 + /* For Broadcom Phy only */
673 + xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
674 + } else {
675 + gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
676 + gm_phy_write(hw, port, PHY_MARV_LED_OVER,
677 + PHY_M_LED_MO_DUP(MO_LED_ON) |
678 + PHY_M_LED_MO_10(MO_LED_ON) |
679 + PHY_M_LED_MO_100(MO_LED_ON) |
680 + PHY_M_LED_MO_1000(MO_LED_ON) |
681 + PHY_M_LED_MO_RX(MO_LED_ON));
682 + }
683 +}
684 +
685 +static void skge_led_off(struct skge_hw *hw, int port)
686 +{
687 + if (hw->chip_id == CHIP_ID_GENESIS) {
688 + skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
689 + skge_write8(hw, B0_LED, LED_STAT_OFF);
690 +
691 + skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
692 + skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
693 +
694 + /* Broadcom only */
695 + xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
696 + } else {
697 + gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
698 + gm_phy_write(hw, port, PHY_MARV_LED_OVER,
699 + PHY_M_LED_MO_DUP(MO_LED_OFF) |
700 + PHY_M_LED_MO_10(MO_LED_OFF) |
701 + PHY_M_LED_MO_100(MO_LED_OFF) |
702 + PHY_M_LED_MO_1000(MO_LED_OFF) |
703 + PHY_M_LED_MO_RX(MO_LED_OFF));
704 + }
705 +}
706 +
707 +static void skge_blink_timer(unsigned long data)
708 +{
709 + struct skge_port *skge = (struct skge_port *) data;
710 + struct skge_hw *hw = skge->hw;
711 + unsigned long flags;
712 +
713 + spin_lock_irqsave(&hw->phy_lock, flags);
714 + if (skge->blink_on)
715 + skge_led_on(hw, skge->port);
716 + else
717 + skge_led_off(hw, skge->port);
718 + spin_unlock_irqrestore(&hw->phy_lock, flags);
719 +
720 + skge->blink_on = !skge->blink_on;
721 + mod_timer(&skge->led_blink, jiffies + BLINK_HZ);
722 +}
723 +
724 +/* blink LED's for finding board */
725 +static int skge_phys_id(struct net_device *dev, u32 data)
726 +{
727 + struct skge_port *skge = netdev_priv(dev);
728 +
729 + if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
730 + data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
731 +
732 + /* start blinking */
733 + skge->blink_on = 1;
734 + mod_timer(&skge->led_blink, jiffies+1);
735 +
736 + msleep_interruptible(data * 1000);
737 + del_timer_sync(&skge->led_blink);
738 +
739 + skge_led_off(skge->hw, skge->port);
740 +
741 + return 0;
742 +}
743 +
744 +static struct ethtool_ops skge_ethtool_ops = {
745 + .get_settings = skge_get_settings,
746 + .set_settings = skge_set_settings,
747 + .get_drvinfo = skge_get_drvinfo,
748 + .get_regs_len = skge_get_regs_len,
749 + .get_regs = skge_get_regs,
750 + .get_wol = skge_get_wol,
751 + .set_wol = skge_set_wol,
752 + .get_msglevel = skge_get_msglevel,
753 + .set_msglevel = skge_set_msglevel,
754 + .nway_reset = skge_nway_reset,
755 + .get_link = ethtool_op_get_link,
756 + .get_ringparam = skge_get_ring_param,
757 + .set_ringparam = skge_set_ring_param,
758 + .get_pauseparam = skge_get_pauseparam,
759 + .set_pauseparam = skge_set_pauseparam,
760 + .get_coalesce = skge_get_coalesce,
761 + .set_coalesce = skge_set_coalesce,
762 + .get_sg = ethtool_op_get_sg,
763 + .set_sg = skge_set_sg,
764 + .get_tx_csum = ethtool_op_get_tx_csum,
765 + .set_tx_csum = skge_set_tx_csum,
766 + .get_rx_csum = skge_get_rx_csum,
767 + .set_rx_csum = skge_set_rx_csum,
768 + .get_strings = skge_get_strings,
769 + .phys_id = skge_phys_id,
770 + .get_stats_count = skge_get_stats_count,
771 + .get_ethtool_stats = skge_get_ethtool_stats,
772 +};
773 +
774 +/*
775 + * Allocate ring elements and chain them together
776 + * One-to-one association of board descriptors with ring elements
777 + */
778 +static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
779 +{
780 + struct skge_tx_desc *d;
781 + struct skge_element *e;
782 + int i;
783 +
784 + ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);
785 + if (!ring->start)
786 + return -ENOMEM;
787 +
788 + for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
789 + e->desc = d;
790 + e->skb = NULL;
791 + if (i == ring->count - 1) {
792 + e->next = ring->start;
793 + d->next_offset = base;
794 + } else {
795 + e->next = e + 1;
796 + d->next_offset = base + (i+1) * sizeof(*d);
797 + }
798 + }
799 + ring->to_use = ring->to_clean = ring->start;
800 +
801 + return 0;
802 +}
803 +
804 +static struct sk_buff *skge_rx_alloc(struct net_device *dev, unsigned int size)
805 +{
806 + struct sk_buff *skb = dev_alloc_skb(size);
807 +
808 + if (likely(skb)) {
809 + skb->dev = dev;
810 + skb_reserve(skb, NET_IP_ALIGN);
811 + }
812 + return skb;
813 +}
814 +
815 +/* Allocate and setup a new buffer for receiving */
816 +static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
817 + struct sk_buff *skb, unsigned int bufsize)
818 +{
819 + struct skge_rx_desc *rd = e->desc;
820 + u64 map;
821 +
822 + map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
823 + PCI_DMA_FROMDEVICE);
824 +
825 + rd->dma_lo = map;
826 + rd->dma_hi = map >> 32;
827 + e->skb = skb;
828 + rd->csum1_start = ETH_HLEN;
829 + rd->csum2_start = ETH_HLEN;
830 + rd->csum1 = 0;
831 + rd->csum2 = 0;
832 +
833 + wmb();
834 +
835 + rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
836 + pci_unmap_addr_set(e, mapaddr, map);
837 + pci_unmap_len_set(e, maplen, bufsize);
838 +}
839 +
840 +/* Resume receiving using existing skb,
841 + * Note: DMA address is not changed by chip.
842 + * MTU not changed while receiver active.
843 + */
844 +static void skge_rx_reuse(struct skge_element *e, unsigned int size)
845 +{
846 + struct skge_rx_desc *rd = e->desc;
847 +
848 + rd->csum2 = 0;
849 + rd->csum2_start = ETH_HLEN;
850 +
851 + wmb();
852 +
853 + rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
854 +}
855 +
856 +
857 +/* Free all buffers in receive ring, assumes receiver stopped */
858 +static void skge_rx_clean(struct skge_port *skge)
859 +{
860 + struct skge_hw *hw = skge->hw;
861 + struct skge_ring *ring = &skge->rx_ring;
862 + struct skge_element *e;
863 +
864 + e = ring->start;
865 + do {
866 + struct skge_rx_desc *rd = e->desc;
867 + rd->control = 0;
868 + if (e->skb) {
869 + pci_unmap_single(hw->pdev,
870 + pci_unmap_addr(e, mapaddr),
871 + pci_unmap_len(e, maplen),
872 + PCI_DMA_FROMDEVICE);
873 + dev_kfree_skb(e->skb);
874 + e->skb = NULL;
875 + }
876 + } while ((e = e->next) != ring->start);
877 +}
878 +
879 +
880 +/* Allocate buffers for receive ring
881 + * For receive: to_clean is next received frame.
882 + */
883 +static int skge_rx_fill(struct skge_port *skge)
884 +{
885 + struct skge_ring *ring = &skge->rx_ring;
886 + struct skge_element *e;
887 + unsigned int bufsize = skge->rx_buf_size;
888 +
889 + e = ring->start;
890 + do {
891 + struct sk_buff *skb = skge_rx_alloc(skge->netdev, bufsize);
892 +
893 + if (!skb)
894 + return -ENOMEM;
895 +
896 + skge_rx_setup(skge, e, skb, bufsize);
897 + } while ( (e = e->next) != ring->start);
898 +
899 + ring->to_clean = ring->start;
900 + return 0;
901 +}
902 +
903 +static void skge_link_up(struct skge_port *skge)
904 +{
905 + netif_carrier_on(skge->netdev);
906 + if (skge->tx_avail > MAX_SKB_FRAGS + 1)
907 + netif_wake_queue(skge->netdev);
908 +
909 + if (netif_msg_link(skge))
910 + printk(KERN_INFO PFX
911 + "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
912 + skge->netdev->name, skge->speed,
913 + skge->duplex == DUPLEX_FULL ? "full" : "half",
914 + (skge->flow_control == FLOW_MODE_NONE) ? "none" :
915 + (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
916 + (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
917 + (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
918 + "unknown");
919 +}
920 +
921 +static void skge_link_down(struct skge_port *skge)
922 +{
923 + netif_carrier_off(skge->netdev);
924 + netif_stop_queue(skge->netdev);
925 +
926 + if (netif_msg_link(skge))
927 + printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
928 +}
929 +
930 +static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
931 +{
932 + int i;
933 + u16 v;
934 +
935 + xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
936 + v = xm_read16(hw, port, XM_PHY_DATA);
937 +
938 + /* Need to wait for external PHY */
939 + for (i = 0; i < PHY_RETRIES; i++) {
940 + udelay(1);
941 + if (xm_read16(hw, port, XM_MMU_CMD)
942 + & XM_MMU_PHY_RDY)
943 + goto ready;
944 + }
945 +
946 + printk(KERN_WARNING PFX "%s: phy read timed out\n",
947 + hw->dev[port]->name);
948 + return 0;
949 + ready:
950 + v = xm_read16(hw, port, XM_PHY_DATA);
951 +
952 + return v;
953 +}
954 +
955 +static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
956 +{
957 + int i;
958 +
959 + xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
960 + for (i = 0; i < PHY_RETRIES; i++) {
961 + if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
962 + goto ready;
963 + udelay(1);
964 + }
965 + printk(KERN_WARNING PFX "%s: phy write failed to come ready\n",
966 + hw->dev[port]->name);
967 +
968 +
969 + ready:
970 + xm_write16(hw, port, XM_PHY_DATA, val);
971 + for (i = 0; i < PHY_RETRIES; i++) {
972 + udelay(1);
973 + if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
974 + return;
975 + }
976 + printk(KERN_WARNING PFX "%s: phy write timed out\n",
977 + hw->dev[port]->name);
978 +}
979 +
980 +static void genesis_init(struct skge_hw *hw)
981 +{
982 + /* set blink source counter */
983 + skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
984 + skge_write8(hw, B2_BSC_CTRL, BSC_START);
985 +
986 + /* configure mac arbiter */
987 + skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
988 +
989 + /* configure mac arbiter timeout values */
990 + skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
991 + skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
992 + skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
993 + skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
994 +
995 + skge_write8(hw, B3_MA_RCINI_RX1, 0);
996 + skge_write8(hw, B3_MA_RCINI_RX2, 0);
997 + skge_write8(hw, B3_MA_RCINI_TX1, 0);
998 + skge_write8(hw, B3_MA_RCINI_TX2, 0);
999 +
1000 + /* configure packet arbiter timeout */
1001 + skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1002 + skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1003 + skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1004 + skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1005 + skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1006 +}
1007 +
1008 +static void genesis_reset(struct skge_hw *hw, int port)
1009 +{
1010 + const u8 zero[8] = { 0 };
1011 +
1012 + /* reset the statistics module */
1013 + xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1014 + xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
1015 + xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1016 + xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1017 + xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1018 +
1019 + /* disable Broadcom PHY IRQ */
1020 + xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1021 +
1022 + xm_outhash(hw, port, XM_HSM, zero);
1023 +}
1024 +
1025 +
1026 +/* Convert mode to MII values */
1027 +static const u16 phy_pause_map[] = {
1028 + [FLOW_MODE_NONE] = 0,
1029 + [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1030 + [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1031 + [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1032 +};
1033 +
1034 +
1035 +/* Check status of Broadcom phy link */
1036 +static void bcom_check_link(struct skge_hw *hw, int port)
1037 +{
1038 + struct net_device *dev = hw->dev[port];
1039 + struct skge_port *skge = netdev_priv(dev);
1040 + u16 status;
1041 +
1042 + /* read twice because of latch */
1043 + (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
1044 + status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1045 +
1046 + pr_debug("bcom_check_link status=0x%x\n", status);
1047 +
1048 + if ((status & PHY_ST_LSYNC) == 0) {
1049 + u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
1050 + cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1051 + xm_write16(hw, port, XM_MMU_CMD, cmd);
1052 + /* dummy read to ensure writing */
1053 + (void) xm_read16(hw, port, XM_MMU_CMD);
1054 +
1055 + if (netif_carrier_ok(dev))
1056 + skge_link_down(skge);
1057 + } else {
1058 + if (skge->autoneg == AUTONEG_ENABLE &&
1059 + (status & PHY_ST_AN_OVER)) {
1060 + u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1061 + u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1062 +
1063 + if (lpa & PHY_B_AN_RF) {
1064 + printk(KERN_NOTICE PFX "%s: remote fault\n",
1065 + dev->name);
1066 + return;
1067 + }
1068 +
1069 + /* Check Duplex mismatch */
1070 + switch(aux & PHY_B_AS_AN_RES_MSK) {
1071 + case PHY_B_RES_1000FD:
1072 + skge->duplex = DUPLEX_FULL;
1073 + break;
1074 + case PHY_B_RES_1000HD:
1075 + skge->duplex = DUPLEX_HALF;
1076 + break;
1077 + default:
1078 + printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1079 + dev->name);
1080 + return;
1081 + }
1082 +
1083 +
1084 + /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1085 + switch (aux & PHY_B_AS_PAUSE_MSK) {
1086 + case PHY_B_AS_PAUSE_MSK:
1087 + skge->flow_control = FLOW_MODE_SYMMETRIC;
1088 + break;
1089 + case PHY_B_AS_PRR:
1090 + skge->flow_control = FLOW_MODE_REM_SEND;
1091 + break;
1092 + case PHY_B_AS_PRT:
1093 + skge->flow_control = FLOW_MODE_LOC_SEND;
1094 + break;
1095 + default:
1096 + skge->flow_control = FLOW_MODE_NONE;
1097 + }
1098 +
1099 + skge->speed = SPEED_1000;
1100 + }
1101 +
1102 + if (!netif_carrier_ok(dev))
1103 + genesis_link_up(skge);
1104 + }
1105 +}
1106 +
1107 +/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1108 + * Phy on for 100 or 10Mbit operation
1109 + */
1110 +static void bcom_phy_init(struct skge_port *skge, int jumbo)
1111 +{
1112 + struct skge_hw *hw = skge->hw;
1113 + int port = skge->port;
1114 + int i;
1115 + u16 id1, r, ext, ctl;
1116 +
1117 + /* magic workaround patterns for Broadcom */
1118 + static const struct {
1119 + u16 reg;
1120 + u16 val;
1121 + } A1hack[] = {
1122 + { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1123 + { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1124 + { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1125 + { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1126 + }, C0hack[] = {
1127 + { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1128 + { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1129 + };
1130 +
1131 + pr_debug("bcom_phy_init\n");
1132 +
1133 + /* read Id from external PHY (all have the same address) */
1134 + id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1135 +
1136 + /* Optimize MDIO transfer by suppressing preamble. */
1137 + r = xm_read16(hw, port, XM_MMU_CMD);
1138 + r |= XM_MMU_NO_PRE;
1139 + xm_write16(hw, port, XM_MMU_CMD,r);
1140 +
1141 + switch(id1) {
1142 + case PHY_BCOM_ID1_C0:
1143 + /*
1144 + * Workaround BCOM Errata for the C0 type.
1145 + * Write magic patterns to reserved registers.
1146 + */
1147 + for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1148 + xm_phy_write(hw, port,
1149 + C0hack[i].reg, C0hack[i].val);
1150 +
1151 + break;
1152 + case PHY_BCOM_ID1_A1:
1153 + /*
1154 + * Workaround BCOM Errata for the A1 type.
1155 + * Write magic patterns to reserved registers.
1156 + */
1157 + for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1158 + xm_phy_write(hw, port,
1159 + A1hack[i].reg, A1hack[i].val);
1160 + break;
1161 + }
1162 +
1163 + /*
1164 + * Workaround BCOM Errata (#10523) for all BCom PHYs.
1165 + * Disable Power Management after reset.
1166 + */
1167 + r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1168 + r |= PHY_B_AC_DIS_PM;
1169 + xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1170 +
1171 + /* Dummy read */
1172 + xm_read16(hw, port, XM_ISRC);
1173 +
1174 + ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1175 + ctl = PHY_CT_SP1000; /* always 1000mbit */
1176 +
1177 + if (skge->autoneg == AUTONEG_ENABLE) {
1178 + /*
1179 + * Workaround BCOM Errata #1 for the C5 type.
1180 + * 1000Base-T Link Acquisition Failure in Slave Mode
1181 + * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1182 + */
1183 + u16 adv = PHY_B_1000C_RD;
1184 + if (skge->advertising & ADVERTISED_1000baseT_Half)
1185 + adv |= PHY_B_1000C_AHD;
1186 + if (skge->advertising & ADVERTISED_1000baseT_Full)
1187 + adv |= PHY_B_1000C_AFD;
1188 + xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1189 +
1190 + ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1191 + } else {
1192 + if (skge->duplex == DUPLEX_FULL)
1193 + ctl |= PHY_CT_DUP_MD;
1194 + /* Force to slave */
1195 + xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1196 + }
1197 +
1198 + /* Set autonegotiation pause parameters */
1199 + xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1200 + phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1201 +
1202 + /* Handle Jumbo frames */
1203 + if (jumbo) {
1204 + xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1205 + PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1206 +
1207 + ext |= PHY_B_PEC_HIGH_LA;
1208 +
1209 + }
1210 +
1211 + xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1212 + xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1213 +
1214 + /* Use link status change interrrupt */
1215 + xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1216 +
1217 + bcom_check_link(hw, port);
1218 +}
1219 +
1220 +static void genesis_mac_init(struct skge_hw *hw, int port)
1221 +{
1222 + struct net_device *dev = hw->dev[port];
1223 + struct skge_port *skge = netdev_priv(dev);
1224 + int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1225 + int i;
1226 + u32 r;
1227 + const u8 zero[6] = { 0 };
1228 +
1229 + /* Clear MIB counters */
1230 + xm_write16(hw, port, XM_STAT_CMD,
1231 + XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1232 + /* Clear two times according to Errata #3 */
1233 + xm_write16(hw, port, XM_STAT_CMD,
1234 + XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1235 +
1236 + /* initialize Rx, Tx and Link LED */
1237 + skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
1238 + skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
1239 +
1240 + skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
1241 + skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
1242 +
1243 + /* Unreset the XMAC. */
1244 + skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1245 +
1246 + /*
1247 + * Perform additional initialization for external PHYs,
1248 + * namely for the 1000baseTX cards that use the XMAC's
1249 + * GMII mode.
1250 + */
1251 + spin_lock_bh(&hw->phy_lock);
1252 + /* Take external Phy out of reset */
1253 + r = skge_read32(hw, B2_GP_IO);
1254 + if (port == 0)
1255 + r |= GP_DIR_0|GP_IO_0;
1256 + else
1257 + r |= GP_DIR_2|GP_IO_2;
1258 +
1259 + skge_write32(hw, B2_GP_IO, r);
1260 + skge_read32(hw, B2_GP_IO);
1261 + spin_unlock_bh(&hw->phy_lock);
1262 +
1263 + /* Enable GMII interfac */
1264 + xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1265 +
1266 + bcom_phy_init(skge, jumbo);
1267 +
1268 + /* Set Station Address */
1269 + xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1270 +
1271 + /* We don't use match addresses so clear */
1272 + for (i = 1; i < 16; i++)
1273 + xm_outaddr(hw, port, XM_EXM(i), zero);
1274 +
1275 + /* configure Rx High Water Mark (XM_RX_HI_WM) */
1276 + xm_write16(hw, port, XM_RX_HI_WM, 1450);
1277 +
1278 + /* We don't need the FCS appended to the packet. */
1279 + r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1280 + if (jumbo)
1281 + r |= XM_RX_BIG_PK_OK;
1282 +
1283 + if (skge->duplex == DUPLEX_HALF) {
1284 + /*
1285 + * If in manual half duplex mode the other side might be in
1286 + * full duplex mode, so ignore if a carrier extension is not seen
1287 + * on frames received
1288 + */
1289 + r |= XM_RX_DIS_CEXT;
1290 + }
1291 + xm_write16(hw, port, XM_RX_CMD, r);
1292 +
1293 +
1294 + /* We want short frames padded to 60 bytes. */
1295 + xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1296 +
1297 + /*
1298 + * Bump up the transmit threshold. This helps hold off transmit
1299 + * underruns when we're blasting traffic from both ports at once.
1300 + */
1301 + xm_write16(hw, port, XM_TX_THR, 512);
1302 +
1303 + /*
1304 + * Enable the reception of all error frames. This is is
1305 + * a necessary evil due to the design of the XMAC. The
1306 + * XMAC's receive FIFO is only 8K in size, however jumbo
1307 + * frames can be up to 9000 bytes in length. When bad
1308 + * frame filtering is enabled, the XMAC's RX FIFO operates
1309 + * in 'store and forward' mode. For this to work, the
1310 + * entire frame has to fit into the FIFO, but that means
1311 + * that jumbo frames larger than 8192 bytes will be
1312 + * truncated. Disabling all bad frame filtering causes
1313 + * the RX FIFO to operate in streaming mode, in which
1314 + * case the XMAC will start transfering frames out of the
1315 + * RX FIFO as soon as the FIFO threshold is reached.
1316 + */
1317 + xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1318 +
1319 +
1320 + /*
1321 + * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1322 + * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1323 + * and 'Octets Rx OK Hi Cnt Ov'.
1324 + */
1325 + xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1326 +
1327 + /*
1328 + * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1329 + * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1330 + * and 'Octets Tx OK Hi Cnt Ov'.
1331 + */
1332 + xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1333 +
1334 + /* Configure MAC arbiter */
1335 + skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1336 +
1337 + /* configure timeout values */
1338 + skge_write8(hw, B3_MA_TOINI_RX1, 72);
1339 + skge_write8(hw, B3_MA_TOINI_RX2, 72);
1340 + skge_write8(hw, B3_MA_TOINI_TX1, 72);
1341 + skge_write8(hw, B3_MA_TOINI_TX2, 72);
1342 +
1343 + skge_write8(hw, B3_MA_RCINI_RX1, 0);
1344 + skge_write8(hw, B3_MA_RCINI_RX2, 0);
1345 + skge_write8(hw, B3_MA_RCINI_TX1, 0);
1346 + skge_write8(hw, B3_MA_RCINI_TX2, 0);
1347 +
1348 + /* Configure Rx MAC FIFO */
1349 + skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1350 + skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1351 + skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1352 +
1353 + /* Configure Tx MAC FIFO */
1354 + skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1355 + skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1356 + skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1357 +
1358 + if (jumbo) {
1359 + /* Enable frame flushing if jumbo frames used */
1360 + skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1361 + } else {
1362 + /* enable timeout timers if normal frames */
1363 + skge_write16(hw, B3_PA_CTRL,
1364 + (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1365 + }
1366 +}
1367 +
1368 +static void genesis_stop(struct skge_port *skge)
1369 +{
1370 + struct skge_hw *hw = skge->hw;
1371 + int port = skge->port;
1372 + u32 reg;
1373 +
1374 + /* Clear Tx packet arbiter timeout IRQ */
1375 + skge_write16(hw, B3_PA_CTRL,
1376 + port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1377 +
1378 + /*
1379 + * If the transfer stucks at the MAC the STOP command will not
1380 + * terminate if we don't flush the XMAC's transmit FIFO !
1381 + */
1382 + xm_write32(hw, port, XM_MODE,
1383 + xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1384 +
1385 +
1386 + /* Reset the MAC */
1387 + skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1388 +
1389 + /* For external PHYs there must be special handling */
1390 + reg = skge_read32(hw, B2_GP_IO);
1391 + if (port == 0) {
1392 + reg |= GP_DIR_0;
1393 + reg &= ~GP_IO_0;
1394 + } else {
1395 + reg |= GP_DIR_2;
1396 + reg &= ~GP_IO_2;
1397 + }
1398 + skge_write32(hw, B2_GP_IO, reg);
1399 + skge_read32(hw, B2_GP_IO);
1400 +
1401 + xm_write16(hw, port, XM_MMU_CMD,
1402 + xm_read16(hw, port, XM_MMU_CMD)
1403 + & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1404 +
1405 + xm_read16(hw, port, XM_MMU_CMD);
1406 +}
1407 +
1408 +
1409 +static void genesis_get_stats(struct skge_port *skge, u64 *data)
1410 +{
1411 + struct skge_hw *hw = skge->hw;
1412 + int port = skge->port;
1413 + int i;
1414 + unsigned long timeout = jiffies + HZ;
1415 +
1416 + xm_write16(hw, port,
1417 + XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1418 +
1419 + /* wait for update to complete */
1420 + while (xm_read16(hw, port, XM_STAT_CMD)
1421 + & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1422 + if (time_after(jiffies, timeout))
1423 + break;
1424 + udelay(10);
1425 + }
1426 +
1427 + /* special case for 64 bit octet counter */
1428 + data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1429 + | xm_read32(hw, port, XM_TXO_OK_LO);
1430 + data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1431 + | xm_read32(hw, port, XM_RXO_OK_LO);
1432 +
1433 + for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1434 + data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1435 +}
1436 +
1437 +static void genesis_mac_intr(struct skge_hw *hw, int port)
1438 +{
1439 + struct skge_port *skge = netdev_priv(hw->dev[port]);
1440 + u16 status = xm_read16(hw, port, XM_ISRC);
1441 +
1442 + if (netif_msg_intr(skge))
1443 + printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1444 + skge->netdev->name, status);
1445 +
1446 + if (status & XM_IS_TXF_UR) {
1447 + xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1448 + ++skge->net_stats.tx_fifo_errors;
1449 + }
1450 + if (status & XM_IS_RXF_OV) {
1451 + xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1452 + ++skge->net_stats.rx_fifo_errors;
1453 + }
1454 +}
1455 +
1456 +static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1457 +{
1458 + int i;
1459 +
1460 + gma_write16(hw, port, GM_SMI_DATA, val);
1461 + gma_write16(hw, port, GM_SMI_CTRL,
1462 + GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1463 + for (i = 0; i < PHY_RETRIES; i++) {
1464 + udelay(1);
1465 +
1466 + if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1467 + break;
1468 + }
1469 +}
1470 +
1471 +static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1472 +{
1473 + int i;
1474 +
1475 + gma_write16(hw, port, GM_SMI_CTRL,
1476 + GM_SMI_CT_PHY_AD(hw->phy_addr)
1477 + | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1478 +
1479 + for (i = 0; i < PHY_RETRIES; i++) {
1480 + udelay(1);
1481 + if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1482 + goto ready;
1483 + }
1484 +
1485 + printk(KERN_WARNING PFX "%s: phy read timeout\n",
1486 + hw->dev[port]->name);
1487 + return 0;
1488 + ready:
1489 + return gma_read16(hw, port, GM_SMI_DATA);
1490 +}
1491 +
1492 +static void genesis_link_up(struct skge_port *skge)
1493 +{
1494 + struct skge_hw *hw = skge->hw;
1495 + int port = skge->port;
1496 + u16 cmd;
1497 + u32 mode, msk;
1498 +
1499 + pr_debug("genesis_link_up\n");
1500 + cmd = xm_read16(hw, port, XM_MMU_CMD);
1501 +
1502 + /*
1503 + * enabling pause frame reception is required for 1000BT
1504 + * because the XMAC is not reset if the link is going down
1505 + */
1506 + if (skge->flow_control == FLOW_MODE_NONE ||
1507 + skge->flow_control == FLOW_MODE_LOC_SEND)
1508 + /* Disable Pause Frame Reception */
1509 + cmd |= XM_MMU_IGN_PF;
1510 + else
1511 + /* Enable Pause Frame Reception */
1512 + cmd &= ~XM_MMU_IGN_PF;
1513 +
1514 + xm_write16(hw, port, XM_MMU_CMD, cmd);
1515 +
1516 + mode = xm_read32(hw, port, XM_MODE);
1517 + if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1518 + skge->flow_control == FLOW_MODE_LOC_SEND) {
1519 + /*
1520 + * Configure Pause Frame Generation
1521 + * Use internal and external Pause Frame Generation.
1522 + * Sending pause frames is edge triggered.
1523 + * Send a Pause frame with the maximum pause time if
1524 + * internal oder external FIFO full condition occurs.
1525 + * Send a zero pause time frame to re-start transmission.
1526 + */
1527 + /* XM_PAUSE_DA = '010000C28001' (default) */
1528 + /* XM_MAC_PTIME = 0xffff (maximum) */
1529 + /* remember this value is defined in big endian (!) */
1530 + xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1531 +
1532 + mode |= XM_PAUSE_MODE;
1533 + skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1534 + } else {
1535 + /*
1536 + * disable pause frame generation is required for 1000BT
1537 + * because the XMAC is not reset if the link is going down
1538 + */
1539 + /* Disable Pause Mode in Mode Register */
1540 + mode &= ~XM_PAUSE_MODE;
1541 +
1542 + skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1543 + }
1544 +
1545 + xm_write32(hw, port, XM_MODE, mode);
1546 +
1547 + msk = XM_DEF_MSK;
1548 + /* disable GP0 interrupt bit for external Phy */
1549 + msk |= XM_IS_INP_ASS;
1550 +
1551 + xm_write16(hw, port, XM_IMSK, msk);
1552 + xm_read16(hw, port, XM_ISRC);
1553 +
1554 + /* get MMU Command Reg. */
1555 + cmd = xm_read16(hw, port, XM_MMU_CMD);
1556 + if (skge->duplex == DUPLEX_FULL)
1557 + cmd |= XM_MMU_GMII_FD;
1558 +
1559 + /*
1560 + * Workaround BCOM Errata (#10523) for all BCom Phys
1561 + * Enable Power Management after link up
1562 + */
1563 + xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1564 + xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1565 + & ~PHY_B_AC_DIS_PM);
1566 + xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1567 +
1568 + /* enable Rx/Tx */
1569 + xm_write16(hw, port, XM_MMU_CMD,
1570 + cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1571 + skge_link_up(skge);
1572 +}
1573 +
1574 +
1575 +static inline void bcom_phy_intr(struct skge_port *skge)
1576 +{
1577 + struct skge_hw *hw = skge->hw;
1578 + int port = skge->port;
1579 + u16 isrc;
1580 +
1581 + isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1582 + if (netif_msg_intr(skge))
1583 + printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1584 + skge->netdev->name, isrc);
1585 +
1586 + if (isrc & PHY_B_IS_PSE)
1587 + printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1588 + hw->dev[port]->name);
1589 +
1590 + /* Workaround BCom Errata:
1591 + * enable and disable loopback mode if "NO HCD" occurs.
1592 + */
1593 + if (isrc & PHY_B_IS_NO_HDCL) {
1594 + u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1595 + xm_phy_write(hw, port, PHY_BCOM_CTRL,
1596 + ctrl | PHY_CT_LOOP);
1597 + xm_phy_write(hw, port, PHY_BCOM_CTRL,
1598 + ctrl & ~PHY_CT_LOOP);
1599 + }
1600 +
1601 + if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1602 + bcom_check_link(hw, port);
1603 +
1604 +}
1605 +
1606 +/* Marvell Phy Initailization */
1607 +static void yukon_init(struct skge_hw *hw, int port)
1608 +{
1609 + struct skge_port *skge = netdev_priv(hw->dev[port]);
1610 + u16 ctrl, ct1000, adv;
1611 + u16 ledctrl, ledover;
1612 +
1613 + pr_debug("yukon_init\n");
1614 + if (skge->autoneg == AUTONEG_ENABLE) {
1615 + u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1616 +
1617 + ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1618 + PHY_M_EC_MAC_S_MSK);
1619 + ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1620 +
1621 + ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1622 +
1623 + gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1624 + }
1625 +
1626 + ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1627 + if (skge->autoneg == AUTONEG_DISABLE)
1628 + ctrl &= ~PHY_CT_ANE;
1629 +
1630 + ctrl |= PHY_CT_RESET;
1631 + gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1632 +
1633 + ctrl = 0;
1634 + ct1000 = 0;
1635 + adv = PHY_AN_CSMA;
1636 +
1637 + if (skge->autoneg == AUTONEG_ENABLE) {
1638 + if (iscopper(hw)) {
1639 + if (skge->advertising & ADVERTISED_1000baseT_Full)
1640 + ct1000 |= PHY_M_1000C_AFD;
1641 + if (skge->advertising & ADVERTISED_1000baseT_Half)
1642 + ct1000 |= PHY_M_1000C_AHD;
1643 + if (skge->advertising & ADVERTISED_100baseT_Full)
1644 + adv |= PHY_M_AN_100_FD;
1645 + if (skge->advertising & ADVERTISED_100baseT_Half)
1646 + adv |= PHY_M_AN_100_HD;
1647 + if (skge->advertising & ADVERTISED_10baseT_Full)
1648 + adv |= PHY_M_AN_10_FD;
1649 + if (skge->advertising & ADVERTISED_10baseT_Half)
1650 + adv |= PHY_M_AN_10_HD;
1651 + } else /* special defines for FIBER (88E1011S only) */
1652 + adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1653 +
1654 + /* Set Flow-control capabilities */
1655 + adv |= phy_pause_map[skge->flow_control];
1656 +
1657 + /* Restart Auto-negotiation */
1658 + ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1659 + } else {
1660 + /* forced speed/duplex settings */
1661 + ct1000 = PHY_M_1000C_MSE;
1662 +
1663 + if (skge->duplex == DUPLEX_FULL)
1664 + ctrl |= PHY_CT_DUP_MD;
1665 +
1666 + switch (skge->speed) {
1667 + case SPEED_1000:
1668 + ctrl |= PHY_CT_SP1000;
1669 + break;
1670 + case SPEED_100:
1671 + ctrl |= PHY_CT_SP100;
1672 + break;
1673 + }
1674 +
1675 + ctrl |= PHY_CT_RESET;
1676 + }
1677 +
1678 + gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1679 +
1680 + gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1681 + gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1682 +
1683 + /* Setup Phy LED's */
1684 + ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
1685 + ledover = 0;
1686 +
1687 + ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
1688 +
1689 + /* turn off the Rx LED (LED_RX) */
1690 + ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
1691 +
1692 + /* disable blink mode (LED_DUPLEX) on collisions */
1693 + ctrl |= PHY_M_LEDC_DP_CTRL;
1694 + gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
1695 +
1696 + if (skge->autoneg == AUTONEG_DISABLE || skge->speed == SPEED_100) {
1697 + /* turn on 100 Mbps LED (LED_LINK100) */
1698 + ledover |= PHY_M_LED_MO_100(MO_LED_ON);
1699 + }
1700 +
1701 + if (ledover)
1702 + gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
1703 +
1704 + /* Enable phy interrupt on autonegotiation complete (or link up) */
1705 + if (skge->autoneg == AUTONEG_ENABLE)
1706 + gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
1707 + else
1708 + gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1709 +}
1710 +
1711 +static void yukon_reset(struct skge_hw *hw, int port)
1712 +{
1713 + gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1714 + gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1715 + gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1716 + gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1717 + gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1718 +
1719 + gma_write16(hw, port, GM_RX_CTRL,
1720 + gma_read16(hw, port, GM_RX_CTRL)
1721 + | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1722 +}
1723 +
1724 +static void yukon_mac_init(struct skge_hw *hw, int port)
1725 +{
1726 + struct skge_port *skge = netdev_priv(hw->dev[port]);
1727 + int i;
1728 + u32 reg;
1729 + const u8 *addr = hw->dev[port]->dev_addr;
1730 +
1731 + /* WA code for COMA mode -- set PHY reset */
1732 + if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1733 + hw->chip_rev >= CHIP_REV_YU_LITE_A3)
1734 + skge_write32(hw, B2_GP_IO,
1735 + (skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9));
1736 +
1737 + /* hard reset */
1738 + skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1739 + skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1740 +
1741 + /* WA code for COMA mode -- clear PHY reset */
1742 + if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1743 + hw->chip_rev >= CHIP_REV_YU_LITE_A3)
1744 + skge_write32(hw, B2_GP_IO,
1745 + (skge_read32(hw, B2_GP_IO) | GP_DIR_9)
1746 + & ~GP_IO_9);
1747 +
1748 + /* Set hardware config mode */
1749 + reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1750 + GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1751 + reg |= iscopper(hw) ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1752 +
1753 + /* Clear GMC reset */
1754 + skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1755 + skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1756 + skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
1757 + if (skge->autoneg == AUTONEG_DISABLE) {
1758 + reg = GM_GPCR_AU_ALL_DIS;
1759 + gma_write16(hw, port, GM_GP_CTRL,
1760 + gma_read16(hw, port, GM_GP_CTRL) | reg);
1761 +
1762 + switch (skge->speed) {
1763 + case SPEED_1000:
1764 + reg |= GM_GPCR_SPEED_1000;
1765 + /* fallthru */
1766 + case SPEED_100:
1767 + reg |= GM_GPCR_SPEED_100;
1768 + }
1769 +
1770 + if (skge->duplex == DUPLEX_FULL)
1771 + reg |= GM_GPCR_DUP_FULL;
1772 + } else
1773 + reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1774 + switch (skge->flow_control) {
1775 + case FLOW_MODE_NONE:
1776 + skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1777 + reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1778 + break;
1779 + case FLOW_MODE_LOC_SEND:
1780 + /* disable Rx flow-control */
1781 + reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1782 + }
1783 +
1784 + gma_write16(hw, port, GM_GP_CTRL, reg);
1785 + skge_read16(hw, GMAC_IRQ_SRC);
1786 +
1787 + spin_lock_bh(&hw->phy_lock);
1788 + yukon_init(hw, port);
1789 + spin_unlock_bh(&hw->phy_lock);
1790 +
1791 + /* MIB clear */
1792 + reg = gma_read16(hw, port, GM_PHY_ADDR);
1793 + gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
1794 +
1795 + for (i = 0; i < GM_MIB_CNT_SIZE; i++)
1796 + gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1797 + gma_write16(hw, port, GM_PHY_ADDR, reg);
1798 +
1799 + /* transmit control */
1800 + gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
1801 +
1802 + /* receive control reg: unicast + multicast + no FCS */
1803 + gma_write16(hw, port, GM_RX_CTRL,
1804 + GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1805 +
1806 + /* transmit flow control */
1807 + gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
1808 +
1809 + /* transmit parameter */
1810 + gma_write16(hw, port, GM_TX_PARAM,
1811 + TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1812 + TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1813 + TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1814 +
1815 + /* serial mode register */
1816 + reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1817 + if (hw->dev[port]->mtu > 1500)
1818 + reg |= GM_SMOD_JUMBO_ENA;
1819 +
1820 + gma_write16(hw, port, GM_SERIAL_MODE, reg);
1821 +
1822 + /* physical address: used for pause frames */
1823 + gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
1824 + /* virtual address for data */
1825 + gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
1826 +
1827 + /* enable interrupt mask for counter overflows */
1828 + gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1829 + gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1830 + gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
1831 +
1832 + /* Initialize Mac Fifo */
1833 +
1834 + /* Configure Rx MAC FIFO */
1835 + skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
1836 + reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1837 + if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1838 + hw->chip_rev >= CHIP_REV_YU_LITE_A3)
1839 + reg &= ~GMF_RX_F_FL_ON;
1840 + skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1841 + skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1842 + skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
1843 +
1844 + /* Configure Tx MAC FIFO */
1845 + skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1846 + skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1847 +}
1848 +
1849 +static void yukon_stop(struct skge_port *skge)
1850 +{
1851 + struct skge_hw *hw = skge->hw;
1852 + int port = skge->port;
1853 +
1854 + if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1855 + hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1856 + skge_write32(hw, B2_GP_IO,
1857 + skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9);
1858 + }
1859 +
1860 + gma_write16(hw, port, GM_GP_CTRL,
1861 + gma_read16(hw, port, GM_GP_CTRL)
1862 + & ~(GM_GPCR_RX_ENA|GM_GPCR_RX_ENA));
1863 + gma_read16(hw, port, GM_GP_CTRL);
1864 +
1865 + /* set GPHY Control reset */
1866 + gma_write32(hw, port, GPHY_CTRL, GPC_RST_SET);
1867 + gma_write32(hw, port, GMAC_CTRL, GMC_RST_SET);
1868 +}
1869 +
1870 +static void yukon_get_stats(struct skge_port *skge, u64 *data)
1871 +{
1872 + struct skge_hw *hw = skge->hw;
1873 + int port = skge->port;
1874 + int i;
1875 +
1876 + data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1877 + | gma_read32(hw, port, GM_TXO_OK_LO);
1878 + data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1879 + | gma_read32(hw, port, GM_RXO_OK_LO);
1880 +
1881 + for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1882 + data[i] = gma_read32(hw, port,
1883 + skge_stats[i].gma_offset);
1884 +}
1885 +
1886 +static void yukon_mac_intr(struct skge_hw *hw, int port)
1887 +{
1888 + struct net_device *dev = hw->dev[port];
1889 + struct skge_port *skge = netdev_priv(dev);
1890 + u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1891 +
1892 + if (netif_msg_intr(skge))
1893 + printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1894 + dev->name, status);
1895 +
1896 + if (status & GM_IS_RX_FF_OR) {
1897 + ++skge->net_stats.rx_fifo_errors;
1898 + gma_write8(hw, port, RX_GMF_CTRL_T, GMF_CLI_RX_FO);
1899 + }
1900 + if (status & GM_IS_TX_FF_UR) {
1901 + ++skge->net_stats.tx_fifo_errors;
1902 + gma_write8(hw, port, TX_GMF_CTRL_T, GMF_CLI_TX_FU);
1903 + }
1904 +
1905 +}
1906 +
1907 +static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1908 +{
1909 + switch (aux & PHY_M_PS_SPEED_MSK) {
1910 + case PHY_M_PS_SPEED_1000:
1911 + return SPEED_1000;
1912 + case PHY_M_PS_SPEED_100:
1913 + return SPEED_100;
1914 + default:
1915 + return SPEED_10;
1916 + }
1917 +}
1918 +
1919 +static void yukon_link_up(struct skge_port *skge)
1920 +{
1921 + struct skge_hw *hw = skge->hw;
1922 + int port = skge->port;
1923 + u16 reg;
1924 +
1925 + pr_debug("yukon_link_up\n");
1926 +
1927 + /* Enable Transmit FIFO Underrun */
1928 + skge_write8(hw, GMAC_IRQ_MSK, GMAC_DEF_MSK);
1929 +
1930 + reg = gma_read16(hw, port, GM_GP_CTRL);
1931 + if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1932 + reg |= GM_GPCR_DUP_FULL;
1933 +
1934 + /* enable Rx/Tx */
1935 + reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1936 + gma_write16(hw, port, GM_GP_CTRL, reg);
1937 +
1938 + gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1939 + skge_link_up(skge);
1940 +}
1941 +
1942 +static void yukon_link_down(struct skge_port *skge)
1943 +{
1944 + struct skge_hw *hw = skge->hw;
1945 + int port = skge->port;
1946 +
1947 + pr_debug("yukon_link_down\n");
1948 + gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1949 + gm_phy_write(hw, port, GM_GP_CTRL,
1950 + gm_phy_read(hw, port, GM_GP_CTRL)
1951 + & ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA));
1952 +
1953 + if (skge->flow_control == FLOW_MODE_REM_SEND) {
1954 + /* restore Asymmetric Pause bit */
1955 + gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1956 + gm_phy_read(hw, port,
1957 + PHY_MARV_AUNE_ADV)
1958 + | PHY_M_AN_ASP);
1959 +
1960 + }
1961 +
1962 + yukon_reset(hw, port);
1963 + skge_link_down(skge);
1964 +
1965 + yukon_init(hw, port);
1966 +}
1967 +
1968 +static void yukon_phy_intr(struct skge_port *skge)
1969 +{
1970 + struct skge_hw *hw = skge->hw;
1971 + int port = skge->port;
1972 + const char *reason = NULL;
1973 + u16 istatus, phystat;
1974 +
1975 + istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1976 + phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1977 +
1978 + if (netif_msg_intr(skge))
1979 + printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1980 + skge->netdev->name, istatus, phystat);
1981 +
1982 + if (istatus & PHY_M_IS_AN_COMPL) {
1983 + if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
1984 + & PHY_M_AN_RF) {
1985 + reason = "remote fault";
1986 + goto failed;
1987 + }
1988 +
1989 + if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1990 + reason = "master/slave fault";
1991 + goto failed;
1992 + }
1993 +
1994 + if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1995 + reason = "speed/duplex";
1996 + goto failed;
1997 + }
1998 +
1999 + skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2000 + ? DUPLEX_FULL : DUPLEX_HALF;
2001 + skge->speed = yukon_speed(hw, phystat);
2002 +
2003 + /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2004 + switch (phystat & PHY_M_PS_PAUSE_MSK) {
2005 + case PHY_M_PS_PAUSE_MSK:
2006 + skge->flow_control = FLOW_MODE_SYMMETRIC;
2007 + break;
2008 + case PHY_M_PS_RX_P_EN:
2009 + skge->flow_control = FLOW_MODE_REM_SEND;
2010 + break;
2011 + case PHY_M_PS_TX_P_EN:
2012 + skge->flow_control = FLOW_MODE_LOC_SEND;
2013 + break;
2014 + default:
2015 + skge->flow_control = FLOW_MODE_NONE;
2016 + }
2017 +
2018 + if (skge->flow_control == FLOW_MODE_NONE ||
2019 + (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2020 + skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2021 + else
2022 + skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2023 + yukon_link_up(skge);
2024 + return;
2025 + }
2026 +
2027 + if (istatus & PHY_M_IS_LSP_CHANGE)
2028 + skge->speed = yukon_speed(hw, phystat);
2029 +
2030 + if (istatus & PHY_M_IS_DUP_CHANGE)
2031 + skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2032 + if (istatus & PHY_M_IS_LST_CHANGE) {
2033 + if (phystat & PHY_M_PS_LINK_UP)
2034 + yukon_link_up(skge);
2035 + else
2036 + yukon_link_down(skge);
2037 + }
2038 + return;
2039 + failed:
2040 + printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2041 + skge->netdev->name, reason);
2042 +
2043 + /* XXX restart autonegotiation? */
2044 +}
2045 +
2046 +static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2047 +{
2048 + u32 end;
2049 +
2050 + start /= 8;
2051 + len /= 8;
2052 + end = start + len - 1;
2053 +
2054 + skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2055 + skge_write32(hw, RB_ADDR(q, RB_START), start);
2056 + skge_write32(hw, RB_ADDR(q, RB_WP), start);
2057 + skge_write32(hw, RB_ADDR(q, RB_RP), start);
2058 + skge_write32(hw, RB_ADDR(q, RB_END), end);
2059 +
2060 + if (q == Q_R1 || q == Q_R2) {
2061 + /* Set thresholds on receive queue's */
2062 + skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2063 + start + (2*len)/3);
2064 + skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2065 + start + (len/3));
2066 + } else {
2067 + /* Enable store & forward on Tx queue's because
2068 + * Tx FIFO is only 4K on Genesis and 1K on Yukon
2069 + */
2070 + skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2071 + }
2072 +
2073 + skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2074 +}
2075 +
2076 +/* Setup Bus Memory Interface */
2077 +static void skge_qset(struct skge_port *skge, u16 q,
2078 + const struct skge_element *e)
2079 +{
2080 + struct skge_hw *hw = skge->hw;
2081 + u32 watermark = 0x600;
2082 + u64 base = skge->dma + (e->desc - skge->mem);
2083 +
2084 + /* optimization to reduce window on 32bit/33mhz */
2085 + if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2086 + watermark /= 2;
2087 +
2088 + skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2089 + skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2090 + skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2091 + skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2092 +}
2093 +
2094 +static int skge_up(struct net_device *dev)
2095 +{
2096 + struct skge_port *skge = netdev_priv(dev);
2097 + struct skge_hw *hw = skge->hw;
2098 + int port = skge->port;
2099 + u32 chunk, ram_addr;
2100 + size_t rx_size, tx_size;
2101 + int err;
2102 +
2103 + if (netif_msg_ifup(skge))
2104 + printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2105 +
2106 + if (dev->mtu > RX_BUF_SIZE)
2107 + skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;
2108 + else
2109 + skge->rx_buf_size = RX_BUF_SIZE;
2110 +
2111 +
2112 + rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2113 + tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2114 + skge->mem_size = tx_size + rx_size;
2115 + skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2116 + if (!skge->mem)
2117 + return -ENOMEM;
2118 +
2119 + memset(skge->mem, 0, skge->mem_size);
2120 +
2121 + if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2122 + goto free_pci_mem;
2123 +
2124 + err = skge_rx_fill(skge);
2125 + if (err)
2126 + goto free_rx_ring;
2127 +
2128 + if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2129 + skge->dma + rx_size)))
2130 + goto free_rx_ring;
2131 +
2132 + skge->tx_avail = skge->tx_ring.count - 1;
2133 +
2134 + /* Enable IRQ from port */
2135 + hw->intr_mask |= portirqmask[port];
2136 + skge_write32(hw, B0_IMSK, hw->intr_mask);
2137 +
2138 + /* Initialze MAC */
2139 + if (hw->chip_id == CHIP_ID_GENESIS)
2140 + genesis_mac_init(hw, port);
2141 + else
2142 + yukon_mac_init(hw, port);
2143 +
2144 + /* Configure RAMbuffers */
2145 + chunk = hw->ram_size / ((hw->ports + 1)*2);
2146 + ram_addr = hw->ram_offset + 2 * chunk * port;
2147 +
2148 + skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2149 + skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2150 +
2151 + BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2152 + skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2153 + skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2154 +
2155 + /* Start receiver BMU */
2156 + wmb();
2157 + skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2158 +
2159 + pr_debug("skge_up completed\n");
2160 + return 0;
2161 +
2162 + free_rx_ring:
2163 + skge_rx_clean(skge);
2164 + kfree(skge->rx_ring.start);
2165 + free_pci_mem:
2166 + pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2167 +
2168 + return err;
2169 +}
2170 +
2171 +static int skge_down(struct net_device *dev)
2172 +{
2173 + struct skge_port *skge = netdev_priv(dev);
2174 + struct skge_hw *hw = skge->hw;
2175 + int port = skge->port;
2176 +
2177 + if (netif_msg_ifdown(skge))
2178 + printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2179 +
2180 + netif_stop_queue(dev);
2181 +
2182 + del_timer_sync(&skge->led_blink);
2183 +
2184 + /* Stop transmitter */
2185 + skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2186 + skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2187 + RB_RST_SET|RB_DIS_OP_MD);
2188 +
2189 + if (hw->chip_id == CHIP_ID_GENESIS)
2190 + genesis_stop(skge);
2191 + else
2192 + yukon_stop(skge);
2193 +
2194 + /* Disable Force Sync bit and Enable Alloc bit */
2195 + skge_write8(hw, SK_REG(port, TXA_CTRL),
2196 + TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2197 +
2198 + /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2199 + skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2200 + skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2201 +
2202 + /* Reset PCI FIFO */
2203 + skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2204 + skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2205 +
2206 + /* Reset the RAM Buffer async Tx queue */
2207 + skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2208 + /* stop receiver */
2209 + skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2210 + skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2211 + RB_RST_SET|RB_DIS_OP_MD);
2212 + skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2213 +
2214 + if (hw->chip_id == CHIP_ID_GENESIS) {
2215 + skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2216 + skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2217 + skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_STOP);
2218 + skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_STOP);
2219 + } else {
2220 + skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2221 + skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2222 + }
2223 +
2224 + /* turn off led's */
2225 + skge_write16(hw, B0_LED, LED_STAT_OFF);
2226 +
2227 + skge_tx_clean(skge);
2228 + skge_rx_clean(skge);
2229 +
2230 + kfree(skge->rx_ring.start);
2231 + kfree(skge->tx_ring.start);
2232 + pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2233 + return 0;
2234 +}
2235 +
2236 +static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2237 +{
2238 + struct skge_port *skge = netdev_priv(dev);
2239 + struct skge_hw *hw = skge->hw;
2240 + struct skge_ring *ring = &skge->tx_ring;
2241 + struct skge_element *e;
2242 + struct skge_tx_desc *td;
2243 + int i;
2244 + u32 control, len;
2245 + u64 map;
2246 + unsigned long flags;
2247 +
2248 + skb = skb_padto(skb, ETH_ZLEN);
2249 + if (!skb)
2250 + return NETDEV_TX_OK;
2251 +
2252 + local_irq_save(flags);
2253 + if (!spin_trylock(&skge->tx_lock)) {
2254 + /* Collision - tell upper layer to requeue */
2255 + local_irq_restore(flags);
2256 + return NETDEV_TX_LOCKED;
2257 + }
2258 +
2259 + if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
2260 + netif_stop_queue(dev);
2261 + spin_unlock_irqrestore(&skge->tx_lock, flags);
2262 +
2263 + printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2264 + dev->name);
2265 + return NETDEV_TX_BUSY;
2266 + }
2267 +
2268 + e = ring->to_use;
2269 + td = e->desc;
2270 + e->skb = skb;
2271 + len = skb_headlen(skb);
2272 + map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2273 + pci_unmap_addr_set(e, mapaddr, map);
2274 + pci_unmap_len_set(e, maplen, len);
2275 +
2276 + td->dma_lo = map;
2277 + td->dma_hi = map >> 32;
2278 +
2279 + if (skb->ip_summed == CHECKSUM_HW) {
2280 + const struct iphdr *ip
2281 + = (const struct iphdr *) (skb->data + ETH_HLEN);
2282 + int offset = skb->h.raw - skb->data;
2283 +
2284 + /* This seems backwards, but it is what the sk98lin
2285 + * does. Looks like hardware is wrong?
2286 + */
2287 + if (ip->protocol == IPPROTO_UDP
2288 + && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2289 + control = BMU_TCP_CHECK;
2290 + else
2291 + control = BMU_UDP_CHECK;
2292 +
2293 + td->csum_offs = 0;
2294 + td->csum_start = offset;
2295 + td->csum_write = offset + skb->csum;
2296 + } else
2297 + control = BMU_CHECK;
2298 +
2299 + if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2300 + control |= BMU_EOF| BMU_IRQ_EOF;
2301 + else {
2302 + struct skge_tx_desc *tf = td;
2303 +
2304 + control |= BMU_STFWD;
2305 + for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2306 + skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2307 +
2308 + map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2309 + frag->size, PCI_DMA_TODEVICE);
2310 +
2311 + e = e->next;
2312 + e->skb = NULL;
2313 + tf = e->desc;
2314 + tf->dma_lo = map;
2315 + tf->dma_hi = (u64) map >> 32;
2316 + pci_unmap_addr_set(e, mapaddr, map);
2317 + pci_unmap_len_set(e, maplen, frag->size);
2318 +
2319 + tf->control = BMU_OWN | BMU_SW | control | frag->size;
2320 + }
2321 + tf->control |= BMU_EOF | BMU_IRQ_EOF;
2322 + }
2323 + /* Make sure all the descriptors written */
2324 + wmb();
2325 + td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2326 + wmb();
2327 +
2328 + skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2329 +
2330 + if (netif_msg_tx_queued(skge))
2331 + printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2332 + dev->name, e - ring->start, skb->len);
2333 +
2334 + ring->to_use = e->next;
2335 + skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2336 + if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2337 + pr_debug("%s: transmit queue full\n", dev->name);
2338 + netif_stop_queue(dev);
2339 + }
2340 +
2341 + dev->trans_start = jiffies;
2342 + spin_unlock_irqrestore(&skge->tx_lock, flags);
2343 +
2344 + return NETDEV_TX_OK;
2345 +}
2346 +
2347 +static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2348 +{
2349 + /* This ring element can be skb or fragment */
2350 + if (e->skb) {
2351 + pci_unmap_single(hw->pdev,
2352 + pci_unmap_addr(e, mapaddr),
2353 + pci_unmap_len(e, maplen),
2354 + PCI_DMA_TODEVICE);
2355 + dev_kfree_skb_any(e->skb);
2356 + e->skb = NULL;
2357 + } else {
2358 + pci_unmap_page(hw->pdev,
2359 + pci_unmap_addr(e, mapaddr),
2360 + pci_unmap_len(e, maplen),
2361 + PCI_DMA_TODEVICE);
2362 + }
2363 +}
2364 +
2365 +static void skge_tx_clean(struct skge_port *skge)
2366 +{
2367 + struct skge_ring *ring = &skge->tx_ring;
2368 + struct skge_element *e;
2369 + unsigned long flags;
2370 +
2371 + spin_lock_irqsave(&skge->tx_lock, flags);
2372 + for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2373 + ++skge->tx_avail;
2374 + skge_tx_free(skge->hw, e);
2375 + }
2376 + ring->to_clean = e;
2377 + spin_unlock_irqrestore(&skge->tx_lock, flags);
2378 +}
2379 +
2380 +static void skge_tx_timeout(struct net_device *dev)
2381 +{
2382 + struct skge_port *skge = netdev_priv(dev);
2383 +
2384 + if (netif_msg_timer(skge))
2385 + printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2386 +
2387 + skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2388 + skge_tx_clean(skge);
2389 +}
2390 +
2391 +static int skge_change_mtu(struct net_device *dev, int new_mtu)
2392 +{
2393 + int err = 0;
2394 + int running = netif_running(dev);
2395 +
2396 + if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2397 + return -EINVAL;
2398 +
2399 +
2400 + if (running)
2401 + skge_down(dev);
2402 + dev->mtu = new_mtu;
2403 + if (running)
2404 + skge_up(dev);
2405 +
2406 + return err;
2407 +}
2408 +
2409 +static void genesis_set_multicast(struct net_device *dev)
2410 +{
2411 + struct skge_port *skge = netdev_priv(dev);
2412 + struct skge_hw *hw = skge->hw;
2413 + int port = skge->port;
2414 + int i, count = dev->mc_count;
2415 + struct dev_mc_list *list = dev->mc_list;
2416 + u32 mode;
2417 + u8 filter[8];
2418 +
2419 + pr_debug("genesis_set_multicast flags=%x count=%d\n", dev->flags, dev->mc_count);
2420 +
2421 + mode = xm_read32(hw, port, XM_MODE);
2422 + mode |= XM_MD_ENA_HASH;
2423 + if (dev->flags & IFF_PROMISC)
2424 + mode |= XM_MD_ENA_PROM;
2425 + else
2426 + mode &= ~XM_MD_ENA_PROM;
2427 +
2428 + if (dev->flags & IFF_ALLMULTI)
2429 + memset(filter, 0xff, sizeof(filter));
2430 + else {
2431 + memset(filter, 0, sizeof(filter));
2432 + for (i = 0; list && i < count; i++, list = list->next) {
2433 + u32 crc, bit;
2434 + crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2435 + bit = ~crc & 0x3f;
2436 + filter[bit/8] |= 1 << (bit%8);
2437 + }
2438 + }
2439 +
2440 + xm_write32(hw, port, XM_MODE, mode);
2441 + xm_outhash(hw, port, XM_HSM, filter);
2442 +}
2443 +
2444 +static void yukon_set_multicast(struct net_device *dev)
2445 +{
2446 + struct skge_port *skge = netdev_priv(dev);
2447 + struct skge_hw *hw = skge->hw;
2448 + int port = skge->port;
2449 + struct dev_mc_list *list = dev->mc_list;
2450 + u16 reg;
2451 + u8 filter[8];
2452 +
2453 + memset(filter, 0, sizeof(filter));
2454 +
2455 + reg = gma_read16(hw, port, GM_RX_CTRL);
2456 + reg |= GM_RXCR_UCF_ENA;
2457 +
2458 + if (dev->flags & IFF_PROMISC) /* promiscious */
2459 + reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2460 + else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2461 + memset(filter, 0xff, sizeof(filter));
2462 + else if (dev->mc_count == 0) /* no multicast */
2463 + reg &= ~GM_RXCR_MCF_ENA;
2464 + else {
2465 + int i;
2466 + reg |= GM_RXCR_MCF_ENA;
2467 +
2468 + for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2469 + u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2470 + filter[bit/8] |= 1 << (bit%8);
2471 + }
2472 + }
2473 +
2474 +
2475 + gma_write16(hw, port, GM_MC_ADDR_H1,
2476 + (u16)filter[0] | ((u16)filter[1] << 8));
2477 + gma_write16(hw, port, GM_MC_ADDR_H2,
2478 + (u16)filter[2] | ((u16)filter[3] << 8));
2479 + gma_write16(hw, port, GM_MC_ADDR_H3,
2480 + (u16)filter[4] | ((u16)filter[5] << 8));
2481 + gma_write16(hw, port, GM_MC_ADDR_H4,
2482 + (u16)filter[6] | ((u16)filter[7] << 8));
2483 +
2484 + gma_write16(hw, port, GM_RX_CTRL, reg);
2485 +}
2486 +
2487 +static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2488 +{
2489 + if (hw->chip_id == CHIP_ID_GENESIS)
2490 + return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2491 + else
2492 + return (status & GMR_FS_ANY_ERR) ||
2493 + (status & GMR_FS_RX_OK) == 0;
2494 +}
2495 +
2496 +static void skge_rx_error(struct skge_port *skge, int slot,
2497 + u32 control, u32 status)
2498 +{
2499 + if (netif_msg_rx_err(skge))
2500 + printk(KERN_DEBUG PFX "%s: rx err, slot %d control 0x%x status 0x%x\n",
2501 + skge->netdev->name, slot, control, status);
2502 +
2503 + if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2504 + skge->net_stats.rx_length_errors++;
2505 + else if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2506 + if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2507 + skge->net_stats.rx_length_errors++;
2508 + if (status & XMR_FS_FRA_ERR)
2509 + skge->net_stats.rx_frame_errors++;
2510 + if (status & XMR_FS_FCS_ERR)
2511 + skge->net_stats.rx_crc_errors++;
2512 + } else {
2513 + if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2514 + skge->net_stats.rx_length_errors++;
2515 + if (status & GMR_FS_FRAGMENT)
2516 + skge->net_stats.rx_frame_errors++;
2517 + if (status & GMR_FS_CRC_ERR)
2518 + skge->net_stats.rx_crc_errors++;
2519 + }
2520 +}
2521 +
2522 +/* Get receive buffer from descriptor.
2523 + * Handles copy of small buffers and reallocation failures
2524 + */
2525 +static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2526 + struct skge_element *e,
2527 + unsigned int len)
2528 +{
2529 + struct sk_buff *nskb, *skb;
2530 +
2531 + if (len < RX_COPY_THRESHOLD) {
2532 + nskb = skge_rx_alloc(skge->netdev, len + NET_IP_ALIGN);
2533 + if (unlikely(!nskb))
2534 + return NULL;
2535 +
2536 + pci_dma_sync_single_for_cpu(skge->hw->pdev,
2537 + pci_unmap_addr(e, mapaddr),
2538 + len, PCI_DMA_FROMDEVICE);
2539 + memcpy(nskb->data, e->skb->data, len);
2540 + pci_dma_sync_single_for_device(skge->hw->pdev,
2541 + pci_unmap_addr(e, mapaddr),
2542 + len, PCI_DMA_FROMDEVICE);
2543 +
2544 + if (skge->rx_csum) {
2545 + struct skge_rx_desc *rd = e->desc;
2546 + nskb->csum = le16_to_cpu(rd->csum2);
2547 + nskb->ip_summed = CHECKSUM_HW;
2548 + }
2549 + skge_rx_reuse(e, skge->rx_buf_size);
2550 + return nskb;
2551 + } else {
2552 + nskb = skge_rx_alloc(skge->netdev, skge->rx_buf_size);
2553 + if (unlikely(!nskb))
2554 + return NULL;
2555 +
2556 + pci_unmap_single(skge->hw->pdev,
2557 + pci_unmap_addr(e, mapaddr),
2558 + pci_unmap_len(e, maplen),
2559 + PCI_DMA_FROMDEVICE);
2560 + skb = e->skb;
2561 + if (skge->rx_csum) {
2562 + struct skge_rx_desc *rd = e->desc;
2563 + skb->csum = le16_to_cpu(rd->csum2);
2564 + skb->ip_summed = CHECKSUM_HW;
2565 + }
2566 +
2567 + skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2568 + return skb;
2569 + }
2570 +}
2571 +
2572 +
2573 +static int skge_poll(struct net_device *dev, int *budget)
2574 +{
2575 + struct skge_port *skge = netdev_priv(dev);
2576 + struct skge_hw *hw = skge->hw;
2577 + struct skge_ring *ring = &skge->rx_ring;
2578 + struct skge_element *e;
2579 + unsigned int to_do = min(dev->quota, *budget);
2580 + unsigned int work_done = 0;
2581 +
2582 + pr_debug("skge_poll\n");
2583 +
2584 + for (e = ring->to_clean; work_done < to_do; e = e->next) {
2585 + struct skge_rx_desc *rd = e->desc;
2586 + struct sk_buff *skb;
2587 + u32 control, len, status;
2588 +
2589 + rmb();
2590 + control = rd->control;
2591 + if (control & BMU_OWN)
2592 + break;
2593 +
2594 + len = control & BMU_BBC;
2595 + status = rd->status;
2596 +
2597 + if (unlikely((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)
2598 + || bad_phy_status(hw, status))) {
2599 + skge_rx_error(skge, e - ring->start, control, status);
2600 + skge_rx_reuse(e, skge->rx_buf_size);
2601 + continue;
2602 + }
2603 +
2604 + if (netif_msg_rx_status(skge))
2605 + printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2606 + dev->name, e - ring->start, rd->status, len);
2607 +
2608 + skb = skge_rx_get(skge, e, len);
2609 + if (likely(skb)) {
2610 + skb_put(skb, len);
2611 + skb->protocol = eth_type_trans(skb, dev);
2612 +
2613 + dev->last_rx = jiffies;
2614 + netif_receive_skb(skb);
2615 +
2616 + ++work_done;
2617 + } else
2618 + skge_rx_reuse(e, skge->rx_buf_size);
2619 + }
2620 + ring->to_clean = e;
2621 +
2622 + /* restart receiver */
2623 + wmb();
2624 + skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR),
2625 + CSR_START | CSR_IRQ_CL_F);
2626 +
2627 + *budget -= work_done;
2628 + dev->quota -= work_done;
2629 +
2630 + if (work_done >= to_do)
2631 + return 1; /* not done */
2632 +
2633 + local_irq_disable();
2634 + __netif_rx_complete(dev);
2635 + hw->intr_mask |= portirqmask[skge->port];
2636 + skge_write32(hw, B0_IMSK, hw->intr_mask);
2637 + local_irq_enable();
2638 + return 0;
2639 +}
2640 +
2641 +static inline void skge_tx_intr(struct net_device *dev)
2642 +{
2643 + struct skge_port *skge = netdev_priv(dev);
2644 + struct skge_hw *hw = skge->hw;
2645 + struct skge_ring *ring = &skge->tx_ring;
2646 + struct skge_element *e;
2647 +
2648 + spin_lock(&skge->tx_lock);
2649 + for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2650 + struct skge_tx_desc *td = e->desc;
2651 + u32 control;
2652 +
2653 + rmb();
2654 + control = td->control;
2655 + if (control & BMU_OWN)
2656 + break;
2657 +
2658 + if (unlikely(netif_msg_tx_done(skge)))
2659 + printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
2660 + dev->name, e - ring->start, td->status);
2661 +
2662 + skge_tx_free(hw, e);
2663 + e->skb = NULL;
2664 + ++skge->tx_avail;
2665 + }
2666 + ring->to_clean = e;
2667 + skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2668 +
2669 + if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2670 + netif_wake_queue(dev);
2671 +
2672 + spin_unlock(&skge->tx_lock);
2673 +}
2674 +
2675 +static void skge_mac_parity(struct skge_hw *hw, int port)
2676 +{
2677 + printk(KERN_ERR PFX "%s: mac data parity error\n",
2678 + hw->dev[port] ? hw->dev[port]->name
2679 + : (port == 0 ? "(port A)": "(port B"));
2680 +
2681 + if (hw->chip_id == CHIP_ID_GENESIS)
2682 + skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
2683 + MFF_CLR_PERR);
2684 + else
2685 + /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
2686 + skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
2687 + (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
2688 + ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2689 +}
2690 +
2691 +static void skge_pci_clear(struct skge_hw *hw)
2692 +{
2693 + u16 status;
2694 +
2695 + pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2696 + skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2697 + pci_write_config_word(hw->pdev, PCI_STATUS,
2698 + status | PCI_STATUS_ERROR_BITS);
2699 + skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2700 +}
2701 +
2702 +static void skge_mac_intr(struct skge_hw *hw, int port)
2703 +{
2704 + if (hw->chip_id == CHIP_ID_GENESIS)
2705 + genesis_mac_intr(hw, port);
2706 + else
2707 + yukon_mac_intr(hw, port);
2708 +}
2709 +
2710 +/* Handle device specific framing and timeout interrupts */
2711 +static void skge_error_irq(struct skge_hw *hw)
2712 +{
2713 + u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2714 +
2715 + if (hw->chip_id == CHIP_ID_GENESIS) {
2716 + /* clear xmac errors */
2717 + if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
2718 + skge_write16(hw, SK_REG(0, RX_MFF_CTRL1), MFF_CLR_INSTAT);
2719 + if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
2720 + skge_write16(hw, SK_REG(0, RX_MFF_CTRL2), MFF_CLR_INSTAT);
2721 + } else {
2722 + /* Timestamp (unused) overflow */
2723 + if (hwstatus & IS_IRQ_TIST_OV)
2724 + skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2725 +
2726 + if (hwstatus & IS_IRQ_SENSOR) {
2727 + /* no sensors on 32-bit Yukon */
2728 + if (!(skge_read16(hw, B0_CTST) & CS_BUS_SLOT_SZ)) {
2729 + printk(KERN_ERR PFX "ignoring bogus sensor interrups\n");
2730 + skge_write32(hw, B0_HWE_IMSK,
2731 + IS_ERR_MSK & ~IS_IRQ_SENSOR);
2732 + } else
2733 + printk(KERN_WARNING PFX "sensor interrupt\n");
2734 + }
2735 +
2736 +
2737 + }
2738 +
2739 + if (hwstatus & IS_RAM_RD_PAR) {
2740 + printk(KERN_ERR PFX "Ram read data parity error\n");
2741 + skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2742 + }
2743 +
2744 + if (hwstatus & IS_RAM_WR_PAR) {
2745 + printk(KERN_ERR PFX "Ram write data parity error\n");
2746 + skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2747 + }
2748 +
2749 + if (hwstatus & IS_M1_PAR_ERR)
2750 + skge_mac_parity(hw, 0);
2751 +
2752 + if (hwstatus & IS_M2_PAR_ERR)
2753 + skge_mac_parity(hw, 1);
2754 +
2755 + if (hwstatus & IS_R1_PAR_ERR)
2756 + skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2757 +
2758 + if (hwstatus & IS_R2_PAR_ERR)
2759 + skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2760 +
2761 + if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2762 + printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
2763 + hwstatus);
2764 +
2765 + skge_pci_clear(hw);
2766 +
2767 + hwstatus = skge_read32(hw, B0_HWE_ISRC);
2768 + if (hwstatus & IS_IRQ_STAT) {
2769 + printk(KERN_WARNING PFX "IRQ status %x: still set ignoring hardware errors\n",
2770 + hwstatus);
2771 + hw->intr_mask &= ~IS_HW_ERR;
2772 + }
2773 + }
2774 +}
2775 +
2776 +/*
2777 + * Interrrupt from PHY are handled in tasklet (soft irq)
2778 + * because accessing phy registers requires spin wait which might
2779 + * cause excess interrupt latency.
2780 + */
2781 +static void skge_extirq(unsigned long data)
2782 +{
2783 + struct skge_hw *hw = (struct skge_hw *) data;
2784 + int port;
2785 +
2786 + spin_lock(&hw->phy_lock);
2787 + for (port = 0; port < 2; port++) {
2788 + struct net_device *dev = hw->dev[port];
2789 +
2790 + if (dev && netif_running(dev)) {
2791 + struct skge_port *skge = netdev_priv(dev);
2792 +
2793 + if (hw->chip_id != CHIP_ID_GENESIS)
2794 + yukon_phy_intr(skge);
2795 + else
2796 + bcom_phy_intr(skge);
2797 + }
2798 + }
2799 + spin_unlock(&hw->phy_lock);
2800 +
2801 + local_irq_disable();
2802 + hw->intr_mask |= IS_EXT_REG;
2803 + skge_write32(hw, B0_IMSK, hw->intr_mask);
2804 + local_irq_enable();
2805 +}
2806 +
2807 +static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2808 +{
2809 + struct skge_hw *hw = dev_id;
2810 + u32 status = skge_read32(hw, B0_SP_ISRC);
2811 +
2812 + if (status == 0 || status == ~0) /* hotplug or shared irq */
2813 + return IRQ_NONE;
2814 +
2815 + status &= hw->intr_mask;
2816 + if (status & IS_R1_F) {
2817 + hw->intr_mask &= ~IS_R1_F;
2818 + netif_rx_schedule(hw->dev[0]);
2819 + }
2820 +
2821 + if (status & IS_R2_F) {
2822 + hw->intr_mask &= ~IS_R2_F;
2823 + netif_rx_schedule(hw->dev[1]);
2824 + }
2825 +
2826 + if (status & IS_XA1_F)
2827 + skge_tx_intr(hw->dev[0]);
2828 +
2829 + if (status & IS_XA2_F)
2830 + skge_tx_intr(hw->dev[1]);
2831 +
2832 + if (status & IS_PA_TO_RX1) {
2833 + struct skge_port *skge = netdev_priv(hw->dev[0]);
2834 + ++skge->net_stats.rx_over_errors;
2835 + skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2836 + }
2837 +
2838 + if (status & IS_PA_TO_RX2) {
2839 + struct skge_port *skge = netdev_priv(hw->dev[1]);
2840 + ++skge->net_stats.rx_over_errors;
2841 + skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2842 + }
2843 +
2844 + if (status & IS_PA_TO_TX1)
2845 + skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2846 +
2847 + if (status & IS_PA_TO_TX2)
2848 + skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2849 +
2850 + if (status & IS_MAC1)
2851 + skge_mac_intr(hw, 0);
2852 +
2853 + if (status & IS_MAC2)
2854 + skge_mac_intr(hw, 1);
2855 +
2856 + if (status & IS_HW_ERR)
2857 + skge_error_irq(hw);
2858 +
2859 + if (status & IS_EXT_REG) {
2860 + hw->intr_mask &= ~IS_EXT_REG;
2861 + tasklet_schedule(&hw->ext_tasklet);
2862 + }
2863 +
2864 + skge_write32(hw, B0_IMSK, hw->intr_mask);
2865 +
2866 + return IRQ_HANDLED;
2867 +}
2868 +
2869 +#ifdef CONFIG_NET_POLL_CONTROLLER
2870 +static void skge_netpoll(struct net_device *dev)
2871 +{
2872 + struct skge_port *skge = netdev_priv(dev);
2873 +
2874 + disable_irq(dev->irq);
2875 + skge_intr(dev->irq, skge->hw, NULL);
2876 + enable_irq(dev->irq);
2877 +}
2878 +#endif
2879 +
2880 +static int skge_set_mac_address(struct net_device *dev, void *p)
2881 +{
2882 + struct skge_port *skge = netdev_priv(dev);
2883 + struct sockaddr *addr = p;
2884 + int err = 0;
2885 +
2886 + if (!is_valid_ether_addr(addr->sa_data))
2887 + return -EADDRNOTAVAIL;
2888 +
2889 + skge_down(dev);
2890 + memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2891 + memcpy_toio(skge->hw->regs + B2_MAC_1 + skge->port*8,
2892 + dev->dev_addr, ETH_ALEN);
2893 + memcpy_toio(skge->hw->regs + B2_MAC_2 + skge->port*8,
2894 + dev->dev_addr, ETH_ALEN);
2895 + if (dev->flags & IFF_UP)
2896 + err = skge_up(dev);
2897 + return err;
2898 +}
2899 +
2900 +static const struct {
2901 + u8 id;
2902 + const char *name;
2903 +} skge_chips[] = {
2904 + { CHIP_ID_GENESIS, "Genesis" },
2905 + { CHIP_ID_YUKON, "Yukon" },
2906 + { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2907 + { CHIP_ID_YUKON_LP, "Yukon-LP"},
2908 +};
2909 +
2910 +static const char *skge_board_name(const struct skge_hw *hw)
2911 +{
2912 + int i;
2913 + static char buf[16];
2914 +
2915 + for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2916 + if (skge_chips[i].id == hw->chip_id)
2917 + return skge_chips[i].name;
2918 +
2919 + snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2920 + return buf;
2921 +}
2922 +
2923 +
2924 +/*
2925 + * Setup the board data structure, but don't bring up
2926 + * the port(s)
2927 + */
2928 +static int skge_reset(struct skge_hw *hw)
2929 +{
2930 + u16 ctst;
2931 + u8 t8, mac_cfg;
2932 + int i;
2933 +
2934 + ctst = skge_read16(hw, B0_CTST);
2935 +
2936 + /* do a SW reset */
2937 + skge_write8(hw, B0_CTST, CS_RST_SET);
2938 + skge_write8(hw, B0_CTST, CS_RST_CLR);
2939 +
2940 + /* clear PCI errors, if any */
2941 + skge_pci_clear(hw);
2942 +
2943 + skge_write8(hw, B0_CTST, CS_MRST_CLR);
2944 +
2945 + /* restore CLK_RUN bits (for Yukon-Lite) */
2946 + skge_write16(hw, B0_CTST,
2947 + ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
2948 +
2949 + hw->chip_id = skge_read8(hw, B2_CHIP_ID);
2950 + hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
2951 + hw->pmd_type = skge_read8(hw, B2_PMD_TYP);
2952 +
2953 + switch (hw->chip_id) {
2954 + case CHIP_ID_GENESIS:
2955 + switch (hw->phy_type) {
2956 + case SK_PHY_BCOM:
2957 + hw->phy_addr = PHY_ADDR_BCOM;
2958 + break;
2959 + default:
2960 + printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
2961 + pci_name(hw->pdev), hw->phy_type);
2962 + return -EOPNOTSUPP;
2963 + }
2964 + break;
2965 +
2966 + case CHIP_ID_YUKON:
2967 + case CHIP_ID_YUKON_LITE:
2968 + case CHIP_ID_YUKON_LP:
2969 + if (hw->phy_type < SK_PHY_MARV_COPPER && hw->pmd_type != 'S')
2970 + hw->phy_type = SK_PHY_MARV_COPPER;
2971 +
2972 + hw->phy_addr = PHY_ADDR_MARV;
2973 + if (!iscopper(hw))
2974 + hw->phy_type = SK_PHY_MARV_FIBER;
2975 +
2976 + break;
2977 +
2978 + default:
2979 + printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2980 + pci_name(hw->pdev), hw->chip_id);
2981 + return -EOPNOTSUPP;
2982 + }
2983 +
2984 + mac_cfg = skge_read8(hw, B2_MAC_CFG);
2985 + hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
2986 + hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
2987 +
2988 + /* read the adapters RAM size */
2989 + t8 = skge_read8(hw, B2_E_0);
2990 + if (hw->chip_id == CHIP_ID_GENESIS) {
2991 + if (t8 == 3) {
2992 + /* special case: 4 x 64k x 36, offset = 0x80000 */
2993 + hw->ram_size = 0x100000;
2994 + hw->ram_offset = 0x80000;
2995 + } else
2996 + hw->ram_size = t8 * 512;
2997 + }
2998 + else if (t8 == 0)
2999 + hw->ram_size = 0x20000;
3000 + else
3001 + hw->ram_size = t8 * 4096;
3002 +
3003 + if (hw->chip_id == CHIP_ID_GENESIS)
3004 + genesis_init(hw);
3005 + else {
3006 + /* switch power to VCC (WA for VAUX problem) */
3007 + skge_write8(hw, B0_POWER_CTRL,
3008 + PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3009 + for (i = 0; i < hw->ports; i++) {
3010 + skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3011 + skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3012 + }
3013 + }
3014 +
3015 + /* turn off hardware timer (unused) */
3016 + skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3017 + skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3018 + skge_write8(hw, B0_LED, LED_STAT_ON);
3019 +
3020 + /* enable the Tx Arbiters */
3021 + for (i = 0; i < hw->ports; i++)
3022 + skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3023 +
3024 + /* Initialize ram interface */
3025 + skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3026 +
3027 + skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3028 + skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3029 + skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3030 + skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3031 + skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3032 + skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3033 + skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3034 + skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3035 + skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3036 + skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3037 + skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3038 + skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3039 +
3040 + skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3041 +
3042 + /* Set interrupt moderation for Transmit only
3043 + * Receive interrupts avoided by NAPI
3044 + */
3045 + skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3046 + skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3047 + skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3048 +
3049 + hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
3050 + skge_write32(hw, B0_IMSK, hw->intr_mask);
3051 +
3052 + if (hw->chip_id != CHIP_ID_GENESIS)
3053 + skge_write8(hw, GMAC_IRQ_MSK, 0);
3054 +
3055 + spin_lock_bh(&hw->phy_lock);
3056 + for (i = 0; i < hw->ports; i++) {
3057 + if (hw->chip_id == CHIP_ID_GENESIS)
3058 + genesis_reset(hw, i);
3059 + else
3060 + yukon_reset(hw, i);
3061 + }
3062 + spin_unlock_bh(&hw->phy_lock);
3063 +
3064 + return 0;
3065 +}
3066 +
3067 +/* Initialize network device */
3068 +static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3069 + int highmem)
3070 +{
3071 + struct skge_port *skge;
3072 + struct net_device *dev = alloc_etherdev(sizeof(*skge));
3073 +
3074 + if (!dev) {
3075 + printk(KERN_ERR "skge etherdev alloc failed");
3076 + return NULL;
3077 + }
3078 +
3079 + SET_MODULE_OWNER(dev);
3080 + SET_NETDEV_DEV(dev, &hw->pdev->dev);
3081 + dev->open = skge_up;
3082 + dev->stop = skge_down;
3083 + dev->hard_start_xmit = skge_xmit_frame;
3084 + dev->get_stats = skge_get_stats;
3085 + if (hw->chip_id == CHIP_ID_GENESIS)
3086 + dev->set_multicast_list = genesis_set_multicast;
3087 + else
3088 + dev->set_multicast_list = yukon_set_multicast;
3089 +
3090 + dev->set_mac_address = skge_set_mac_address;
3091 + dev->change_mtu = skge_change_mtu;
3092 + SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3093 + dev->tx_timeout = skge_tx_timeout;
3094 + dev->watchdog_timeo = TX_WATCHDOG;
3095 + dev->poll = skge_poll;
3096 + dev->weight = NAPI_WEIGHT;
3097 +#ifdef CONFIG_NET_POLL_CONTROLLER
3098 + dev->poll_controller = skge_netpoll;
3099 +#endif
3100 + dev->irq = hw->pdev->irq;
3101 + dev->features = NETIF_F_LLTX;
3102 + if (highmem)
3103 + dev->features |= NETIF_F_HIGHDMA;
3104 +
3105 + skge = netdev_priv(dev);
3106 + skge->netdev = dev;
3107 + skge->hw = hw;
3108 + skge->msg_enable = netif_msg_init(debug, default_msg);
3109 + skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3110 + skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3111 +
3112 + /* Auto speed and flow control */
3113 + skge->autoneg = AUTONEG_ENABLE;
3114 + skge->flow_control = FLOW_MODE_SYMMETRIC;
3115 + skge->duplex = -1;
3116 + skge->speed = -1;
3117 + skge->advertising = skge_supported_modes(hw);
3118 +
3119 + hw->dev[port] = dev;
3120 +
3121 + skge->port = port;
3122 +
3123 + spin_lock_init(&skge->tx_lock);
3124 +
3125 + init_timer(&skge->led_blink);
3126 + skge->led_blink.function = skge_blink_timer;
3127 + skge->led_blink.data = (unsigned long) skge;
3128 +
3129 + if (hw->chip_id != CHIP_ID_GENESIS) {
3130 + dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3131 + skge->rx_csum = 1;
3132 + }
3133 +
3134 + /* read the mac address */
3135 + memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3136 +
3137 + /* device is off until link detection */
3138 + netif_carrier_off(dev);
3139 + netif_stop_queue(dev);
3140 +
3141 + return dev;
3142 +}
3143 +
3144 +static void __devinit skge_show_addr(struct net_device *dev)
3145 +{
3146 + const struct skge_port *skge = netdev_priv(dev);
3147 +
3148 + if (netif_msg_probe(skge))
3149 + printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3150 + dev->name,
3151 + dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3152 + dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3153 +}
3154 +
3155 +static int __devinit skge_probe(struct pci_dev *pdev,
3156 + const struct pci_device_id *ent)
3157 +{
3158 + struct net_device *dev, *dev1;
3159 + struct skge_hw *hw;
3160 + int err, using_dac = 0;
3161 +
3162 + if ((err = pci_enable_device(pdev))) {
3163 + printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3164 + pci_name(pdev));
3165 + goto err_out;
3166 + }
3167 +
3168 + if ((err = pci_request_regions(pdev, DRV_NAME))) {
3169 + printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3170 + pci_name(pdev));
3171 + goto err_out_disable_pdev;
3172 + }
3173 +
3174 + pci_set_master(pdev);
3175 +
3176 + if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)))
3177 + using_dac = 1;
3178 + else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3179 + printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3180 + pci_name(pdev));
3181 + goto err_out_free_regions;
3182 + }
3183 +
3184 +#ifdef __BIG_ENDIAN
3185 + /* byte swap decriptors in hardware */
3186 + {
3187 + u32 reg;
3188 +
3189 + pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3190 + reg |= PCI_REV_DESC;
3191 + pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3192 + }
3193 +#endif
3194 +
3195 + err = -ENOMEM;
3196 + hw = kmalloc(sizeof(*hw), GFP_KERNEL);
3197 + if (!hw) {
3198 + printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3199 + pci_name(pdev));
3200 + goto err_out_free_regions;
3201 + }
3202 +
3203 + memset(hw, 0, sizeof(*hw));
3204 + hw->pdev = pdev;
3205 + spin_lock_init(&hw->phy_lock);
3206 + tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3207 +
3208 + hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3209 + if (!hw->regs) {
3210 + printk(KERN_ERR PFX "%s: cannot map device registers\n",
3211 + pci_name(pdev));
3212 + goto err_out_free_hw;
3213 + }
3214 +
3215 + if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
3216 + printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3217 + pci_name(pdev), pdev->irq);
3218 + goto err_out_iounmap;
3219 + }
3220 + pci_set_drvdata(pdev, hw);
3221 +
3222 + err = skge_reset(hw);
3223 + if (err)
3224 + goto err_out_free_irq;
3225 +
3226 + printk(KERN_INFO PFX "addr 0x%lx irq %d chip %s rev %d\n",
3227 + pci_resource_start(pdev, 0), pdev->irq,
3228 + skge_board_name(hw), hw->chip_rev);
3229 +
3230 + if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
3231 + goto err_out_led_off;
3232 +
3233 + if ((err = register_netdev(dev))) {
3234 + printk(KERN_ERR PFX "%s: cannot register net device\n",
3235 + pci_name(pdev));
3236 + goto err_out_free_netdev;
3237 + }
3238 +
3239 + skge_show_addr(dev);
3240 +
3241 + if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
3242 + if (register_netdev(dev1) == 0)
3243 + skge_show_addr(dev1);
3244 + else {
3245 + /* Failure to register second port need not be fatal */
3246 + printk(KERN_WARNING PFX "register of second port failed\n");
3247 + hw->dev[1] = NULL;
3248 + free_netdev(dev1);
3249 + }
3250 + }
3251 +
3252 + return 0;
3253 +
3254 +err_out_free_netdev:
3255 + free_netdev(dev);
3256 +err_out_led_off:
3257 + skge_write16(hw, B0_LED, LED_STAT_OFF);
3258 +err_out_free_irq:
3259 + free_irq(pdev->irq, hw);
3260 +err_out_iounmap:
3261 + iounmap(hw->regs);
3262 +err_out_free_hw:
3263 + kfree(hw);
3264 +err_out_free_regions:
3265 + pci_release_regions(pdev);
3266 +err_out_disable_pdev:
3267 + pci_disable_device(pdev);
3268 + pci_set_drvdata(pdev, NULL);
3269 +err_out:
3270 + return err;
3271 +}
3272 +
3273 +static void __devexit skge_remove(struct pci_dev *pdev)
3274 +{
3275 + struct skge_hw *hw = pci_get_drvdata(pdev);
3276 + struct net_device *dev0, *dev1;
3277 +
3278 + if (!hw)
3279 + return;
3280 +
3281 + if ((dev1 = hw->dev[1]))
3282 + unregister_netdev(dev1);
3283 + dev0 = hw->dev[0];
3284 + unregister_netdev(dev0);
3285 +
3286 + tasklet_kill(&hw->ext_tasklet);
3287 +
3288 + free_irq(pdev->irq, hw);
3289 + pci_release_regions(pdev);
3290 + pci_disable_device(pdev);
3291 + if (dev1)
3292 + free_netdev(dev1);
3293 + free_netdev(dev0);
3294 + skge_write16(hw, B0_LED, LED_STAT_OFF);
3295 + iounmap(hw->regs);
3296 + kfree(hw);
3297 + pci_set_drvdata(pdev, NULL);
3298 +}
3299 +
3300 +#ifdef CONFIG_PM
3301 +static int skge_suspend(struct pci_dev *pdev, u32 state)
3302 +{
3303 + struct skge_hw *hw = pci_get_drvdata(pdev);
3304 + int i, wol = 0;
3305 +
3306 + for (i = 0; i < 2; i++) {
3307 + struct net_device *dev = hw->dev[i];
3308 +
3309 + if (dev) {
3310 + struct skge_port *skge = netdev_priv(dev);
3311 + if (netif_running(dev)) {
3312 + netif_carrier_off(dev);
3313 + skge_down(dev);
3314 + }
3315 + netif_device_detach(dev);
3316 + wol |= skge->wol;
3317 + }
3318 + }
3319 +
3320 + pci_save_state(pdev);
3321 + pci_enable_wake(pdev, state, wol);
3322 + pci_disable_device(pdev);
3323 + pci_set_power_state(pdev, pci_choose_state(pdev, state));
3324 +
3325 + return 0;
3326 +}
3327 +
3328 +static int skge_resume(struct pci_dev *pdev)
3329 +{
3330 + struct skge_hw *hw = pci_get_drvdata(pdev);
3331 + int i;
3332 +
3333 + pci_set_power_state(pdev, PCI_D0);
3334 + pci_restore_state(pdev);
3335 + pci_enable_wake(pdev, PCI_D0, 0);
3336 +
3337 + skge_reset(hw);
3338 +
3339 + for (i = 0; i < 2; i++) {
3340 + struct net_device *dev = hw->dev[i];
3341 + if (dev) {
3342 + netif_device_attach(dev);
3343 + if (netif_running(dev))
3344 + skge_up(dev);
3345 + }
3346 + }
3347 + return 0;
3348 +}
3349 +#endif
3350 +
3351 +static struct pci_driver skge_driver = {
3352 + .name = DRV_NAME,
3353 + .id_table = skge_id_table,
3354 + .probe = skge_probe,
3355 + .remove = __devexit_p(skge_remove),
3356 +#ifdef CONFIG_PM
3357 + .suspend = skge_suspend,
3358 + .resume = skge_resume,
3359 +#endif
3360 +};
3361 +
3362 +static int __init skge_init_module(void)
3363 +{
3364 + return pci_module_init(&skge_driver);
3365 +}
3366 +
3367 +static void __exit skge_cleanup_module(void)
3368 +{
3369 + pci_unregister_driver(&skge_driver);
3370 +}
3371 +
3372 +module_init(skge_init_module);
3373 +module_exit(skge_cleanup_module);
3374 diff -urNpX dontdiff linux-2.6.12/drivers/net/skge.h linux-dsd/drivers/net/skge.h
3375 --- linux-2.6.12/drivers/net/skge.h 1970-01-01 01:00:00.000000000 +0100
3376 +++ linux-dsd/drivers/net/skge.h 2005-06-28 00:59:27.000000000 +0100
3377 @@ -0,0 +1,2627 @@
3378 +/*
3379 + * Definitions for the new Marvell Yukon / SysKonenct driver.
3380 + */
3381 +#ifndef _SKGE_H
3382 +#define _SKGE_H
3383 +
3384 +/* PCI config registers */
3385 +#define PCI_DEV_REG1 0x40
3386 +#define PCI_DEV_REG2 0x44
3387 +
3388 +#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
3389 + PCI_STATUS_SIG_SYSTEM_ERROR | \
3390 + PCI_STATUS_REC_MASTER_ABORT | \
3391 + PCI_STATUS_REC_TARGET_ABORT | \
3392 + PCI_STATUS_PARITY)
3393 +
3394 +enum csr_regs {
3395 + B0_RAP = 0x0000,
3396 + B0_CTST = 0x0004,
3397 + B0_LED = 0x0006,
3398 + B0_POWER_CTRL = 0x0007,
3399 + B0_ISRC = 0x0008,
3400 + B0_IMSK = 0x000c,
3401 + B0_HWE_ISRC = 0x0010,
3402 + B0_HWE_IMSK = 0x0014,
3403 + B0_SP_ISRC = 0x0018,
3404 + B0_XM1_IMSK = 0x0020,
3405 + B0_XM1_ISRC = 0x0028,
3406 + B0_XM1_PHY_ADDR = 0x0030,
3407 + B0_XM1_PHY_DATA = 0x0034,
3408 + B0_XM2_IMSK = 0x0040,
3409 + B0_XM2_ISRC = 0x0048,
3410 + B0_XM2_PHY_ADDR = 0x0050,
3411 + B0_XM2_PHY_DATA = 0x0054,
3412 + B0_R1_CSR = 0x0060,
3413 + B0_R2_CSR = 0x0064,
3414 + B0_XS1_CSR = 0x0068,
3415 + B0_XA1_CSR = 0x006c,
3416 + B0_XS2_CSR = 0x0070,
3417 + B0_XA2_CSR = 0x0074,
3418 +
3419 + B2_MAC_1 = 0x0100,
3420 + B2_MAC_2 = 0x0108,
3421 + B2_MAC_3 = 0x0110,
3422 + B2_CONN_TYP = 0x0118,
3423 + B2_PMD_TYP = 0x0119,
3424 + B2_MAC_CFG = 0x011a,
3425 + B2_CHIP_ID = 0x011b,
3426 + B2_E_0 = 0x011c,
3427 + B2_E_1 = 0x011d,
3428 + B2_E_2 = 0x011e,
3429 + B2_E_3 = 0x011f,
3430 + B2_FAR = 0x0120,
3431 + B2_FDP = 0x0124,
3432 + B2_LD_CTRL = 0x0128,
3433 + B2_LD_TEST = 0x0129,
3434 + B2_TI_INI = 0x0130,
3435 + B2_TI_VAL = 0x0134,
3436 + B2_TI_CTRL = 0x0138,
3437 + B2_TI_TEST = 0x0139,
3438 + B2_IRQM_INI = 0x0140,
3439 + B2_IRQM_VAL = 0x0144,
3440 + B2_IRQM_CTRL = 0x0148,
3441 + B2_IRQM_TEST = 0x0149,
3442 + B2_IRQM_MSK = 0x014c,
3443 + B2_IRQM_HWE_MSK = 0x0150,
3444 + B2_TST_CTRL1 = 0x0158,
3445 + B2_TST_CTRL2 = 0x0159,
3446 + B2_GP_IO = 0x015c,
3447 + B2_I2C_CTRL = 0x0160,
3448 + B2_I2C_DATA = 0x0164,
3449 + B2_I2C_IRQ = 0x0168,
3450 + B2_I2C_SW = 0x016c,
3451 + B2_BSC_INI = 0x0170,
3452 + B2_BSC_VAL = 0x0174,
3453 + B2_BSC_CTRL = 0x0178,
3454 + B2_BSC_STAT = 0x0179,
3455 + B2_BSC_TST = 0x017a,
3456 +
3457 + B3_RAM_ADDR = 0x0180,
3458 + B3_RAM_DATA_LO = 0x0184,
3459 + B3_RAM_DATA_HI = 0x0188,
3460 + B3_RI_WTO_R1 = 0x0190,
3461 + B3_RI_WTO_XA1 = 0x0191,
3462 + B3_RI_WTO_XS1 = 0x0192,
3463 + B3_RI_RTO_R1 = 0x0193,
3464 + B3_RI_RTO_XA1 = 0x0194,
3465 + B3_RI_RTO_XS1 = 0x0195,
3466 + B3_RI_WTO_R2 = 0x0196,
3467 + B3_RI_WTO_XA2 = 0x0197,
3468 + B3_RI_WTO_XS2 = 0x0198,
3469 + B3_RI_RTO_R2 = 0x0199,
3470 + B3_RI_RTO_XA2 = 0x019a,
3471 + B3_RI_RTO_XS2 = 0x019b,
3472 + B3_RI_TO_VAL = 0x019c,
3473 + B3_RI_CTRL = 0x01a0,
3474 + B3_RI_TEST = 0x01a2,
3475 + B3_MA_TOINI_RX1 = 0x01b0,
3476 + B3_MA_TOINI_RX2 = 0x01b1,
3477 + B3_MA_TOINI_TX1 = 0x01b2,
3478 + B3_MA_TOINI_TX2 = 0x01b3,
3479 + B3_MA_TOVAL_RX1 = 0x01b4,
3480 + B3_MA_TOVAL_RX2 = 0x01b5,
3481 + B3_MA_TOVAL_TX1 = 0x01b6,
3482 + B3_MA_TOVAL_TX2 = 0x01b7,
3483 + B3_MA_TO_CTRL = 0x01b8,
3484 + B3_MA_TO_TEST = 0x01ba,
3485 + B3_MA_RCINI_RX1 = 0x01c0,
3486 + B3_MA_RCINI_RX2 = 0x01c1,
3487 + B3_MA_RCINI_TX1 = 0x01c2,
3488 + B3_MA_RCINI_TX2 = 0x01c3,
3489 + B3_MA_RCVAL_RX1 = 0x01c4,
3490 + B3_MA_RCVAL_RX2 = 0x01c5,
3491 + B3_MA_RCVAL_TX1 = 0x01c6,
3492 + B3_MA_RCVAL_TX2 = 0x01c7,
3493 + B3_MA_RC_CTRL = 0x01c8,
3494 + B3_MA_RC_TEST = 0x01ca,
3495 + B3_PA_TOINI_RX1 = 0x01d0,
3496 + B3_PA_TOINI_RX2 = 0x01d4,
3497 + B3_PA_TOINI_TX1 = 0x01d8,
3498 + B3_PA_TOINI_TX2 = 0x01dc,
3499 + B3_PA_TOVAL_RX1 = 0x01e0,
3500 + B3_PA_TOVAL_RX2 = 0x01e4,
3501 + B3_PA_TOVAL_TX1 = 0x01e8,
3502 + B3_PA_TOVAL_TX2 = 0x01ec,
3503 + B3_PA_CTRL = 0x01f0,
3504 + B3_PA_TEST = 0x01f2,
3505 +};
3506 +
3507 +/* B0_CTST 16 bit Control/Status register */
3508 +enum {
3509 + CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
3510 + CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
3511 + CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
3512 + CS_VAUX_AVAIL = 1<<10,/* VAUX available (YUKON only) */
3513 + CS_BUS_CLOCK = 1<<9, /* Bus Clock 0/1 = 33/66 MHz */
3514 + CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
3515 + CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
3516 + CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
3517 + CS_STOP_DONE = 1<<5, /* Stop Master is finished */
3518 + CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
3519 + CS_MRST_CLR = 1<<3, /* Clear Master reset */
3520 + CS_MRST_SET = 1<<2, /* Set Master reset */
3521 + CS_RST_CLR = 1<<1, /* Clear Software reset */
3522 + CS_RST_SET = 1, /* Set Software reset */
3523 +
3524 +/* B0_LED 8 Bit LED register */
3525 +/* Bit 7.. 2: reserved */
3526 + LED_STAT_ON = 1<<1, /* Status LED on */
3527 + LED_STAT_OFF = 1, /* Status LED off */
3528 +
3529 +/* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
3530 + PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
3531 + PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
3532 + PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
3533 + PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
3534 + PC_VAUX_ON = 1<<3, /* Switch VAUX On */
3535 + PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
3536 + PC_VCC_ON = 1<<1, /* Switch VCC On */
3537 + PC_VCC_OFF = 1<<0, /* Switch VCC Off */
3538 +};
3539 +
3540 +/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
3541 +enum {
3542 + IS_ALL_MSK = 0xbffffffful, /* All Interrupt bits */
3543 + IS_HW_ERR = 1<<31, /* Interrupt HW Error */
3544 + /* Bit 30: reserved */
3545 + IS_PA_TO_RX1 = 1<<29, /* Packet Arb Timeout Rx1 */
3546 + IS_PA_TO_RX2 = 1<<28, /* Packet Arb Timeout Rx2 */
3547 + IS_PA_TO_TX1 = 1<<27, /* Packet Arb Timeout Tx1 */
3548 + IS_PA_TO_TX2 = 1<<26, /* Packet Arb Timeout Tx2 */
3549 + IS_I2C_READY = 1<<25, /* IRQ on end of I2C Tx */
3550 + IS_IRQ_SW = 1<<24, /* SW forced IRQ */
3551 + IS_EXT_REG = 1<<23, /* IRQ from LM80 or PHY (GENESIS only) */
3552 + /* IRQ from PHY (YUKON only) */
3553 + IS_TIMINT = 1<<22, /* IRQ from Timer */
3554 + IS_MAC1 = 1<<21, /* IRQ from MAC 1 */
3555 + IS_LNK_SYNC_M1 = 1<<20, /* Link Sync Cnt wrap MAC 1 */
3556 + IS_MAC2 = 1<<19, /* IRQ from MAC 2 */
3557 + IS_LNK_SYNC_M2 = 1<<18, /* Link Sync Cnt wrap MAC 2 */
3558 +/* Receive Queue 1 */
3559 + IS_R1_B = 1<<17, /* Q_R1 End of Buffer */
3560 + IS_R1_F = 1<<16, /* Q_R1 End of Frame */
3561 + IS_R1_C = 1<<15, /* Q_R1 Encoding Error */
3562 +/* Receive Queue 2 */
3563 + IS_R2_B = 1<<14, /* Q_R2 End of Buffer */
3564 + IS_R2_F = 1<<13, /* Q_R2 End of Frame */
3565 + IS_R2_C = 1<<12, /* Q_R2 Encoding Error */
3566 +/* Synchronous Transmit Queue 1 */
3567 + IS_XS1_B = 1<<11, /* Q_XS1 End of Buffer */
3568 + IS_XS1_F = 1<<10, /* Q_XS1 End of Frame */
3569 + IS_XS1_C = 1<<9, /* Q_XS1 Encoding Error */
3570 +/* Asynchronous Transmit Queue 1 */
3571 + IS_XA1_B = 1<<8, /* Q_XA1 End of Buffer */
3572 + IS_XA1_F = 1<<7, /* Q_XA1 End of Frame */
3573 + IS_XA1_C = 1<<6, /* Q_XA1 Encoding Error */
3574 +/* Synchronous Transmit Queue 2 */
3575 + IS_XS2_B = 1<<5, /* Q_XS2 End of Buffer */
3576 + IS_XS2_F = 1<<4, /* Q_XS2 End of Frame */
3577 + IS_XS2_C = 1<<3, /* Q_XS2 Encoding Error */
3578 +/* Asynchronous Transmit Queue 2 */
3579 + IS_XA2_B = 1<<2, /* Q_XA2 End of Buffer */
3580 + IS_XA2_F = 1<<1, /* Q_XA2 End of Frame */
3581 + IS_XA2_C = 1<<0, /* Q_XA2 Encoding Error */
3582 +
3583 + IS_TO_PORT1 = IS_PA_TO_RX1 | IS_PA_TO_TX1,
3584 + IS_TO_PORT2 = IS_PA_TO_RX2 | IS_PA_TO_TX2,
3585 +
3586 + IS_PORT_1 = IS_XA1_F| IS_R1_F | IS_TO_PORT1 | IS_MAC1,
3587 + IS_PORT_2 = IS_XA2_F| IS_R2_F | IS_TO_PORT2 | IS_MAC2,
3588 +};
3589 +
3590 +
3591 +/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
3592 +enum {
3593 + IS_ERR_MSK = 0x00003fff,/* All Error bits */
3594 +
3595 + IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
3596 + IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
3597 + IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
3598 + IS_IRQ_STAT = 1<<10, /* IRQ status exception */
3599 + IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
3600 + IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
3601 + IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
3602 + IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
3603 + IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
3604 + IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
3605 + IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
3606 + IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
3607 + IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
3608 + IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
3609 +};
3610 +
3611 +/* B2_TST_CTRL1 8 bit Test Control Register 1 */
3612 +enum {
3613 + TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
3614 + TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
3615 + TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
3616 + TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
3617 + TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
3618 + TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
3619 + TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
3620 + TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
3621 +};
3622 +
3623 +/* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
3624 +enum {
3625 + CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
3626 + /* Bit 3.. 2: reserved */
3627 + CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
3628 + CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
3629 +};
3630 +
3631 +/* B2_CHIP_ID 8 bit Chip Identification Number */
3632 +enum {
3633 + CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */
3634 + CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */
3635 + CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
3636 + CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
3637 + CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
3638 + CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
3639 + CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
3640 +
3641 + CHIP_REV_YU_LITE_A1 = 3, /* Chip Rev. for YUKON-Lite A1,A2 */
3642 + CHIP_REV_YU_LITE_A3 = 7, /* Chip Rev. for YUKON-Lite A3 */
3643 +};
3644 +
3645 +/* B2_TI_CTRL 8 bit Timer control */
3646 +/* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
3647 +enum {
3648 + TIM_START = 1<<2, /* Start Timer */
3649 + TIM_STOP = 1<<1, /* Stop Timer */
3650 + TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
3651 +};
3652 +
3653 +/* B2_TI_TEST 8 Bit Timer Test */
3654 +/* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
3655 +/* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
3656 +enum {
3657 + TIM_T_ON = 1<<2, /* Test mode on */
3658 + TIM_T_OFF = 1<<1, /* Test mode off */
3659 + TIM_T_STEP = 1<<0, /* Test step */
3660 +};
3661 +
3662 +/* B2_GP_IO 32 bit General Purpose I/O Register */
3663 +enum {
3664 + GP_DIR_9 = 1<<25, /* IO_9 direct, 0=In/1=Out */
3665 + GP_DIR_8 = 1<<24, /* IO_8 direct, 0=In/1=Out */
3666 + GP_DIR_7 = 1<<23, /* IO_7 direct, 0=In/1=Out */
3667 + GP_DIR_6 = 1<<22, /* IO_6 direct, 0=In/1=Out */
3668 + GP_DIR_5 = 1<<21, /* IO_5 direct, 0=In/1=Out */
3669 + GP_DIR_4 = 1<<20, /* IO_4 direct, 0=In/1=Out */
3670 + GP_DIR_3 = 1<<19, /* IO_3 direct, 0=In/1=Out */
3671 + GP_DIR_2 = 1<<18, /* IO_2 direct, 0=In/1=Out */
3672 + GP_DIR_1 = 1<<17, /* IO_1 direct, 0=In/1=Out */
3673 + GP_DIR_0 = 1<<16, /* IO_0 direct, 0=In/1=Out */
3674 +
3675 + GP_IO_9 = 1<<9, /* IO_9 pin */
3676 + GP_IO_8 = 1<<8, /* IO_8 pin */
3677 + GP_IO_7 = 1<<7, /* IO_7 pin */
3678 + GP_IO_6 = 1<<6, /* IO_6 pin */
3679 + GP_IO_5 = 1<<5, /* IO_5 pin */
3680 + GP_IO_4 = 1<<4, /* IO_4 pin */
3681 + GP_IO_3 = 1<<3, /* IO_3 pin */
3682 + GP_IO_2 = 1<<2, /* IO_2 pin */
3683 + GP_IO_1 = 1<<1, /* IO_1 pin */
3684 + GP_IO_0 = 1<<0, /* IO_0 pin */
3685 +};
3686 +
3687 +/* Descriptor Bit Definition */
3688 +/* TxCtrl Transmit Buffer Control Field */
3689 +/* RxCtrl Receive Buffer Control Field */
3690 +enum {
3691 + BMU_OWN = 1<<31, /* OWN bit: 0=host/1=BMU */
3692 + BMU_STF = 1<<30, /* Start of Frame */
3693 + BMU_EOF = 1<<29, /* End of Frame */
3694 + BMU_IRQ_EOB = 1<<28, /* Req "End of Buffer" IRQ */
3695 + BMU_IRQ_EOF = 1<<27, /* Req "End of Frame" IRQ */
3696 + /* TxCtrl specific bits */
3697 + BMU_STFWD = 1<<26, /* (Tx) Store & Forward Frame */
3698 + BMU_NO_FCS = 1<<25, /* (Tx) Disable MAC FCS (CRC) generation */
3699 + BMU_SW = 1<<24, /* (Tx) 1 bit res. for SW use */
3700 + /* RxCtrl specific bits */
3701 + BMU_DEV_0 = 1<<26, /* (Rx) Transfer data to Dev0 */
3702 + BMU_STAT_VAL = 1<<25, /* (Rx) Rx Status Valid */
3703 + BMU_TIST_VAL = 1<<24, /* (Rx) Rx TimeStamp Valid */
3704 + /* Bit 23..16: BMU Check Opcodes */
3705 + BMU_CHECK = 0x55<<16, /* Default BMU check */
3706 + BMU_TCP_CHECK = 0x56<<16, /* Descr with TCP ext */
3707 + BMU_UDP_CHECK = 0x57<<16, /* Descr with UDP ext (YUKON only) */
3708 + BMU_BBC = 0xffffL, /* Bit 15.. 0: Buffer Byte Counter */
3709 +};
3710 +
3711 +/* B2_BSC_CTRL 8 bit Blink Source Counter Control */
3712 +enum {
3713 + BSC_START = 1<<1, /* Start Blink Source Counter */
3714 + BSC_STOP = 1<<0, /* Stop Blink Source Counter */
3715 +};
3716 +
3717 +/* B2_BSC_STAT 8 bit Blink Source Counter Status */
3718 +enum {
3719 + BSC_SRC = 1<<0, /* Blink Source, 0=Off / 1=On */
3720 +};
3721 +
3722 +/* B2_BSC_TST 16 bit Blink Source Counter Test Reg */
3723 +enum {
3724 + BSC_T_ON = 1<<2, /* Test mode on */
3725 + BSC_T_OFF = 1<<1, /* Test mode off */
3726 + BSC_T_STEP = 1<<0, /* Test step */
3727 +};
3728 +
3729 +/* B3_RAM_ADDR 32 bit RAM Address, to read or write */
3730 + /* Bit 31..19: reserved */
3731 +#define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
3732 +/* RAM Interface Registers */
3733 +
3734 +/* B3_RI_CTRL 16 bit RAM Iface Control Register */
3735 +enum {
3736 + RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
3737 + RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
3738 +
3739 + RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
3740 + RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
3741 +};
3742 +
3743 +/* MAC Arbiter Registers */
3744 +/* B3_MA_TO_CTRL 16 bit MAC Arbiter Timeout Ctrl Reg */
3745 +enum {
3746 + MA_FOE_ON = 1<<3, /* XMAC Fast Output Enable ON */
3747 + MA_FOE_OFF = 1<<2, /* XMAC Fast Output Enable OFF */
3748 + MA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
3749 + MA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
3750 +
3751 +};
3752 +
3753 +/* Timeout values */
3754 +#define SK_MAC_TO_53 72 /* MAC arbiter timeout */
3755 +#define SK_PKT_TO_53 0x2000 /* Packet arbiter timeout */
3756 +#define SK_PKT_TO_MAX 0xffff /* Maximum value */
3757 +#define SK_RI_TO_53 36 /* RAM interface timeout */
3758 +
3759 +/* Packet Arbiter Registers */
3760 +/* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */
3761 +enum {
3762 + PA_CLR_TO_TX2 = 1<<13, /* Clear IRQ Packet Timeout TX2 */
3763 + PA_CLR_TO_TX1 = 1<<12, /* Clear IRQ Packet Timeout TX1 */
3764 + PA_CLR_TO_RX2 = 1<<11, /* Clear IRQ Packet Timeout RX2 */
3765 + PA_CLR_TO_RX1 = 1<<10, /* Clear IRQ Packet Timeout RX1 */
3766 + PA_ENA_TO_TX2 = 1<<9, /* Enable Timeout Timer TX2 */
3767 + PA_DIS_TO_TX2 = 1<<8, /* Disable Timeout Timer TX2 */
3768 + PA_ENA_TO_TX1 = 1<<7, /* Enable Timeout Timer TX1 */
3769 + PA_DIS_TO_TX1 = 1<<6, /* Disable Timeout Timer TX1 */
3770 + PA_ENA_TO_RX2 = 1<<5, /* Enable Timeout Timer RX2 */
3771 + PA_DIS_TO_RX2 = 1<<4, /* Disable Timeout Timer RX2 */
3772 + PA_ENA_TO_RX1 = 1<<3, /* Enable Timeout Timer RX1 */
3773 + PA_DIS_TO_RX1 = 1<<2, /* Disable Timeout Timer RX1 */
3774 + PA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
3775 + PA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
3776 +};
3777 +
3778 +#define PA_ENA_TO_ALL (PA_ENA_TO_RX1 | PA_ENA_TO_RX2 |\
3779 + PA_ENA_TO_TX1 | PA_ENA_TO_TX2)
3780 +
3781 +
3782 +/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
3783 +/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
3784 +/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
3785 +/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
3786 +/* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
3787 +
3788 +#define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
3789 +
3790 +/* TXA_CTRL 8 bit Tx Arbiter Control Register */
3791 +enum {
3792 + TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
3793 + TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
3794 + TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
3795 + TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
3796 + TXA_START_RC = 1<<3, /* Start sync Rate Control */
3797 + TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
3798 + TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
3799 + TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
3800 +};
3801 +
3802 +/*
3803 + * Bank 4 - 5
3804 + */
3805 +/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
3806 +enum {
3807 + TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
3808 + TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
3809 + TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
3810 + TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
3811 + TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
3812 + TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
3813 + TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
3814 +};
3815 +
3816 +
3817 +enum {
3818 + B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
3819 + B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
3820 + B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
3821 + B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
3822 + B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
3823 + B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
3824 + B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
3825 + B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
3826 + B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
3827 +};
3828 +
3829 +/* Queue Register Offsets, use Q_ADDR() to access */
3830 +enum {
3831 + B8_Q_REGS = 0x0400, /* base of Queue registers */
3832 + Q_D = 0x00, /* 8*32 bit Current Descriptor */
3833 + Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */
3834 + Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */
3835 + Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
3836 + Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
3837 + Q_BC = 0x30, /* 32 bit Current Byte Counter */
3838 + Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
3839 + Q_F = 0x38, /* 32 bit Flag Register */
3840 + Q_T1 = 0x3c, /* 32 bit Test Register 1 */
3841 + Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */
3842 + Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */
3843 + Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */
3844 + Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */
3845 + Q_T2 = 0x40, /* 32 bit Test Register 2 */
3846 + Q_T3 = 0x44, /* 32 bit Test Register 3 */
3847 +
3848 +/* Yukon-2 */
3849 + Q_DONE = 0x24, /* 16 bit Done Index (Yukon-2 only) */
3850 + Q_WM = 0x40, /* 16 bit FIFO Watermark */
3851 + Q_AL = 0x42, /* 8 bit FIFO Alignment */
3852 + Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */
3853 + Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */
3854 + Q_RP = 0x48, /* 8 bit FIFO Read Pointer */
3855 + Q_RL = 0x4a, /* 8 bit FIFO Read Level */
3856 + Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */
3857 + Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */
3858 + Q_WL = 0x4e, /* 8 bit FIFO Write Level */
3859 + Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */
3860 +};
3861 +#define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
3862 +
3863 +/* RAM Buffer Register Offsets */
3864 +enum {
3865 +
3866 + RB_START = 0x00,/* 32 bit RAM Buffer Start Address */
3867 + RB_END = 0x04,/* 32 bit RAM Buffer End Address */
3868 + RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
3869 + RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
3870 + RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
3871 + RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
3872 + RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */
3873 + RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
3874 + /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
3875 + RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
3876 + RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
3877 + RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
3878 + RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
3879 + RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
3880 +};
3881 +
3882 +/* Receive and Transmit Queues */
3883 +enum {
3884 + Q_R1 = 0x0000, /* Receive Queue 1 */
3885 + Q_R2 = 0x0080, /* Receive Queue 2 */
3886 + Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
3887 + Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
3888 + Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
3889 + Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
3890 +};
3891 +
3892 +/* Different MAC Types */
3893 +enum {
3894 + SK_MAC_XMAC = 0, /* Xaqti XMAC II */
3895 + SK_MAC_GMAC = 1, /* Marvell GMAC */
3896 +};
3897 +
3898 +/* Different PHY Types */
3899 +enum {
3900 + SK_PHY_XMAC = 0,/* integrated in XMAC II */
3901 + SK_PHY_BCOM = 1,/* Broadcom BCM5400 */
3902 + SK_PHY_LONE = 2,/* Level One LXT1000 [not supported]*/
3903 + SK_PHY_NAT = 3,/* National DP83891 [not supported] */
3904 + SK_PHY_MARV_COPPER= 4,/* Marvell 88E1011S */
3905 + SK_PHY_MARV_FIBER = 5,/* Marvell 88E1011S working on fiber */
3906 +};
3907 +
3908 +/* PHY addresses (bits 12..8 of PHY address reg) */
3909 +enum {
3910 + PHY_ADDR_XMAC = 0<<8,
3911 + PHY_ADDR_BCOM = 1<<8,
3912 +
3913 +/* GPHY address (bits 15..11 of SMI control reg) */
3914 + PHY_ADDR_MARV = 0,
3915 +};
3916 +
3917 +#define RB_ADDR(offs, queue) (B16_RAM_REGS + (queue) + (offs))
3918 +
3919 +/* Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only) */
3920 +enum {
3921 + RX_MFF_EA = 0x0c00,/* 32 bit Receive MAC FIFO End Address */
3922 + RX_MFF_WP = 0x0c04,/* 32 bit Receive MAC FIFO Write Pointer */
3923 +
3924 + RX_MFF_RP = 0x0c0c,/* 32 bit Receive MAC FIFO Read Pointer */
3925 + RX_MFF_PC = 0x0c10,/* 32 bit Receive MAC FIFO Packet Cnt */
3926 + RX_MFF_LEV = 0x0c14,/* 32 bit Receive MAC FIFO Level */
3927 + RX_MFF_CTRL1 = 0x0c18,/* 16 bit Receive MAC FIFO Control Reg 1*/
3928 + RX_MFF_STAT_TO = 0x0c1a,/* 8 bit Receive MAC Status Timeout */
3929 + RX_MFF_TIST_TO = 0x0c1b,/* 8 bit Receive MAC Time Stamp Timeout */
3930 + RX_MFF_CTRL2 = 0x0c1c,/* 8 bit Receive MAC FIFO Control Reg 2*/
3931 + RX_MFF_TST1 = 0x0c1d,/* 8 bit Receive MAC FIFO Test Reg 1 */
3932 + RX_MFF_TST2 = 0x0c1e,/* 8 bit Receive MAC FIFO Test Reg 2 */
3933 +
3934 + RX_LED_INI = 0x0c20,/* 32 bit Receive LED Cnt Init Value */
3935 + RX_LED_VAL = 0x0c24,/* 32 bit Receive LED Cnt Current Value */
3936 + RX_LED_CTRL = 0x0c28,/* 8 bit Receive LED Cnt Control Reg */
3937 + RX_LED_TST = 0x0c29,/* 8 bit Receive LED Cnt Test Register */
3938 +
3939 + LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
3940 + LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
3941 + LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
3942 + LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
3943 + LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
3944 +};
3945 +
3946 +/* Receive and Transmit MAC FIFO Registers (GENESIS only) */
3947 +/* RX_MFF_CTRL1 16 bit Receive MAC FIFO Control Reg 1 */
3948 +enum {
3949 + MFF_ENA_RDY_PAT = 1<<13, /* Enable Ready Patch */
3950 + MFF_DIS_RDY_PAT = 1<<12, /* Disable Ready Patch */
3951 + MFF_ENA_TIM_PAT = 1<<11, /* Enable Timing Patch */
3952 + MFF_DIS_TIM_PAT = 1<<10, /* Disable Timing Patch */
3953 + MFF_ENA_ALM_FUL = 1<<9, /* Enable AlmostFull Sign */
3954 + MFF_DIS_ALM_FUL = 1<<8, /* Disable AlmostFull Sign */
3955 + MFF_ENA_PAUSE = 1<<7, /* Enable Pause Signaling */
3956 + MFF_DIS_PAUSE = 1<<6, /* Disable Pause Signaling */
3957 + MFF_ENA_FLUSH = 1<<5, /* Enable Frame Flushing */
3958 + MFF_DIS_FLUSH = 1<<4, /* Disable Frame Flushing */
3959 + MFF_ENA_TIST = 1<<3, /* Enable Time Stamp Gener */
3960 + MFF_DIS_TIST = 1<<2, /* Disable Time Stamp Gener */
3961 + MFF_CLR_INTIST = 1<<1, /* Clear IRQ No Time Stamp */
3962 + MFF_CLR_INSTAT = 1<<0, /* Clear IRQ No Status */
3963 +#define MFF_RX_CTRL_DEF MFF_ENA_TIM_PAT
3964 +};
3965 +
3966 +/* TX_MFF_CTRL1 16 bit Transmit MAC FIFO Control Reg 1 */
3967 +enum {
3968 + MFF_CLR_PERR = 1<<15, /* Clear Parity Error IRQ */
3969 + /* Bit 14: reserved */
3970 + MFF_ENA_PKT_REC = 1<<13, /* Enable Packet Recovery */
3971 + MFF_DIS_PKT_REC = 1<<12, /* Disable Packet Recovery */
3972 +
3973 + MFF_ENA_W4E = 1<<7, /* Enable Wait for Empty */
3974 + MFF_DIS_W4E = 1<<6, /* Disable Wait for Empty */
3975 +
3976 + MFF_ENA_LOOPB = 1<<3, /* Enable Loopback */
3977 + MFF_DIS_LOOPB = 1<<2, /* Disable Loopback */
3978 + MFF_CLR_MAC_RST = 1<<1, /* Clear XMAC Reset */
3979 + MFF_SET_MAC_RST = 1<<0, /* Set XMAC Reset */
3980 +};
3981 +
3982 +#define MFF_TX_CTRL_DEF (MFF_ENA_PKT_REC | MFF_ENA_TIM_PAT | MFF_ENA_FLUSH)
3983 +
3984 +/* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */
3985 +/* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */
3986 +enum {
3987 + MFF_WSP_T_ON = 1<<6, /* Tx: Write Shadow Ptr TestOn */
3988 + MFF_WSP_T_OFF = 1<<5, /* Tx: Write Shadow Ptr TstOff */
3989 + MFF_WSP_INC = 1<<4, /* Tx: Write Shadow Ptr Increment */
3990 + MFF_PC_DEC = 1<<3, /* Packet Counter Decrement */
3991 + MFF_PC_T_ON = 1<<2, /* Packet Counter Test On */
3992 + MFF_PC_T_OFF = 1<<1, /* Packet Counter Test Off */
3993 + MFF_PC_INC = 1<<0, /* Packet Counter Increment */
3994 +};
3995 +
3996 +/* RX_MFF_TST1 8 bit Receive MAC FIFO Test Register 1 */
3997 +/* TX_MFF_TST1 8 bit Transmit MAC FIFO Test Register 1 */
3998 +enum {
3999 + MFF_WP_T_ON = 1<<6, /* Write Pointer Test On */
4000 + MFF_WP_T_OFF = 1<<5, /* Write Pointer Test Off */
4001 + MFF_WP_INC = 1<<4, /* Write Pointer Increm */
4002 +
4003 + MFF_RP_T_ON = 1<<2, /* Read Pointer Test On */
4004 + MFF_RP_T_OFF = 1<<1, /* Read Pointer Test Off */
4005 + MFF_RP_DEC = 1<<0, /* Read Pointer Decrement */
4006 +};
4007 +
4008 +/* RX_MFF_CTRL2 8 bit Receive MAC FIFO Control Reg 2 */
4009 +/* TX_MFF_CTRL2 8 bit Transmit MAC FIFO Control Reg 2 */
4010 +enum {
4011 + MFF_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
4012 + MFF_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
4013 + MFF_RST_CLR = 1<<1, /* Clear MAC FIFO Reset */
4014 + MFF_RST_SET = 1<<0, /* Set MAC FIFO Reset */
4015 +};
4016 +
4017 +
4018 +/* Link LED Counter Registers (GENESIS only) */
4019 +
4020 +/* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */
4021 +/* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */
4022 +/* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */
4023 +enum {
4024 + LED_START = 1<<2, /* Start Timer */
4025 + LED_STOP = 1<<1, /* Stop Timer */
4026 + LED_STATE = 1<<0, /* Rx/Tx: LED State, 1=LED on */
4027 +};
4028 +
4029 +/* RX_LED_TST 8 bit Receive LED Cnt Test Register */
4030 +/* TX_LED_TST 8 bit Transmit LED Cnt Test Register */
4031 +/* LNK_SYNC_TST 8 bit Link Sync Cnt Test Register */
4032 +enum {
4033 + LED_T_ON = 1<<2, /* LED Counter Test mode On */
4034 + LED_T_OFF = 1<<1, /* LED Counter Test mode Off */
4035 + LED_T_STEP = 1<<0, /* LED Counter Step */
4036 +};
4037 +
4038 +/* LNK_LED_REG 8 bit Link LED Register */
4039 +enum {
4040 + LED_BLK_ON = 1<<5, /* Link LED Blinking On */
4041 + LED_BLK_OFF = 1<<4, /* Link LED Blinking Off */
4042 + LED_SYNC_ON = 1<<3, /* Use Sync Wire to switch LED */
4043 + LED_SYNC_OFF = 1<<2, /* Disable Sync Wire Input */
4044 + LED_ON = 1<<1, /* switch LED on */
4045 + LED_OFF = 1<<0, /* switch LED off */
4046 +};
4047 +
4048 +/* Receive GMAC FIFO (YUKON and Yukon-2) */
4049 +enum {
4050 + RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
4051 + RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
4052 + RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
4053 + RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
4054 + RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
4055 + RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
4056 +
4057 + RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
4058 + RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
4059 +
4060 + RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
4061 +
4062 + RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
4063 +
4064 + RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
4065 +};
4066 +
4067 +
4068 +/* TXA_TEST 8 bit Tx Arbiter Test Register */
4069 +enum {
4070 + TXA_INT_T_ON = 1<<5, /* Tx Arb Interval Timer Test On */
4071 + TXA_INT_T_OFF = 1<<4, /* Tx Arb Interval Timer Test Off */
4072 + TXA_INT_T_STEP = 1<<3, /* Tx Arb Interval Timer Step */
4073 + TXA_LIM_T_ON = 1<<2, /* Tx Arb Limit Timer Test On */
4074 + TXA_LIM_T_OFF = 1<<1, /* Tx Arb Limit Timer Test Off */
4075 + TXA_LIM_T_STEP = 1<<0, /* Tx Arb Limit Timer Step */
4076 +};
4077 +
4078 +/* TXA_STAT 8 bit Tx Arbiter Status Register */
4079 +enum {
4080 + TXA_PRIO_XS = 1<<0, /* sync queue has prio to send */
4081 +};
4082 +
4083 +
4084 +/* Q_BC 32 bit Current Byte Counter */
4085 +
4086 +/* BMU Control Status Registers */
4087 +/* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
4088 +/* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
4089 +/* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
4090 +/* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
4091 +/* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
4092 +/* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
4093 +/* Q_CSR 32 bit BMU Control/Status Register */
4094 +
4095 +enum {
4096 + CSR_SV_IDLE = 1<<24, /* BMU SM Idle */
4097 +
4098 + CSR_DESC_CLR = 1<<21, /* Clear Reset for Descr */
4099 + CSR_DESC_SET = 1<<20, /* Set Reset for Descr */
4100 + CSR_FIFO_CLR = 1<<19, /* Clear Reset for FIFO */
4101 + CSR_FIFO_SET = 1<<18, /* Set Reset for FIFO */
4102 + CSR_HPI_RUN = 1<<17, /* Release HPI SM */
4103 + CSR_HPI_RST = 1<<16, /* Reset HPI SM to Idle */
4104 + CSR_SV_RUN = 1<<15, /* Release Supervisor SM */
4105 + CSR_SV_RST = 1<<14, /* Reset Supervisor SM */
4106 + CSR_DREAD_RUN = 1<<13, /* Release Descr Read SM */
4107 + CSR_DREAD_RST = 1<<12, /* Reset Descr Read SM */
4108 + CSR_DWRITE_RUN = 1<<11, /* Release Descr Write SM */
4109 + CSR_DWRITE_RST = 1<<10, /* Reset Descr Write SM */
4110 + CSR_TRANS_RUN = 1<<9, /* Release Transfer SM */
4111 + CSR_TRANS_RST = 1<<8, /* Reset Transfer SM */
4112 + CSR_ENA_POL = 1<<7, /* Enable Descr Polling */
4113 + CSR_DIS_POL = 1<<6, /* Disable Descr Polling */
4114 + CSR_STOP = 1<<5, /* Stop Rx/Tx Queue */
4115 + CSR_START = 1<<4, /* Start Rx/Tx Queue */
4116 + CSR_IRQ_CL_P = 1<<3, /* (Rx) Clear Parity IRQ */
4117 + CSR_IRQ_CL_B = 1<<2, /* Clear EOB IRQ */
4118 + CSR_IRQ_CL_F = 1<<1, /* Clear EOF IRQ */
4119 + CSR_IRQ_CL_C = 1<<0, /* Clear ERR IRQ */
4120 +};
4121 +
4122 +#define CSR_SET_RESET (CSR_DESC_SET | CSR_FIFO_SET | CSR_HPI_RST |\
4123 + CSR_SV_RST | CSR_DREAD_RST | CSR_DWRITE_RST |\
4124 + CSR_TRANS_RST)
4125 +#define CSR_CLR_RESET (CSR_DESC_CLR | CSR_FIFO_CLR | CSR_HPI_RUN |\
4126 + CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\
4127 + CSR_TRANS_RUN)
4128 +
4129 +/* Q_F 32 bit Flag Register */
4130 +enum {
4131 + F_ALM_FULL = 1<<27, /* Rx FIFO: almost full */
4132 + F_EMPTY = 1<<27, /* Tx FIFO: empty flag */
4133 + F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */
4134 + F_WM_REACHED = 1<<25, /* Watermark reached */
4135 +
4136 + F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */
4137 + F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */
4138 +};
4139 +
4140 +/* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
4141 +/* RB_START 32 bit RAM Buffer Start Address */
4142 +/* RB_END 32 bit RAM Buffer End Address */
4143 +/* RB_WP 32 bit RAM Buffer Write Pointer */
4144 +/* RB_RP 32 bit RAM Buffer Read Pointer */
4145 +/* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
4146 +/* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
4147 +/* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
4148 +/* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
4149 +/* RB_PC 32 bit RAM Buffer Packet Counter */
4150 +/* RB_LEV 32 bit RAM Buffer Level Register */
4151 +
4152 +#define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
4153 +/* RB_TST2 8 bit RAM Buffer Test Register 2 */
4154 +/* RB_TST1 8 bit RAM Buffer Test Register 1 */
4155 +
4156 +/* RB_CTRL 8 bit RAM Buffer Control Register */
4157 +enum {
4158 + RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
4159 + RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
4160 + RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
4161 + RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
4162 + RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
4163 + RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
4164 +};
4165 +
4166 +/* Transmit MAC FIFO and Transmit LED Registers (GENESIS only), */
4167 +enum {
4168 + TX_MFF_EA = 0x0d00,/* 32 bit Transmit MAC FIFO End Address */
4169 + TX_MFF_WP = 0x0d04,/* 32 bit Transmit MAC FIFO WR Pointer */
4170 + TX_MFF_WSP = 0x0d08,/* 32 bit Transmit MAC FIFO WR Shadow Ptr */
4171 + TX_MFF_RP = 0x0d0c,/* 32 bit Transmit MAC FIFO RD Pointer */
4172 + TX_MFF_PC = 0x0d10,/* 32 bit Transmit MAC FIFO Packet Cnt */
4173 + TX_MFF_LEV = 0x0d14,/* 32 bit Transmit MAC FIFO Level */
4174 + TX_MFF_CTRL1 = 0x0d18,/* 16 bit Transmit MAC FIFO Ctrl Reg 1 */
4175 + TX_MFF_WAF = 0x0d1a,/* 8 bit Transmit MAC Wait after flush */
4176 +
4177 + TX_MFF_CTRL2 = 0x0d1c,/* 8 bit Transmit MAC FIFO Ctrl Reg 2 */
4178 + TX_MFF_TST1 = 0x0d1d,/* 8 bit Transmit MAC FIFO Test Reg 1 */
4179 + TX_MFF_TST2 = 0x0d1e,/* 8 bit Transmit MAC FIFO Test Reg 2 */
4180 +
4181 + TX_LED_INI = 0x0d20,/* 32 bit Transmit LED Cnt Init Value */
4182 + TX_LED_VAL = 0x0d24,/* 32 bit Transmit LED Cnt Current Val */
4183 + TX_LED_CTRL = 0x0d28,/* 8 bit Transmit LED Cnt Control Reg */
4184 + TX_LED_TST = 0x0d29,/* 8 bit Transmit LED Cnt Test Reg */
4185 +};
4186 +
4187 +/* Counter and Timer constants, for a host clock of 62.5 MHz */
4188 +#define SK_XMIT_DUR 0x002faf08UL /* 50 ms */
4189 +#define SK_BLK_DUR 0x01dcd650UL /* 500 ms */
4190 +
4191 +#define SK_DPOLL_DEF 0x00ee6b28UL /* 250 ms at 62.5 MHz */
4192 +
4193 +#define SK_DPOLL_MAX 0x00ffffffUL /* 268 ms at 62.5 MHz */
4194 + /* 215 ms at 78.12 MHz */
4195 +
4196 +#define SK_FACT_62 100 /* is given in percent */
4197 +#define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */
4198 +#define SK_FACT_78 125 /* on YUKON: 78.12 MHz */
4199 +
4200 +
4201 +/* Transmit GMAC FIFO (YUKON only) */
4202 +enum {
4203 + TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
4204 + TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
4205 + TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
4206 +
4207 + TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
4208 + TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
4209 + TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
4210 +
4211 + TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
4212 + TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
4213 + TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
4214 +
4215 + /* Descriptor Poll Timer Registers */
4216 + B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
4217 + B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
4218 + B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
4219 +
4220 + B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
4221 +
4222 + /* Time Stamp Timer Registers (YUKON only) */
4223 + GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
4224 + GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
4225 + GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
4226 +};
4227 +
4228 +/* Status BMU Registers (Yukon-2 only)*/
4229 +enum {
4230 + STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */
4231 + STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */
4232 + /* 0x0e85 - 0x0e86: reserved */
4233 + STAT_LIST_ADDR_LO = 0x0e88,/* 32 bit Status List Start Addr (low) */
4234 + STAT_LIST_ADDR_HI = 0x0e8c,/* 32 bit Status List Start Addr (high) */
4235 + STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */
4236 + STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */
4237 + STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */
4238 + STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */
4239 + STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */
4240 + STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */
4241 +
4242 +/* FIFO Control/Status Registers (Yukon-2 only)*/
4243 + STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */
4244 + STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */
4245 + STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */
4246 + STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */
4247 + STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */
4248 + STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */
4249 + STAT_FIFO_ISR_WM = 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */
4250 +
4251 +/* Level and ISR Timer Registers (Yukon-2 only)*/
4252 + STAT_LEV_TIMER_INI = 0x0eb0,/* 32 bit Level Timer Init. Value Reg */
4253 + STAT_LEV_TIMER_CNT = 0x0eb4,/* 32 bit Level Timer Counter Reg */
4254 + STAT_LEV_TIMER_CTRL = 0x0eb8,/* 8 bit Level Timer Control Reg */
4255 + STAT_LEV_TIMER_TEST = 0x0eb9,/* 8 bit Level Timer Test Reg */
4256 + STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */
4257 + STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */
4258 + STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */
4259 + STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */
4260 + STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */
4261 + STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */
4262 + STAT_ISR_TIMER_CTRL = 0x0ed8,/* 8 bit ISR Timer Control Reg */
4263 + STAT_ISR_TIMER_TEST = 0x0ed9,/* 8 bit ISR Timer Test Reg */
4264 +
4265 + ST_LAST_IDX_MASK = 0x007f,/* Last Index Mask */
4266 + ST_TXRP_IDX_MASK = 0x0fff,/* Tx Report Index Mask */
4267 + ST_TXTH_IDX_MASK = 0x0fff,/* Tx Threshold Index Mask */
4268 + ST_WM_IDX_MASK = 0x3f,/* FIFO Watermark Index Mask */
4269 +};
4270 +
4271 +enum {
4272 + LINKLED_OFF = 0x01,
4273 + LINKLED_ON = 0x02,
4274 + LINKLED_LINKSYNC_OFF = 0x04,
4275 + LINKLED_LINKSYNC_ON = 0x08,
4276 + LINKLED_BLINK_OFF = 0x10,
4277 + LINKLED_BLINK_ON = 0x20,
4278 +};
4279 +
4280 +/* GMAC and GPHY Control Registers (YUKON only) */
4281 +enum {
4282 + GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
4283 + GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
4284 + GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
4285 + GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
4286 + GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
4287 +
4288 +/* Wake-up Frame Pattern Match Control Registers (YUKON only) */
4289 +
4290 + WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
4291 +
4292 + WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
4293 + WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
4294 + WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
4295 + WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
4296 + WOL_PATT_PME = 0x0f2a,/* 8 bit WOL PME Match Enable (Yukon-2) */
4297 + WOL_PATT_ASFM = 0x0f2b,/* 8 bit WOL ASF Match Enable (Yukon-2) */
4298 + WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
4299 +
4300 +/* WOL Pattern Length Registers (YUKON only) */
4301 +
4302 + WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
4303 + WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
4304 +
4305 +/* WOL Pattern Counter Registers (YUKON only) */
4306 +
4307 + WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
4308 + WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
4309 +};
4310 +
4311 +enum {
4312 + WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
4313 + WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
4314 +};
4315 +
4316 +enum {
4317 + BASE_XMAC_1 = 0x2000,/* XMAC 1 registers */
4318 + BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
4319 + BASE_XMAC_2 = 0x3000,/* XMAC 2 registers */
4320 + BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
4321 +};
4322 +
4323 +/*
4324 + * Receive Frame Status Encoding
4325 + */
4326 +enum {
4327 + XMR_FS_LEN = 0x3fff<<18, /* Bit 31..18: Rx Frame Length */
4328 + XMR_FS_2L_VLAN = 1<<17, /* Bit 17: tagged wh 2Lev VLAN ID*/
4329 + XMR_FS_1_VLAN = 1<<16, /* Bit 16: tagged wh 1ev VLAN ID*/
4330 + XMR_FS_BC = 1<<15, /* Bit 15: Broadcast Frame */
4331 + XMR_FS_MC = 1<<14, /* Bit 14: Multicast Frame */
4332 + XMR_FS_UC = 1<<13, /* Bit 13: Unicast Frame */
4333 +
4334 + XMR_FS_BURST = 1<<11, /* Bit 11: Burst Mode */
4335 + XMR_FS_CEX_ERR = 1<<10, /* Bit 10: Carrier Ext. Error */
4336 + XMR_FS_802_3 = 1<<9, /* Bit 9: 802.3 Frame */
4337 + XMR_FS_COL_ERR = 1<<8, /* Bit 8: Collision Error */
4338 + XMR_FS_CAR_ERR = 1<<7, /* Bit 7: Carrier Event Error */
4339 + XMR_FS_LEN_ERR = 1<<6, /* Bit 6: In-Range Length Error */
4340 + XMR_FS_FRA_ERR = 1<<5, /* Bit 5: Framing Error */
4341 + XMR_FS_RUNT = 1<<4, /* Bit 4: Runt Frame */
4342 + XMR_FS_LNG_ERR = 1<<3, /* Bit 3: Giant (Jumbo) Frame */
4343 + XMR_FS_FCS_ERR = 1<<2, /* Bit 2: Frame Check Sequ Err */
4344 + XMR_FS_ERR = 1<<1, /* Bit 1: Frame Error */
4345 + XMR_FS_MCTRL = 1<<0, /* Bit 0: MAC Control Packet */
4346 +
4347 +/*
4348 + * XMR_FS_ERR will be set if
4349 + * XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT,
4350 + * XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR_FS_CEX_ERR
4351 + * is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR will issue
4352 + * XMR_FS_ERR unless the corresponding bit in the Receive Command
4353 + * Register is set.
4354 + */
4355 +};
4356 +
4357 +/*
4358 +,* XMAC-PHY Registers, indirect addressed over the XMAC
4359 + */
4360 +enum {
4361 + PHY_XMAC_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
4362 + PHY_XMAC_STAT = 0x01,/* 16 bit r/w PHY Status Register */
4363 + PHY_XMAC_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
4364 + PHY_XMAC_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
4365 + PHY_XMAC_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
4366 + PHY_XMAC_AUNE_LP = 0x05,/* 16 bit r/o Link Partner Abi Reg */
4367 + PHY_XMAC_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
4368 + PHY_XMAC_NEPG = 0x07,/* 16 bit r/w Next Page Register */
4369 + PHY_XMAC_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
4370 +
4371 + PHY_XMAC_EXT_STAT = 0x0f,/* 16 bit r/o Ext Status Register */
4372 + PHY_XMAC_RES_ABI = 0x10,/* 16 bit r/o PHY Resolved Ability */
4373 +};
4374 +/*
4375 + * Broadcom-PHY Registers, indirect addressed over XMAC
4376 + */
4377 +enum {
4378 + PHY_BCOM_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
4379 + PHY_BCOM_STAT = 0x01,/* 16 bit r/o PHY Status Register */
4380 + PHY_BCOM_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
4381 + PHY_BCOM_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
4382 + PHY_BCOM_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
4383 + PHY_BCOM_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
4384 + PHY_BCOM_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
4385 + PHY_BCOM_NEPG = 0x07,/* 16 bit r/w Next Page Register */
4386 + PHY_BCOM_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
4387 + /* Broadcom-specific registers */
4388 + PHY_BCOM_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
4389 + PHY_BCOM_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
4390 + PHY_BCOM_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
4391 + PHY_BCOM_P_EXT_CTRL = 0x10,/* 16 bit r/w PHY Extended Ctrl Reg */
4392 + PHY_BCOM_P_EXT_STAT = 0x11,/* 16 bit r/o PHY Extended Stat Reg */
4393 + PHY_BCOM_RE_CTR = 0x12,/* 16 bit r/w Receive Error Counter */
4394 + PHY_BCOM_FC_CTR = 0x13,/* 16 bit r/w False Carrier Sense Cnt */
4395 + PHY_BCOM_RNO_CTR = 0x14,/* 16 bit r/w Receiver NOT_OK Cnt */
4396 +
4397 + PHY_BCOM_AUX_CTRL = 0x18,/* 16 bit r/w Auxiliary Control Reg */
4398 + PHY_BCOM_AUX_STAT = 0x19,/* 16 bit r/o Auxiliary Stat Summary */
4399 + PHY_BCOM_INT_STAT = 0x1a,/* 16 bit r/o Interrupt Status Reg */
4400 + PHY_BCOM_INT_MASK = 0x1b,/* 16 bit r/w Interrupt Mask Reg */
4401 +};
4402 +
4403 +/*
4404 + * Marvel-PHY Registers, indirect addressed over GMAC
4405 + */
4406 +enum {
4407 + PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
4408 + PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
4409 + PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
4410 + PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
4411 + PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
4412 + PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
4413 + PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
4414 + PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
4415 + PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
4416 + /* Marvel-specific registers */
4417 + PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
4418 + PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
4419 + PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
4420 + PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
4421 + PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
4422 + PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
4423 + PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
4424 + PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
4425 + PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
4426 + PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
4427 + PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
4428 + PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
4429 + PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
4430 + PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
4431 + PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
4432 + PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
4433 + PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
4434 + PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
4435 +
4436 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
4437 + PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
4438 + PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
4439 + PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
4440 + PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
4441 + PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
4442 +};
4443 +
4444 +enum {
4445 + PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
4446 + PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
4447 + PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
4448 + PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
4449 + PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
4450 + PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
4451 + PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
4452 + PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
4453 + PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
4454 + PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
4455 +};
4456 +
4457 +enum {
4458 + PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
4459 + PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
4460 + PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
4461 +};
4462 +
4463 +enum {
4464 + PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
4465 +
4466 + PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
4467 + PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
4468 + PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */
4469 + PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
4470 + PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
4471 + PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
4472 + PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
4473 +};
4474 +
4475 +enum {
4476 + PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
4477 + PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
4478 + PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
4479 +};
4480 +
4481 +/* different Broadcom PHY Ids */
4482 +enum {
4483 + PHY_BCOM_ID1_A1 = 0x6041,
4484 + PHY_BCOM_ID1_B2 = 0x6043,
4485 + PHY_BCOM_ID1_C0 = 0x6044,
4486 + PHY_BCOM_ID1_C5 = 0x6047,
4487 +};
4488 +
4489 +/* different Marvell PHY Ids */
4490 +enum {
4491 + PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
4492 + PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
4493 + PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
4494 + PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
4495 + PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
4496 +};
4497 +
4498 +/* Advertisement register bits */
4499 +enum {
4500 + PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
4501 + PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
4502 + PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */
4503 +
4504 + PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
4505 + PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */
4506 + PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */
4507 + PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
4508 + PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
4509 + PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
4510 + PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
4511 + PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
4512 + PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
4513 + PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
4514 + PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL |
4515 + PHY_AN_100HALF | PHY_AN_100FULL,
4516 +};
4517 +
4518 +/* Xmac Specific */
4519 +enum {
4520 + PHY_X_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
4521 + PHY_X_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
4522 + PHY_X_AN_RFB = 3<<12,/* Bit 13..12: Remote Fault Bits */
4523 +
4524 + PHY_X_AN_PAUSE = 3<<7,/* Bit 8.. 7: Pause Bits */
4525 + PHY_X_AN_HD = 1<<6, /* Bit 6: Half Duplex */
4526 + PHY_X_AN_FD = 1<<5, /* Bit 5: Full Duplex */
4527 +};
4528 +
4529 +/* Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding */
4530 +enum {
4531 + PHY_X_P_NO_PAUSE = 0<<7,/* Bit 8..7: no Pause Mode */
4532 + PHY_X_P_SYM_MD = 1<<7, /* Bit 8..7: symmetric Pause Mode */
4533 + PHY_X_P_ASYM_MD = 2<<7,/* Bit 8..7: asymmetric Pause Mode */
4534 + PHY_X_P_BOTH_MD = 3<<7,/* Bit 8..7: both Pause Mode */
4535 +};
4536 +
4537 +
4538 +/* Broadcom-Specific */
4539 +/***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
4540 +enum {
4541 + PHY_B_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
4542 + PHY_B_1000C_MSE = 1<<12, /* Bit 12: Master/Slave Enable */
4543 + PHY_B_1000C_MSC = 1<<11, /* Bit 11: M/S Configuration */
4544 + PHY_B_1000C_RD = 1<<10, /* Bit 10: Repeater/DTE */
4545 + PHY_B_1000C_AFD = 1<<9, /* Bit 9: Advertise Full Duplex */
4546 + PHY_B_1000C_AHD = 1<<8, /* Bit 8: Advertise Half Duplex */
4547 +};
4548 +
4549 +/***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
4550 +/***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
4551 +enum {
4552 + PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
4553 + PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
4554 + PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
4555 + PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
4556 + PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
4557 + PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
4558 + /* Bit 9..8: reserved */
4559 + PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
4560 +};
4561 +
4562 +/***** PHY_BCOM_EXT_STAT 16 bit r/o Extended Status Register *****/
4563 +enum {
4564 + PHY_B_ES_X_FD_CAP = 1<<15, /* Bit 15: 1000Base-X FD capable */
4565 + PHY_B_ES_X_HD_CAP = 1<<14, /* Bit 14: 1000Base-X HD capable */
4566 + PHY_B_ES_T_FD_CAP = 1<<13, /* Bit 13: 1000Base-T FD capable */
4567 + PHY_B_ES_T_HD_CAP = 1<<12, /* Bit 12: 1000Base-T HD capable */
4568 +};
4569 +
4570 +/***** PHY_BCOM_P_EXT_CTRL 16 bit r/w PHY Extended Control Reg *****/
4571 +enum {
4572 + PHY_B_PEC_MAC_PHY = 1<<15, /* Bit 15: 10BIT/GMI-Interface */
4573 + PHY_B_PEC_DIS_CROSS = 1<<14, /* Bit 14: Disable MDI Crossover */
4574 + PHY_B_PEC_TX_DIS = 1<<13, /* Bit 13: Tx output Disabled */
4575 + PHY_B_PEC_INT_DIS = 1<<12, /* Bit 12: Interrupts Disabled */
4576 + PHY_B_PEC_F_INT = 1<<11, /* Bit 11: Force Interrupt */
4577 + PHY_B_PEC_BY_45 = 1<<10, /* Bit 10: Bypass 4B5B-Decoder */
4578 + PHY_B_PEC_BY_SCR = 1<<9, /* Bit 9: Bypass Scrambler */
4579 + PHY_B_PEC_BY_MLT3 = 1<<8, /* Bit 8: Bypass MLT3 Encoder */
4580 + PHY_B_PEC_BY_RXA = 1<<7, /* Bit 7: Bypass Rx Alignm. */
4581 + PHY_B_PEC_RES_SCR = 1<<6, /* Bit 6: Reset Scrambler */
4582 + PHY_B_PEC_EN_LTR = 1<<5, /* Bit 5: Ena LED Traffic Mode */
4583 + PHY_B_PEC_LED_ON = 1<<4, /* Bit 4: Force LED's on */
4584 + PHY_B_PEC_LED_OFF = 1<<3, /* Bit 3: Force LED's off */
4585 + PHY_B_PEC_EX_IPG = 1<<2, /* Bit 2: Extend Tx IPG Mode */
4586 + PHY_B_PEC_3_LED = 1<<1, /* Bit 1: Three Link LED mode */
4587 + PHY_B_PEC_HIGH_LA = 1<<0, /* Bit 0: GMII FIFO Elasticy */
4588 +};
4589 +
4590 +/***** PHY_BCOM_P_EXT_STAT 16 bit r/o PHY Extended Status Reg *****/
4591 +enum {
4592 + PHY_B_PES_CROSS_STAT = 1<<13, /* Bit 13: MDI Crossover Status */
4593 + PHY_B_PES_INT_STAT = 1<<12, /* Bit 12: Interrupt Status */
4594 + PHY_B_PES_RRS = 1<<11, /* Bit 11: Remote Receiver Stat. */
4595 + PHY_B_PES_LRS = 1<<10, /* Bit 10: Local Receiver Stat. */
4596 + PHY_B_PES_LOCKED = 1<<9, /* Bit 9: Locked */
4597 + PHY_B_PES_LS = 1<<8, /* Bit 8: Link Status */
4598 + PHY_B_PES_RF = 1<<7, /* Bit 7: Remote Fault */
4599 + PHY_B_PES_CE_ER = 1<<6, /* Bit 6: Carrier Ext Error */
4600 + PHY_B_PES_BAD_SSD = 1<<5, /* Bit 5: Bad SSD */
4601 + PHY_B_PES_BAD_ESD = 1<<4, /* Bit 4: Bad ESD */
4602 + PHY_B_PES_RX_ER = 1<<3, /* Bit 3: Receive Error */
4603 + PHY_B_PES_TX_ER = 1<<2, /* Bit 2: Transmit Error */
4604 + PHY_B_PES_LOCK_ER = 1<<1, /* Bit 1: Lock Error */
4605 + PHY_B_PES_MLT3_ER = 1<<0, /* Bit 0: MLT3 code Error */
4606 +};
4607 +
4608 +/* PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
4609 +/* PHY_BCOM_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/
4610 +enum {
4611 + PHY_B_AN_RF = 1<<13, /* Bit 13: Remote Fault */
4612 +
4613 + PHY_B_AN_ASP = 1<<11, /* Bit 11: Asymmetric Pause */
4614 + PHY_B_AN_PC = 1<<10, /* Bit 10: Pause Capable */
4615 +};
4616 +
4617 +
4618 +/***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/
4619 +enum {
4620 + PHY_B_FC_CTR = 0xff, /* Bit 7..0: False Carrier Counter */
4621 +
4622 +/***** PHY_BCOM_RNO_CTR 16 bit r/w Receive NOT_OK Counter *****/
4623 + PHY_B_RC_LOC_MSK = 0xff00, /* Bit 15..8: Local Rx NOT_OK cnt */
4624 + PHY_B_RC_REM_MSK = 0x00ff, /* Bit 7..0: Remote Rx NOT_OK cnt */
4625 +
4626 +/***** PHY_BCOM_AUX_CTRL 16 bit r/w Auxiliary Control Reg *****/
4627 + PHY_B_AC_L_SQE = 1<<15, /* Bit 15: Low Squelch */
4628 + PHY_B_AC_LONG_PACK = 1<<14, /* Bit 14: Rx Long Packets */
4629 + PHY_B_AC_ER_CTRL = 3<<12,/* Bit 13..12: Edgerate Control */
4630 + /* Bit 11: reserved */
4631 + PHY_B_AC_TX_TST = 1<<10, /* Bit 10: Tx test bit, always 1 */
4632 + /* Bit 9.. 8: reserved */
4633 + PHY_B_AC_DIS_PRF = 1<<7, /* Bit 7: dis part resp filter */
4634 + /* Bit 6: reserved */
4635 + PHY_B_AC_DIS_PM = 1<<5, /* Bit 5: dis power management */
4636 + /* Bit 4: reserved */
4637 + PHY_B_AC_DIAG = 1<<3, /* Bit 3: Diagnostic Mode */
4638 +};
4639 +
4640 +/***** PHY_BCOM_AUX_STAT 16 bit r/o Auxiliary Status Reg *****/
4641 +enum {
4642 + PHY_B_AS_AN_C = 1<<15, /* Bit 15: AutoNeg complete */
4643 + PHY_B_AS_AN_CA = 1<<14, /* Bit 14: AN Complete Ack */
4644 + PHY_B_AS_ANACK_D = 1<<13, /* Bit 13: AN Ack Detect */
4645 + PHY_B_AS_ANAB_D = 1<<12, /* Bit 12: AN Ability Detect */
4646 + PHY_B_AS_NPW = 1<<11, /* Bit 11: AN Next Page Wait */
4647 + PHY_B_AS_AN_RES_MSK = 7<<8,/* Bit 10..8: AN HDC */
4648 + PHY_B_AS_PDF = 1<<7, /* Bit 7: Parallel Detect. Fault */
4649 + PHY_B_AS_RF = 1<<6, /* Bit 6: Remote Fault */
4650 + PHY_B_AS_ANP_R = 1<<5, /* Bit 5: AN Page Received */
4651 + PHY_B_AS_LP_ANAB = 1<<4, /* Bit 4: LP AN Ability */
4652 + PHY_B_AS_LP_NPAB = 1<<3, /* Bit 3: LP Next Page Ability */
4653 + PHY_B_AS_LS = 1<<2, /* Bit 2: Link Status */
4654 + PHY_B_AS_PRR = 1<<1, /* Bit 1: Pause Resolution-Rx */
4655 + PHY_B_AS_PRT = 1<<0, /* Bit 0: Pause Resolution-Tx */
4656 +};
4657 +#define PHY_B_AS_PAUSE_MSK (PHY_B_AS_PRR | PHY_B_AS_PRT)
4658 +
4659 +/***** PHY_BCOM_INT_STAT 16 bit r/o Interrupt Status Reg *****/
4660 +/***** PHY_BCOM_INT_MASK 16 bit r/w Interrupt Mask Reg *****/
4661 +enum {
4662 + PHY_B_IS_PSE = 1<<14, /* Bit 14: Pair Swap Error */
4663 + PHY_B_IS_MDXI_SC = 1<<13, /* Bit 13: MDIX Status Change */
4664 + PHY_B_IS_HCT = 1<<12, /* Bit 12: counter above 32k */
4665 + PHY_B_IS_LCT = 1<<11, /* Bit 11: counter above 128 */
4666 + PHY_B_IS_AN_PR = 1<<10, /* Bit 10: Page Received */
4667 + PHY_B_IS_NO_HDCL = 1<<9, /* Bit 9: No HCD Link */
4668 + PHY_B_IS_NO_HDC = 1<<8, /* Bit 8: No HCD */
4669 + PHY_B_IS_NEG_USHDC = 1<<7, /* Bit 7: Negotiated Unsup. HCD */
4670 + PHY_B_IS_SCR_S_ER = 1<<6, /* Bit 6: Scrambler Sync Error */
4671 + PHY_B_IS_RRS_CHANGE = 1<<5, /* Bit 5: Remote Rx Stat Change */
4672 + PHY_B_IS_LRS_CHANGE = 1<<4, /* Bit 4: Local Rx Stat Change */
4673 + PHY_B_IS_DUP_CHANGE = 1<<3, /* Bit 3: Duplex Mode Change */
4674 + PHY_B_IS_LSP_CHANGE = 1<<2, /* Bit 2: Link Speed Change */
4675 + PHY_B_IS_LST_CHANGE = 1<<1, /* Bit 1: Link Status Changed */
4676 + PHY_B_IS_CRC_ER = 1<<0, /* Bit 0: CRC Error */
4677 +};
4678 +#define PHY_B_DEF_MSK \
4679 + (~(PHY_B_IS_PSE | PHY_B_IS_AN_PR | PHY_B_IS_DUP_CHANGE | \
4680 + PHY_B_IS_LSP_CHANGE | PHY_B_IS_LST_CHANGE))
4681 +
4682 +/* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */
4683 +enum {
4684 + PHY_B_P_NO_PAUSE = 0<<10,/* Bit 11..10: no Pause Mode */
4685 + PHY_B_P_SYM_MD = 1<<10, /* Bit 11..10: symmetric Pause Mode */
4686 + PHY_B_P_ASYM_MD = 2<<10,/* Bit 11..10: asymmetric Pause Mode */
4687 + PHY_B_P_BOTH_MD = 3<<10,/* Bit 11..10: both Pause Mode */
4688 +};
4689 +/*
4690 + * Resolved Duplex mode and Capabilities (Aux Status Summary Reg)
4691 + */
4692 +enum {
4693 + PHY_B_RES_1000FD = 7<<8,/* Bit 10..8: 1000Base-T Full Dup. */
4694 + PHY_B_RES_1000HD = 6<<8,/* Bit 10..8: 1000Base-T Half Dup. */
4695 +};
4696 +
4697 +/** Marvell-Specific */
4698 +enum {
4699 + PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
4700 + PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */
4701 + PHY_M_AN_RF = 1<<13, /* Remote Fault */
4702 +
4703 + PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */
4704 + PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */
4705 + PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
4706 + PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
4707 + PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
4708 + PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
4709 + PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
4710 + PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
4711 +};
4712 +
4713 +/* special defines for FIBER (88E1011S only) */
4714 +enum {
4715 + PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
4716 + PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
4717 + PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
4718 + PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
4719 +};
4720 +
4721 +/* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
4722 +enum {
4723 + PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
4724 + PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
4725 + PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
4726 + PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
4727 +};
4728 +
4729 +/***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
4730 +enum {
4731 + PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
4732 + PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
4733 + PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
4734 + PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
4735 + PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
4736 + PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
4737 +};
4738 +
4739 +/***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
4740 +enum {
4741 + PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
4742 + PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
4743 + PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
4744 + PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */
4745 + PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
4746 + PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */
4747 + PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
4748 + PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */
4749 + PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */
4750 + PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */
4751 + PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */
4752 + PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */
4753 +};
4754 +
4755 +enum {
4756 + PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */
4757 + PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
4758 +};
4759 +
4760 +#define PHY_M_PC_MDI_XMODE(x) (((x)<<5) & PHY_M_PC_MDIX_MSK)
4761 +
4762 +enum {
4763 + PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
4764 + PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */
4765 + PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
4766 +};
4767 +
4768 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
4769 +enum {
4770 + PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
4771 + PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */
4772 + PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */
4773 + PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */
4774 + PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
4775 +
4776 + PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */
4777 + PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
4778 +
4779 + PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */
4780 + PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
4781 +};
4782 +
4783 +/***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
4784 +enum {
4785 + PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
4786 + PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */
4787 + PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */
4788 + PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */
4789 + PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */
4790 + PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */
4791 + PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */
4792 + PHY_M_PS_LINK_UP = 1<<10, /* Link Up */
4793 + PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
4794 + PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */
4795 + PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */
4796 + PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */
4797 + PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */
4798 + PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */
4799 + PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */
4800 + PHY_M_PS_JABBER = 1<<0, /* Jabber */
4801 +};
4802 +
4803 +#define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
4804 +
4805 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
4806 +enum {
4807 + PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */
4808 + PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
4809 +};
4810 +
4811 +enum {
4812 + PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
4813 + PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */
4814 + PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */
4815 + PHY_M_IS_AN_PR = 1<<12, /* Page Received */
4816 + PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
4817 + PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */
4818 + PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */
4819 + PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */
4820 + PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */
4821 + PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */
4822 + PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */
4823 + PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */
4824 +
4825 + PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */
4826 + PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */
4827 + PHY_M_IS_JABBER = 1<<0, /* Jabber */
4828 +};
4829 +
4830 +#define PHY_M_DEF_MSK ( PHY_M_IS_AN_ERROR | PHY_M_IS_LSP_CHANGE | \
4831 + PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR)
4832 +
4833 +/***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
4834 +enum {
4835 + PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
4836 + PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
4837 +
4838 + PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
4839 + PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
4840 + /* (88E1011 only) */
4841 + PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */
4842 + /* (88E1011 only) */
4843 + PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */
4844 + /* (88E1111 only) */
4845 + PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
4846 + /* !!! Errata in spec. (1 = disable) */
4847 + PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
4848 + PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */
4849 + PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
4850 + PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
4851 + PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
4852 + PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};
4853 +
4854 +#define PHY_M_EC_M_DSC(x) ((x)<<10) /* 00=1x; 01=2x; 10=3x; 11=4x */
4855 +#define PHY_M_EC_S_DSC(x) ((x)<<8) /* 00=dis; 01=1x; 10=2x; 11=3x */
4856 +#define PHY_M_EC_MAC_S(x) ((x)<<4) /* 01X=0; 110=2.5; 111=25 (MHz) */
4857 +
4858 +#define PHY_M_EC_M_DSC_2(x) ((x)<<9) /* 000=1x; 001=2x; 010=3x; 011=4x */
4859 + /* 100=5x; 101=6x; 110=7x; 111=8x */
4860 +enum {
4861 + MAC_TX_CLK_0_MHZ = 2,
4862 + MAC_TX_CLK_2_5_MHZ = 6,
4863 + MAC_TX_CLK_25_MHZ = 7,
4864 +};
4865 +
4866 +/***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
4867 +enum {
4868 + PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */
4869 + PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
4870 + PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
4871 + PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
4872 + PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
4873 + PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
4874 + PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
4875 + /* (88E1111 only) */
4876 +};
4877 +
4878 +enum {
4879 + PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */
4880 + /* (88E1011 only) */
4881 + PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
4882 + PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
4883 + PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
4884 + PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
4885 + PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
4886 +};
4887 +
4888 +#define PHY_M_LED_PULS_DUR(x) ( ((x)<<12) & PHY_M_LEDC_PULS_MSK)
4889 +
4890 +enum {
4891 + PULS_NO_STR = 0,/* no pulse stretching */
4892 + PULS_21MS = 1,/* 21 ms to 42 ms */
4893 + PULS_42MS = 2,/* 42 ms to 84 ms */
4894 + PULS_84MS = 3,/* 84 ms to 170 ms */
4895 + PULS_170MS = 4,/* 170 ms to 340 ms */
4896 + PULS_340MS = 5,/* 340 ms to 670 ms */
4897 + PULS_670MS = 6,/* 670 ms to 1.3 s */
4898 + PULS_1300MS = 7,/* 1.3 s to 2.7 s */
4899 +};
4900 +
4901 +#define PHY_M_LED_BLINK_RT(x) ( ((x)<<8) & PHY_M_LEDC_BL_R_MSK)
4902 +
4903 +enum {
4904 + BLINK_42MS = 0,/* 42 ms */
4905 + BLINK_84MS = 1,/* 84 ms */
4906 + BLINK_170MS = 2,/* 170 ms */
4907 + BLINK_340MS = 3,/* 340 ms */
4908 + BLINK_670MS = 4,/* 670 ms */
4909 +};
4910 +
4911 +/***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
4912 +#define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */
4913 + /* Bit 13..12: reserved */
4914 +#define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */
4915 +#define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */
4916 +#define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */
4917 +#define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */
4918 +#define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */
4919 +#define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */
4920 +
4921 +enum {
4922 + MO_LED_NORM = 0,
4923 + MO_LED_BLINK = 1,
4924 + MO_LED_OFF = 2,
4925 + MO_LED_ON = 3,
4926 +};
4927 +
4928 +/***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
4929 +enum {
4930 + PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */
4931 + PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */
4932 + PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
4933 + PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */
4934 + PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */
4935 +};
4936 +
4937 +/***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
4938 +enum {
4939 + PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
4940 + PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */
4941 + PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */
4942 + PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */
4943 + PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */
4944 + PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */
4945 + PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */
4946 + /* (88E1111 only) */
4947 + /* Bit 9.. 4: reserved (88E1011 only) */
4948 + PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
4949 + PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */
4950 + PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
4951 +};
4952 +
4953 +/***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/
4954 +enum {
4955 + PHY_M_CABD_ENA_TEST = 1<<15, /* Enable Test (Page 0) */
4956 + PHY_M_CABD_DIS_WAIT = 1<<15, /* Disable Waiting Period (Page 1) */
4957 + /* (88E1111 only) */
4958 + PHY_M_CABD_STAT_MSK = 3<<13, /* Bit 14..13: Status Mask */
4959 + PHY_M_CABD_AMPL_MSK = 0x1f<<8,/* Bit 12.. 8: Amplitude Mask */
4960 + /* (88E1111 only) */
4961 + PHY_M_CABD_DIST_MSK = 0xff, /* Bit 7.. 0: Distance Mask */
4962 +};
4963 +
4964 +/* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */
4965 +enum {
4966 + CABD_STAT_NORMAL= 0,
4967 + CABD_STAT_SHORT = 1,
4968 + CABD_STAT_OPEN = 2,
4969 + CABD_STAT_FAIL = 3,
4970 +};
4971 +
4972 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
4973 +/***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
4974 + /* Bit 15..12: reserved (used internally) */
4975 +enum {
4976 + PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
4977 + PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
4978 + PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
4979 +};
4980 +
4981 +#define PHY_M_FELP_LED2_CTRL(x) ( ((x)<<8) & PHY_M_FELP_LED2_MSK)
4982 +#define PHY_M_FELP_LED1_CTRL(x) ( ((x)<<4) & PHY_M_FELP_LED1_MSK)
4983 +#define PHY_M_FELP_LED0_CTRL(x) ( ((x)<<0) & PHY_M_FELP_LED0_MSK)
4984 +
4985 +enum {
4986 + LED_PAR_CTRL_COLX = 0x00,
4987 + LED_PAR_CTRL_ERROR = 0x01,
4988 + LED_PAR_CTRL_DUPLEX = 0x02,
4989 + LED_PAR_CTRL_DP_COL = 0x03,
4990 + LED_PAR_CTRL_SPEED = 0x04,
4991 + LED_PAR_CTRL_LINK = 0x05,
4992 + LED_PAR_CTRL_TX = 0x06,
4993 + LED_PAR_CTRL_RX = 0x07,
4994 + LED_PAR_CTRL_ACT = 0x08,
4995 + LED_PAR_CTRL_LNK_RX = 0x09,
4996 + LED_PAR_CTRL_LNK_AC = 0x0a,
4997 + LED_PAR_CTRL_ACT_BL = 0x0b,
4998 + LED_PAR_CTRL_TX_BL = 0x0c,
4999 + LED_PAR_CTRL_RX_BL = 0x0d,
5000 + LED_PAR_CTRL_COL_BL = 0x0e,
5001 + LED_PAR_CTRL_INACT = 0x0f
5002 +};
5003 +
5004 +/*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
5005 +enum {
5006 + PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */
5007 + PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
5008 + PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
5009 +};
5010 +
5011 +/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
5012 +/***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
5013 +enum {
5014 + PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */
5015 + PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */
5016 + PHY_M_MAC_MD_COPPER = 5,/* Copper only */
5017 + PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */
5018 +};
5019 +#define PHY_M_MAC_MODE_SEL(x) ( ((x)<<7) & PHY_M_MAC_MD_MSK)
5020 +
5021 +/***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
5022 +enum {
5023 + PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */
5024 + PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
5025 + PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */
5026 + PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
5027 +};
5028 +
5029 +#define PHY_M_LEDC_LOS_CTRL(x) ( ((x)<<12) & PHY_M_LEDC_LOS_MSK)
5030 +#define PHY_M_LEDC_INIT_CTRL(x) ( ((x)<<8) & PHY_M_LEDC_INIT_MSK)
5031 +#define PHY_M_LEDC_STA1_CTRL(x) ( ((x)<<4) & PHY_M_LEDC_STA1_MSK)
5032 +#define PHY_M_LEDC_STA0_CTRL(x) ( ((x)<<0) & PHY_M_LEDC_STA0_MSK)
5033 +
5034 +/* GMAC registers */
5035 +/* Port Registers */
5036 +enum {
5037 + GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
5038 + GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
5039 + GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
5040 + GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
5041 + GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
5042 + GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
5043 + GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
5044 +/* Source Address Registers */
5045 + GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
5046 + GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
5047 + GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
5048 + GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
5049 + GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
5050 + GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
5051 +
5052 +/* Multicast Address Hash Registers */
5053 + GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
5054 + GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
5055 + GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
5056 + GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
5057 +
5058 +/* Interrupt Source Registers */
5059 + GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
5060 + GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
5061 + GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
5062 +
5063 +/* Interrupt Mask Registers */
5064 + GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
5065 + GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
5066 + GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
5067 +
5068 +/* Serial Management Interface (SMI) Registers */
5069 + GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
5070 + GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
5071 + GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
5072 +};
5073 +
5074 +/* MIB Counters */
5075 +#define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */
5076 +#define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */
5077 +
5078 +/*
5079 + * MIB Counters base address definitions (low word) -
5080 + * use offset 4 for access to high word (32 bit r/o)
5081 + */
5082 +enum {
5083 + GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */
5084 + GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */
5085 + GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
5086 + GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
5087 + GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
5088 + /* GM_MIB_CNT_BASE + 40: reserved */
5089 + GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
5090 + GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
5091 + GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
5092 + GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */
5093 + GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
5094 + GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
5095 + GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
5096 + GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */
5097 + GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */
5098 + GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */
5099 + GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */
5100 + GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */
5101 + GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */
5102 + GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152, /* Rx Frame too Long Error */
5103 + GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160, /* Rx Jabber Packet Frame */
5104 + /* GM_MIB_CNT_BASE + 168: reserved */
5105 + GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176, /* Rx FIFO overflow Event */
5106 + /* GM_MIB_CNT_BASE + 184: reserved */
5107 + GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192, /* Unicast Frames Xmitted OK */
5108 + GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200, /* Broadcast Frames Xmitted OK */
5109 + GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208, /* Pause MAC Ctrl Frames Xmitted */
5110 + GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216, /* Multicast Frames Xmitted OK */
5111 + GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224, /* Octets Transmitted OK Low */
5112 + GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232, /* Octets Transmitted OK High */
5113 + GM_TXF_64B = GM_MIB_CNT_BASE + 240, /* 64 Byte Tx Frame */
5114 + GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */
5115 + GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */
5116 + GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */
5117 + GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */
5118 + GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */
5119 + GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */
5120 +
5121 + GM_TXF_COL = GM_MIB_CNT_BASE + 304, /* Tx Collision */
5122 + GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312, /* Tx Late Collision */
5123 + GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320, /* Tx aborted due to Exces. Col. */
5124 + GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328, /* Tx Multiple Collision */
5125 + GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336, /* Tx Single Collision */
5126 + GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344, /* Tx FIFO Underrun Event */
5127 +};
5128 +
5129 +/* GMAC Bit Definitions */
5130 +/* GM_GP_STAT 16 bit r/o General Purpose Status Register */
5131 +enum {
5132 + GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */
5133 + GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
5134 + GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
5135 + GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
5136 + GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
5137 + GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
5138 + GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occured */
5139 + GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occured */
5140 +
5141 + GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
5142 + GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
5143 + GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */
5144 + GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
5145 + GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
5146 +};
5147 +
5148 +/* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
5149 +enum {
5150 + GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
5151 + GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
5152 + GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
5153 + GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
5154 + GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
5155 + GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
5156 + GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
5157 + GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */
5158 + GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */
5159 + GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
5160 + GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
5161 + GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */
5162 + GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
5163 + GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
5164 + GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
5165 +};
5166 +
5167 +#define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
5168 +#define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
5169 +
5170 +/* GM_TX_CTRL 16 bit r/w Transmit Control Register */
5171 +enum {
5172 + GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
5173 + GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
5174 + GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
5175 + GM_TXCR_COL_THR_MSK = 1<<10, /* Bit 12..10: Collision Threshold */
5176 +};
5177 +
5178 +#define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
5179 +#define TX_COL_DEF 0x04
5180 +
5181 +/* GM_RX_CTRL 16 bit r/w Receive Control Register */
5182 +enum {
5183 + GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
5184 + GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
5185 + GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
5186 + GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
5187 +};
5188 +
5189 +/* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
5190 +enum {
5191 + GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
5192 + GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */
5193 + GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */
5194 +
5195 + TX_JAM_LEN_DEF = 0x03,
5196 + TX_JAM_IPG_DEF = 0x0b,
5197 + TX_IPG_JAM_DEF = 0x1c,
5198 +};
5199 +
5200 +#define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK)
5201 +#define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK)
5202 +#define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK)
5203 +
5204 +
5205 +/* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
5206 +enum {
5207 + GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
5208 + GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */
5209 + GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */
5210 + GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
5211 + GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
5212 +};
5213 +
5214 +#define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
5215 +#define DATA_BLIND_DEF 0x04
5216 +
5217 +#define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
5218 +#define IPG_DATA_DEF 0x1e
5219 +
5220 +/* GM_SMI_CTRL 16 bit r/w SMI Control Register */
5221 +enum {
5222 + GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */
5223 + GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */
5224 + GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
5225 + GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
5226 + GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
5227 +};
5228 +
5229 +#define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
5230 +#define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK)
5231 +
5232 +/* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
5233 +enum {
5234 + GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
5235 + GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
5236 +};
5237 +
5238 +/* Receive Frame Status Encoding */
5239 +enum {
5240 + GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */
5241 + GMR_FS_VLAN = 1<<13, /* Bit 13: VLAN Packet */
5242 + GMR_FS_JABBER = 1<<12, /* Bit 12: Jabber Packet */
5243 + GMR_FS_UN_SIZE = 1<<11, /* Bit 11: Undersize Packet */
5244 + GMR_FS_MC = 1<<10, /* Bit 10: Multicast Packet */
5245 + GMR_FS_BC = 1<<9, /* Bit 9: Broadcast Packet */
5246 + GMR_FS_RX_OK = 1<<8, /* Bit 8: Receive OK (Good Packet) */
5247 + GMR_FS_GOOD_FC = 1<<7, /* Bit 7: Good Flow-Control Packet */
5248 + GMR_FS_BAD_FC = 1<<6, /* Bit 6: Bad Flow-Control Packet */
5249 + GMR_FS_MII_ERR = 1<<5, /* Bit 5: MII Error */
5250 + GMR_FS_LONG_ERR = 1<<4, /* Bit 4: Too Long Packet */
5251 + GMR_FS_FRAGMENT = 1<<3, /* Bit 3: Fragment */
5252 +
5253 + GMR_FS_CRC_ERR = 1<<1, /* Bit 1: CRC Error */
5254 + GMR_FS_RX_FF_OV = 1<<0, /* Bit 0: Rx FIFO Overflow */
5255 +
5256 +/*
5257 + * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR)
5258 + */
5259 + GMR_FS_ANY_ERR = GMR_FS_CRC_ERR | GMR_FS_LONG_ERR |
5260 + GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
5261 + GMR_FS_JABBER,
5262 +/* Rx GMAC FIFO Flush Mask (default) */
5263 + RX_FF_FL_DEF_MSK = GMR_FS_CRC_ERR | GMR_FS_RX_FF_OV |GMR_FS_MII_ERR |
5264 + GMR_FS_BAD_FC | GMR_FS_GOOD_FC | GMR_FS_UN_SIZE |
5265 + GMR_FS_JABBER,
5266 +};
5267 +
5268 +/* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
5269 +enum {
5270 + GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */
5271 + GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */
5272 + GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */
5273 +
5274 + GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */
5275 + GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */
5276 + GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */
5277 + GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
5278 + GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
5279 + GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
5280 + GMF_CLI_RX_FC = 1<<4, /* Clear IRQ Rx Frame Complete */
5281 + GMF_OPER_ON = 1<<3, /* Operational Mode On */
5282 + GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
5283 + GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
5284 + GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */
5285 +
5286 + RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */
5287 +};
5288 +
5289 +
5290 +/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
5291