/[linux-patches]/genpatches-2.6/tags/2.6.12-12/4345_it8212.patch
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Contents of /genpatches-2.6/tags/2.6.12-12/4345_it8212.patch

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Revision 137 - (show annotations) (download)
Tue Aug 9 21:23:12 2005 UTC (12 years, 10 months ago) by dsd
File size: 26452 byte(s)
2.6.12-12 release
1 Author: Alan Cox <alan@lxorguk.ukuu.org.uk>
2 Date: Mon, 27 Jun 2005 22:24:30 +0000 (-0700)
3 Source: http://www.kernel.org/git/gitweb.cgi?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=da9091ee3b5f9808c64abb925cefe7b100018614
4
5 [PATCH] ide: it8212 backport for Bartlomiej IDE
6
7 This lets you throw out the iteraid stuff that has ended up back in due
8 to stupid goings on in the IDE world. Its the same heavily tested code
9 shipped in Fedora/Red Hat products but without the other dependancies on
10 the Bartlomiej IDE layer.
11
12 Pre-requisite: the ide-disk patch I sent to handle pure LBA devices.
13
14 Obviously you lose things like hot unplug with the Bartlomiej IDE layer
15 at the moment but that won't matter to most users.
16
17 The patch does the following
18 - Add IT8211/12 to pci_ids.h
19 - Add Makefile/Kconfig entry
20 - Add it8212 driver
21
22 No core IDE code is touched by this diff
23
24 Embedded system testing and the ability to force raid mode off by David
25 Howells
26
27 Made possible by the ite reference code, documentation and also several
28 clarifications and pieces of assistance provided by ITE themselves
29
30 Signed-off-by: Alan Cox <alan@redhat.com>
31 Acked-by: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl>
32 Signed-off-by: Andrew Morton <akpm@osdl.org>
33 Signed-off-by: Linus Torvalds <torvalds@osdl.org>
34
35 --- a/drivers/ide/Kconfig
36 +++ b/drivers/ide/Kconfig
37 @@ -606,6 +606,12 @@ config BLK_DEV_IT8172
38 <http://www.ite.com.tw/ia/brief_it8172bsp.htm>; picture of the
39 board at <http://www.mvista.com/partners/semiconductor/ite.html>.
40
41 +config BLK_DEV_IT821X
42 + tristate "IT821X IDE support"
43 + help
44 + This driver adds support for the ITE 8211 IDE controller and the
45 + IT 8212 IDE RAID controller in both RAID and pass-through mode.
46 +
47 config BLK_DEV_NS87415
48 tristate "NS87415 chipset support"
49 help
50 --- a/drivers/ide/pci/Makefile
51 +++ b/drivers/ide/pci/Makefile
52 @@ -12,6 +12,7 @@ obj-$(CONFIG_BLK_DEV_HPT34X) += hpt34x.
53 obj-$(CONFIG_BLK_DEV_HPT366) += hpt366.o
54 #obj-$(CONFIG_BLK_DEV_HPT37X) += hpt37x.o
55 obj-$(CONFIG_BLK_DEV_IT8172) += it8172.o
56 +obj-$(CONFIG_BLK_DEV_IT821X) += it821x.o
57 obj-$(CONFIG_BLK_DEV_NS87415) += ns87415.o
58 obj-$(CONFIG_BLK_DEV_OPTI621) += opti621.o
59 obj-$(CONFIG_BLK_DEV_PDC202XX_OLD) += pdc202xx_old.o
60 --- /dev/null
61 +++ b/drivers/ide/pci/it821x.c
62 @@ -0,0 +1,812 @@
63 +
64 +/*
65 + * linux/drivers/ide/pci/it821x.c Version 0.09 December 2004
66 + *
67 + * Copyright (C) 2004 Red Hat <alan@redhat.com>
68 + *
69 + * May be copied or modified under the terms of the GNU General Public License
70 + * Based in part on the ITE vendor provided SCSI driver.
71 + *
72 + * Documentation available from
73 + * http://www.ite.com.tw/pc/IT8212F_V04.pdf
74 + * Some other documents are NDA.
75 + *
76 + * The ITE8212 isn't exactly a standard IDE controller. It has two
77 + * modes. In pass through mode then it is an IDE controller. In its smart
78 + * mode its actually quite a capable hardware raid controller disguised
79 + * as an IDE controller. Smart mode only understands DMA read/write and
80 + * identify, none of the fancier commands apply. The IT8211 is identical
81 + * in other respects but lacks the raid mode.
82 + *
83 + * Errata:
84 + * o Rev 0x10 also requires master/slave hold the same DMA timings and
85 + * cannot do ATAPI MWDMA.
86 + * o The identify data for raid volumes lacks CHS info (technically ok)
87 + * but also fails to set the LBA28 and other bits. We fix these in
88 + * the IDE probe quirk code.
89 + * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode
90 + * raid then the controller firmware dies
91 + * o Smart mode without RAID doesn't clear all the necessary identify
92 + * bits to reduce the command set to the one used
93 + *
94 + * This has a few impacts on the driver
95 + * - In pass through mode we do all the work you would expect
96 + * - In smart mode the clocking set up is done by the controller generally
97 + * but we must watch the other limits and filter.
98 + * - There are a few extra vendor commands that actually talk to the
99 + * controller but only work PIO with no IRQ.
100 + *
101 + * Vendor areas of the identify block in smart mode are used for the
102 + * timing and policy set up. Each HDD in raid mode also has a serial
103 + * block on the disk. The hardware extra commands are get/set chip status,
104 + * rebuild, get rebuild status.
105 + *
106 + * In Linux the driver supports pass through mode as if the device was
107 + * just another IDE controller. If the smart mode is running then
108 + * volumes are managed by the controller firmware and each IDE "disk"
109 + * is a raid volume. Even more cute - the controller can do automated
110 + * hotplug and rebuild.
111 + *
112 + * The pass through controller itself is a little demented. It has a
113 + * flaw that it has a single set of PIO/MWDMA timings per channel so
114 + * non UDMA devices restrict each others performance. It also has a
115 + * single clock source per channel so mixed UDMA100/133 performance
116 + * isn't perfect and we have to pick a clock. Thankfully none of this
117 + * matters in smart mode. ATAPI DMA is not currently supported.
118 + *
119 + * It seems the smart mode is a win for RAID1/RAID10 but otherwise not.
120 + *
121 + * TODO
122 + * - ATAPI UDMA is ok but not MWDMA it seems
123 + * - RAID configuration ioctls
124 + * - Move to libata once it grows up
125 + */
126 +
127 +#include <linux/config.h>
128 +#include <linux/types.h>
129 +#include <linux/module.h>
130 +#include <linux/pci.h>
131 +#include <linux/delay.h>
132 +#include <linux/hdreg.h>
133 +#include <linux/ide.h>
134 +#include <linux/init.h>
135 +
136 +#include <asm/io.h>
137 +
138 +struct it821x_dev
139 +{
140 + unsigned int smart:1, /* Are we in smart raid mode */
141 + timing10:1; /* Rev 0x10 */
142 + u8 clock_mode; /* 0, ATA_50 or ATA_66 */
143 + u8 want[2][2]; /* Mode/Pri log for master slave */
144 + /* We need these for switching the clock when DMA goes on/off
145 + The high byte is the 66Mhz timing */
146 + u16 pio[2]; /* Cached PIO values */
147 + u16 mwdma[2]; /* Cached MWDMA values */
148 + u16 udma[2]; /* Cached UDMA values (per drive) */
149 +};
150 +
151 +#define ATA_66 0
152 +#define ATA_50 1
153 +#define ATA_ANY 2
154 +
155 +#define UDMA_OFF 0
156 +#define MWDMA_OFF 0
157 +
158 +/*
159 + * We allow users to force the card into non raid mode without
160 + * flashing the alternative BIOS. This is also neccessary right now
161 + * for embedded platforms that cannot run a PC BIOS but are using this
162 + * device.
163 + */
164 +
165 +static int it8212_noraid;
166 +
167 +/**
168 + * it821x_program - program the PIO/MWDMA registers
169 + * @drive: drive to tune
170 + *
171 + * Program the PIO/MWDMA timing for this channel according to the
172 + * current clock.
173 + */
174 +
175 +static void it821x_program(ide_drive_t *drive, u16 timing)
176 +{
177 + ide_hwif_t *hwif = drive->hwif;
178 + struct it821x_dev *itdev = ide_get_hwifdata(hwif);
179 + int channel = hwif->channel;
180 + u8 conf;
181 +
182 + /* Program PIO/MWDMA timing bits */
183 + if(itdev->clock_mode == ATA_66)
184 + conf = timing >> 8;
185 + else
186 + conf = timing & 0xFF;
187 + pci_write_config_byte(hwif->pci_dev, 0x54 + 4 * channel, conf);
188 +}
189 +
190 +/**
191 + * it821x_program_udma - program the UDMA registers
192 + * @drive: drive to tune
193 + *
194 + * Program the UDMA timing for this drive according to the
195 + * current clock.
196 + */
197 +
198 +static void it821x_program_udma(ide_drive_t *drive, u16 timing)
199 +{
200 + ide_hwif_t *hwif = drive->hwif;
201 + struct it821x_dev *itdev = ide_get_hwifdata(hwif);
202 + int channel = hwif->channel;
203 + int unit = drive->select.b.unit;
204 + u8 conf;
205 +
206 + /* Program UDMA timing bits */
207 + if(itdev->clock_mode == ATA_66)
208 + conf = timing >> 8;
209 + else
210 + conf = timing & 0xFF;
211 + if(itdev->timing10 == 0)
212 + pci_write_config_byte(hwif->pci_dev, 0x56 + 4 * channel + unit, conf);
213 + else {
214 + pci_write_config_byte(hwif->pci_dev, 0x56 + 4 * channel, conf);
215 + pci_write_config_byte(hwif->pci_dev, 0x56 + 4 * channel + 1, conf);
216 + }
217 +}
218 +
219 +
220 +/**
221 + * it821x_clock_strategy
222 + * @hwif: hardware interface
223 + *
224 + * Select between the 50 and 66Mhz base clocks to get the best
225 + * results for this interface.
226 + */
227 +
228 +static void it821x_clock_strategy(ide_drive_t *drive)
229 +{
230 + ide_hwif_t *hwif = drive->hwif;
231 + struct it821x_dev *itdev = ide_get_hwifdata(hwif);
232 +
233 + u8 unit = drive->select.b.unit;
234 + ide_drive_t *pair = &hwif->drives[1-unit];
235 +
236 + int clock, altclock;
237 + u8 v;
238 + int sel = 0;
239 +
240 + if(itdev->want[0][0] > itdev->want[1][0]) {
241 + clock = itdev->want[0][1];
242 + altclock = itdev->want[1][1];
243 + } else {
244 + clock = itdev->want[1][1];
245 + altclock = itdev->want[0][1];
246 + }
247 +
248 + /* Master doesn't care does the slave ? */
249 + if(clock == ATA_ANY)
250 + clock = altclock;
251 +
252 + /* Nobody cares - keep the same clock */
253 + if(clock == ATA_ANY)
254 + return;
255 + /* No change */
256 + if(clock == itdev->clock_mode)
257 + return;
258 +
259 + /* Load this into the controller ? */
260 + if(clock == ATA_66)
261 + itdev->clock_mode = ATA_66;
262 + else {
263 + itdev->clock_mode = ATA_50;
264 + sel = 1;
265 + }
266 + pci_read_config_byte(hwif->pci_dev, 0x50, &v);
267 + v &= ~(1 << (1 + hwif->channel));
268 + v |= sel << (1 + hwif->channel);
269 + pci_write_config_byte(hwif->pci_dev, 0x50, v);
270 +
271 + /*
272 + * Reprogram the UDMA/PIO of the pair drive for the switch
273 + * MWDMA will be dealt with by the dma switcher
274 + */
275 + if(pair && itdev->udma[1-unit] != UDMA_OFF) {
276 + it821x_program_udma(pair, itdev->udma[1-unit]);
277 + it821x_program(pair, itdev->pio[1-unit]);
278 + }
279 + /*
280 + * Reprogram the UDMA/PIO of our drive for the switch.
281 + * MWDMA will be dealt with by the dma switcher
282 + */
283 + if(itdev->udma[unit] != UDMA_OFF) {
284 + it821x_program_udma(drive, itdev->udma[unit]);
285 + it821x_program(drive, itdev->pio[unit]);
286 + }
287 +}
288 +
289 +/**
290 + * it821x_ratemask - Compute available modes
291 + * @drive: IDE drive
292 + *
293 + * Compute the available speeds for the devices on the interface. This
294 + * is all modes to ATA133 clipped by drive cable setup.
295 + */
296 +
297 +static u8 it821x_ratemask (ide_drive_t *drive)
298 +{
299 + u8 mode = 4;
300 + if (!eighty_ninty_three(drive))
301 + mode = min(mode, (u8)1);
302 + return mode;
303 +}
304 +
305 +/**
306 + * it821x_tuneproc - tune a drive
307 + * @drive: drive to tune
308 + * @mode_wanted: the target operating mode
309 + *
310 + * Load the timing settings for this device mode into the
311 + * controller. By the time we are called the mode has been
312 + * modified as neccessary to handle the absence of seperate
313 + * master/slave timers for MWDMA/PIO.
314 + *
315 + * This code is only used in pass through mode.
316 + */
317 +
318 +static void it821x_tuneproc (ide_drive_t *drive, byte mode_wanted)
319 +{
320 + ide_hwif_t *hwif = drive->hwif;
321 + struct it821x_dev *itdev = ide_get_hwifdata(hwif);
322 + int unit = drive->select.b.unit;
323 +
324 + /* Spec says 89 ref driver uses 88 */
325 + static u16 pio[] = { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 };
326 + static u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY };
327 +
328 + if(itdev->smart)
329 + return;
330 +
331 + /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */
332 + itdev->want[unit][1] = pio_want[mode_wanted];
333 + itdev->want[unit][0] = 1; /* PIO is lowest priority */
334 + itdev->pio[unit] = pio[mode_wanted];
335 + it821x_clock_strategy(drive);
336 + it821x_program(drive, itdev->pio[unit]);
337 +}
338 +
339 +/**
340 + * it821x_tune_mwdma - tune a channel for MWDMA
341 + * @drive: drive to set up
342 + * @mode_wanted: the target operating mode
343 + *
344 + * Load the timing settings for this device mode into the
345 + * controller when doing MWDMA in pass through mode. The caller
346 + * must manage the whole lack of per device MWDMA/PIO timings and
347 + * the shared MWDMA/PIO timing register.
348 + */
349 +
350 +static void it821x_tune_mwdma (ide_drive_t *drive, byte mode_wanted)
351 +{
352 + ide_hwif_t *hwif = drive->hwif;
353 + struct it821x_dev *itdev = (void *)ide_get_hwifdata(hwif);
354 + int unit = drive->select.b.unit;
355 + int channel = hwif->channel;
356 + u8 conf;
357 +
358 + static u16 dma[] = { 0x8866, 0x3222, 0x3121 };
359 + static u8 mwdma_want[] = { ATA_ANY, ATA_66, ATA_ANY };
360 +
361 + itdev->want[unit][1] = mwdma_want[mode_wanted];
362 + itdev->want[unit][0] = 2; /* MWDMA is low priority */
363 + itdev->mwdma[unit] = dma[mode_wanted];
364 + itdev->udma[unit] = UDMA_OFF;
365 +
366 + /* UDMA bits off - Revision 0x10 do them in pairs */
367 + pci_read_config_byte(hwif->pci_dev, 0x50, &conf);
368 + if(itdev->timing10)
369 + conf |= channel ? 0x60: 0x18;
370 + else
371 + conf |= 1 << (3 + 2 * channel + unit);
372 + pci_write_config_byte(hwif->pci_dev, 0x50, conf);
373 +
374 + it821x_clock_strategy(drive);
375 + /* FIXME: do we need to program this ? */
376 + /* it821x_program(drive, itdev->mwdma[unit]); */
377 +}
378 +
379 +/**
380 + * it821x_tune_udma - tune a channel for UDMA
381 + * @drive: drive to set up
382 + * @mode_wanted: the target operating mode
383 + *
384 + * Load the timing settings for this device mode into the
385 + * controller when doing UDMA modes in pass through.
386 + */
387 +
388 +static void it821x_tune_udma (ide_drive_t *drive, byte mode_wanted)
389 +{
390 + ide_hwif_t *hwif = drive->hwif;
391 + struct it821x_dev *itdev = ide_get_hwifdata(hwif);
392 + int unit = drive->select.b.unit;
393 + int channel = hwif->channel;
394 + u8 conf;
395 +
396 + static u16 udma[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 };
397 + static u8 udma_want[] = { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 };
398 +
399 + itdev->want[unit][1] = udma_want[mode_wanted];
400 + itdev->want[unit][0] = 3; /* UDMA is high priority */
401 + itdev->mwdma[unit] = MWDMA_OFF;
402 + itdev->udma[unit] = udma[mode_wanted];
403 + if(mode_wanted >= 5)
404 + itdev->udma[unit] |= 0x8080; /* UDMA 5/6 select on */
405 +
406 + /* UDMA on. Again revision 0x10 must do the pair */
407 + pci_read_config_byte(hwif->pci_dev, 0x50, &conf);
408 + if(itdev->timing10)
409 + conf &= channel ? 0x9F: 0xE7;
410 + else
411 + conf &= ~ (1 << (3 + 2 * channel + unit));
412 + pci_write_config_byte(hwif->pci_dev, 0x50, conf);
413 +
414 + it821x_clock_strategy(drive);
415 + it821x_program_udma(drive, itdev->udma[unit]);
416 +
417 +}
418 +
419 +/**
420 + * config_it821x_chipset_for_pio - set drive timings
421 + * @drive: drive to tune
422 + * @speed we want
423 + *
424 + * Compute the best pio mode we can for a given device. We must
425 + * pick a speed that does not cause problems with the other device
426 + * on the cable.
427 + */
428 +
429 +static void config_it821x_chipset_for_pio (ide_drive_t *drive, byte set_speed)
430 +{
431 + u8 unit = drive->select.b.unit;
432 + ide_hwif_t *hwif = drive->hwif;
433 + ide_drive_t *pair = &hwif->drives[1-unit];
434 + u8 speed = 0, set_pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
435 + u8 pair_pio;
436 +
437 + /* We have to deal with this mess in pairs */
438 + if(pair != NULL) {
439 + pair_pio = ide_get_best_pio_mode(pair, 255, 5, NULL);
440 + /* Trim PIO to the slowest of the master/slave */
441 + if(pair_pio < set_pio)
442 + set_pio = pair_pio;
443 + }
444 + it821x_tuneproc(drive, set_pio);
445 + speed = XFER_PIO_0 + set_pio;
446 + /* XXX - We trim to the lowest of the pair so the other drive
447 + will always be fine at this point until we do hotplug passthru */
448 +
449 + if (set_speed)
450 + (void) ide_config_drive_speed(drive, speed);
451 +}
452 +
453 +/**
454 + * it821x_dma_read - DMA hook
455 + * @drive: drive for DMA
456 + *
457 + * The IT821x has a single timing register for MWDMA and for PIO
458 + * operations. As we flip back and forth we have to reload the
459 + * clock. In addition the rev 0x10 device only works if the same
460 + * timing value is loaded into the master and slave UDMA clock
461 + * so we must also reload that.
462 + *
463 + * FIXME: we could figure out in advance if we need to do reloads
464 + */
465 +
466 +static void it821x_dma_start(ide_drive_t *drive)
467 +{
468 + ide_hwif_t *hwif = drive->hwif;
469 + struct it821x_dev *itdev = ide_get_hwifdata(hwif);
470 + int unit = drive->select.b.unit;
471 + if(itdev->mwdma[unit] != MWDMA_OFF)
472 + it821x_program(drive, itdev->mwdma[unit]);
473 + else if(itdev->udma[unit] != UDMA_OFF && itdev->timing10)
474 + it821x_program_udma(drive, itdev->udma[unit]);
475 + ide_dma_start(drive);
476 +}
477 +
478 +/**
479 + * it821x_dma_write - DMA hook
480 + * @drive: drive for DMA stop
481 + *
482 + * The IT821x has a single timing register for MWDMA and for PIO
483 + * operations. As we flip back and forth we have to reload the
484 + * clock.
485 + */
486 +
487 +static int it821x_dma_end(ide_drive_t *drive)
488 +{
489 + ide_hwif_t *hwif = drive->hwif;
490 + int unit = drive->select.b.unit;
491 + struct it821x_dev *itdev = ide_get_hwifdata(hwif);
492 + int ret = __ide_dma_end(drive);
493 + if(itdev->mwdma[unit] != MWDMA_OFF)
494 + it821x_program(drive, itdev->pio[unit]);
495 + return ret;
496 +}
497 +
498 +
499 +/**
500 + * it821x_tune_chipset - set controller timings
501 + * @drive: Drive to set up
502 + * @xferspeed: speed we want to achieve
503 + *
504 + * Tune the ITE chipset for the desired mode. If we can't achieve
505 + * the desired mode then tune for a lower one, but ultimately
506 + * make the thing work.
507 + */
508 +
509 +static int it821x_tune_chipset (ide_drive_t *drive, byte xferspeed)
510 +{
511 +
512 + ide_hwif_t *hwif = drive->hwif;
513 + struct it821x_dev *itdev = ide_get_hwifdata(hwif);
514 + u8 speed = ide_rate_filter(it821x_ratemask(drive), xferspeed);
515 +
516 + if(!itdev->smart) {
517 + switch(speed) {
518 + case XFER_PIO_4:
519 + case XFER_PIO_3:
520 + case XFER_PIO_2:
521 + case XFER_PIO_1:
522 + case XFER_PIO_0:
523 + it821x_tuneproc(drive, (speed - XFER_PIO_0));
524 + break;
525 + /* MWDMA tuning is really hard because our MWDMA and PIO
526 + timings are kept in the same place. We can switch in the
527 + host dma on/off callbacks */
528 + case XFER_MW_DMA_2:
529 + case XFER_MW_DMA_1:
530 + case XFER_MW_DMA_0:
531 + it821x_tune_mwdma(drive, (speed - XFER_MW_DMA_0));
532 + break;
533 + case XFER_UDMA_6:
534 + case XFER_UDMA_5:
535 + case XFER_UDMA_4:
536 + case XFER_UDMA_3:
537 + case XFER_UDMA_2:
538 + case XFER_UDMA_1:
539 + case XFER_UDMA_0:
540 + it821x_tune_udma(drive, (speed - XFER_UDMA_0));
541 + break;
542 + default:
543 + return 1;
544 + }
545 + }
546 + /*
547 + * In smart mode the clocking is done by the host controller
548 + * snooping the mode we picked. The rest of it is not our problem
549 + */
550 + return ide_config_drive_speed(drive, speed);
551 +}
552 +
553 +/**
554 + * config_chipset_for_dma - configure for DMA
555 + * @drive: drive to configure
556 + *
557 + * Called by the IDE layer when it wants the timings set up.
558 + */
559 +
560 +static int config_chipset_for_dma (ide_drive_t *drive)
561 +{
562 + u8 speed = ide_dma_speed(drive, it821x_ratemask(drive));
563 +
564 + config_it821x_chipset_for_pio(drive, !speed);
565 + it821x_tune_chipset(drive, speed);
566 + return ide_dma_enable(drive);
567 +}
568 +
569 +/**
570 + * it821x_configure_drive_for_dma - set up for DMA transfers
571 + * @drive: drive we are going to set up
572 + *
573 + * Set up the drive for DMA, tune the controller and drive as
574 + * required. If the drive isn't suitable for DMA or we hit
575 + * other problems then we will drop down to PIO and set up
576 + * PIO appropriately
577 + */
578 +
579 +static int it821x_config_drive_for_dma (ide_drive_t *drive)
580 +{
581 + ide_hwif_t *hwif = drive->hwif;
582 +
583 + if (ide_use_dma(drive)) {
584 + if (config_chipset_for_dma(drive))
585 + return hwif->ide_dma_on(drive);
586 + }
587 + config_it821x_chipset_for_pio(drive, 1);
588 + return hwif->ide_dma_off_quietly(drive);
589 +}
590 +
591 +/**
592 + * ata66_it821x - check for 80 pin cable
593 + * @hwif: interface to check
594 + *
595 + * Check for the presence of an ATA66 capable cable on the
596 + * interface. Problematic as it seems some cards don't have
597 + * the needed logic onboard.
598 + */
599 +
600 +static unsigned int __devinit ata66_it821x(ide_hwif_t *hwif)
601 +{
602 + /* The reference driver also only does disk side */
603 + return 1;
604 +}
605 +
606 +/**
607 + * it821x_fixup - post init callback
608 + * @hwif: interface
609 + *
610 + * This callback is run after the drives have been probed but
611 + * before anything gets attached. It allows drivers to do any
612 + * final tuning that is needed, or fixups to work around bugs.
613 + */
614 +
615 +static void __devinit it821x_fixups(ide_hwif_t *hwif)
616 +{
617 + struct it821x_dev *itdev = ide_get_hwifdata(hwif);
618 + int i;
619 +
620 + if(!itdev->smart) {
621 + /*
622 + * If we are in pass through mode then not much
623 + * needs to be done, but we do bother to clear the
624 + * IRQ mask as we may well be in PIO (eg rev 0x10)
625 + * for now and we know unmasking is safe on this chipset.
626 + */
627 + for (i = 0; i < 2; i++) {
628 + ide_drive_t *drive = &hwif->drives[i];
629 + if(drive->present)
630 + drive->unmask = 1;
631 + }
632 + return;
633 + }
634 + /*
635 + * Perform fixups on smart mode. We need to "lose" some
636 + * capabilities the firmware lacks but does not filter, and
637 + * also patch up some capability bits that it forgets to set
638 + * in RAID mode.
639 + */
640 +
641 + for(i = 0; i < 2; i++) {
642 + ide_drive_t *drive = &hwif->drives[i];
643 + struct hd_driveid *id;
644 + u16 *idbits;
645 +
646 + if(!drive->present)
647 + continue;
648 + id = drive->id;
649 + idbits = (u16 *)drive->id;
650 +
651 + /* Check for RAID v native */
652 + if(strstr(id->model, "Integrated Technology Express")) {
653 + /* In raid mode the ident block is slightly buggy
654 + We need to set the bits so that the IDE layer knows
655 + LBA28. LBA48 and DMA ar valid */
656 + id->capability |= 3; /* LBA28, DMA */
657 + id->command_set_2 |= 0x0400; /* LBA48 valid */
658 + id->cfs_enable_2 |= 0x0400; /* LBA48 on */
659 + /* Reporting logic */
660 + printk(KERN_INFO "%s: IT8212 %sRAID %d volume",
661 + drive->name,
662 + idbits[147] ? "Bootable ":"",
663 + idbits[129]);
664 + if(idbits[129] != 1)
665 + printk("(%dK stripe)", idbits[146]);
666 + printk(".\n");
667 + /* Now the core code will have wrongly decided no DMA
668 + so we need to fix this */
669 + hwif->ide_dma_off_quietly(drive);
670 +#ifdef CONFIG_IDEDMA_ONLYDISK
671 + if (drive->media == ide_disk)
672 +#endif
673 + hwif->ide_dma_check(drive);
674 + } else {
675 + /* Non RAID volume. Fixups to stop the core code
676 + doing unsupported things */
677 + id->field_valid &= 1;
678 + id->queue_depth = 0;
679 + id->command_set_1 = 0;
680 + id->command_set_2 &= 0xC400;
681 + id->cfsse &= 0xC000;
682 + id->cfs_enable_1 = 0;
683 + id->cfs_enable_2 &= 0xC400;
684 + id->csf_default &= 0xC000;
685 + id->word127 = 0;
686 + id->dlf = 0;
687 + id->csfo = 0;
688 + id->cfa_power = 0;
689 + printk(KERN_INFO "%s: Performing identify fixups.\n",
690 + drive->name);
691 + }
692 + }
693 +
694 +}
695 +
696 +/**
697 + * init_hwif_it821x - set up hwif structs
698 + * @hwif: interface to set up
699 + *
700 + * We do the basic set up of the interface structure. The IT8212
701 + * requires several custom handlers so we override the default
702 + * ide DMA handlers appropriately
703 + */
704 +
705 +static void __devinit init_hwif_it821x(ide_hwif_t *hwif)
706 +{
707 + struct it821x_dev *idev = kmalloc(sizeof(struct it821x_dev), GFP_KERNEL);
708 + u8 conf;
709 +
710 + if(idev == NULL) {
711 + printk(KERN_ERR "it821x: out of memory, falling back to legacy behaviour.\n");
712 + goto fallback;
713 + }
714 + memset(idev, 0, sizeof(struct it821x_dev));
715 + ide_set_hwifdata(hwif, idev);
716 +
717 + pci_read_config_byte(hwif->pci_dev, 0x50, &conf);
718 + if(conf & 1) {
719 + idev->smart = 1;
720 + hwif->atapi_dma = 0;
721 + /* Long I/O's although allowed in LBA48 space cause the
722 + onboard firmware to enter the twighlight zone */
723 + hwif->rqsize = 256;
724 + }
725 +
726 + /* Pull the current clocks from 0x50 also */
727 + if (conf & (1 << (1 + hwif->channel)))
728 + idev->clock_mode = ATA_50;
729 + else
730 + idev->clock_mode = ATA_66;
731 +
732 + idev->want[0][1] = ATA_ANY;
733 + idev->want[1][1] = ATA_ANY;
734 +
735 + /*
736 + * Not in the docs but according to the reference driver
737 + * this is neccessary.
738 + */
739 +
740 + pci_read_config_byte(hwif->pci_dev, 0x08, &conf);
741 + if(conf == 0x10) {
742 + idev->timing10 = 1;
743 + hwif->atapi_dma = 0;
744 + if(!idev->smart)
745 + printk(KERN_WARNING "it821x: Revision 0x10, workarounds activated.\n");
746 + }
747 +
748 + hwif->speedproc = &it821x_tune_chipset;
749 + hwif->tuneproc = &it821x_tuneproc;
750 +
751 + /* MWDMA/PIO clock switching for pass through mode */
752 + if(!idev->smart) {
753 + hwif->dma_start = &it821x_dma_start;
754 + hwif->ide_dma_end = &it821x_dma_end;
755 + }
756 +
757 + hwif->drives[0].autotune = 1;
758 + hwif->drives[1].autotune = 1;
759 +
760 + if (!hwif->dma_base)
761 + goto fallback;
762 +
763 + hwif->ultra_mask = 0x7f;
764 + hwif->mwdma_mask = 0x07;
765 + hwif->swdma_mask = 0x07;
766 +
767 + hwif->ide_dma_check = &it821x_config_drive_for_dma;
768 + if (!(hwif->udma_four))
769 + hwif->udma_four = ata66_it821x(hwif);
770 +
771 + /*
772 + * The BIOS often doesn't set up DMA on this controller
773 + * so we always do it.
774 + */
775 +
776 + hwif->autodma = 1;
777 + hwif->drives[0].autodma = hwif->autodma;
778 + hwif->drives[1].autodma = hwif->autodma;
779 + return;
780 +fallback:
781 + hwif->autodma = 0;
782 + return;
783 +}
784 +
785 +static void __devinit it8212_disable_raid(struct pci_dev *dev)
786 +{
787 + /* Reset local CPU, and set BIOS not ready */
788 + pci_write_config_byte(dev, 0x5E, 0x01);
789 +
790 + /* Set to bypass mode, and reset PCI bus */
791 + pci_write_config_byte(dev, 0x50, 0x00);
792 + pci_write_config_word(dev, PCI_COMMAND,
793 + PCI_COMMAND_PARITY | PCI_COMMAND_IO |
794 + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
795 + pci_write_config_word(dev, 0x40, 0xA0F3);
796 +
797 + pci_write_config_dword(dev,0x4C, 0x02040204);
798 + pci_write_config_byte(dev, 0x42, 0x36);
799 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0);
800 +}
801 +
802 +static unsigned int __devinit init_chipset_it821x(struct pci_dev *dev, const char *name)
803 +{
804 + u8 conf;
805 + static char *mode[2] = { "pass through", "smart" };
806 +
807 + /* Force the card into bypass mode if so requested */
808 + if (it8212_noraid) {
809 + printk(KERN_INFO "it8212: forcing bypass mode.\n");
810 + it8212_disable_raid(dev);
811 + }
812 + pci_read_config_byte(dev, 0x50, &conf);
813 + printk(KERN_INFO "it821x: controller in %s mode.\n", mode[conf & 1]);
814 + return 0;
815 +}
816 +
817 +
818 +#define DECLARE_ITE_DEV(name_str) \
819 + { \
820 + .name = name_str, \
821 + .init_chipset = init_chipset_it821x, \
822 + .init_hwif = init_hwif_it821x, \
823 + .channels = 2, \
824 + .autodma = AUTODMA, \
825 + .bootable = ON_BOARD, \
826 + .fixup = it821x_fixups \
827 + }
828 +
829 +static ide_pci_device_t it821x_chipsets[] __devinitdata = {
830 + /* 0 */ DECLARE_ITE_DEV("IT8212"),
831 +};
832 +
833 +/**
834 + * it821x_init_one - pci layer discovery entry
835 + * @dev: PCI device
836 + * @id: ident table entry
837 + *
838 + * Called by the PCI code when it finds an ITE821x controller.
839 + * We then use the IDE PCI generic helper to do most of the work.
840 + */
841 +
842 +static int __devinit it821x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
843 +{
844 + ide_setup_pci_device(dev, &it821x_chipsets[id->driver_data]);
845 + return 0;
846 +}
847 +
848 +static struct pci_device_id it821x_pci_tbl[] = {
849 + { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
850 + { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8212, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
851 + { 0, },
852 +};
853 +
854 +MODULE_DEVICE_TABLE(pci, it821x_pci_tbl);
855 +
856 +static struct pci_driver driver = {
857 + .name = "ITE821x IDE",
858 + .id_table = it821x_pci_tbl,
859 + .probe = it821x_init_one,
860 +};
861 +
862 +static int __init it821x_ide_init(void)
863 +{
864 + return ide_pci_register_driver(&driver);
865 +}
866 +
867 +module_init(it821x_ide_init);
868 +
869 +module_param_named(noraid, it8212_noraid, int, S_IRUGO);
870 +MODULE_PARM_DESC(it8212_noraid, "Force card into bypass mode");
871 +
872 +MODULE_AUTHOR("Alan Cox");
873 +MODULE_DESCRIPTION("PCI driver module for the ITE 821x");
874 +MODULE_LICENSE("GPL");
875 --- a/include/linux/pci_ids.h
876 +++ b/include/linux/pci_ids.h
877 @@ -1815,6 +1815,8 @@
878 #define PCI_VENDOR_ID_ITE 0x1283
879 #define PCI_DEVICE_ID_ITE_IT8172G 0x8172
880 #define PCI_DEVICE_ID_ITE_IT8172G_AUDIO 0x0801
881 +#define PCI_DEVICE_ID_ITE_8211 0x8211
882 +#define PCI_DEVICE_ID_ITE_8212 0x8212
883 #define PCI_DEVICE_ID_ITE_8872 0x8872
884 #define PCI_DEVICE_ID_ITE_IT8330G_0 0xe886
885

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