/[linux-patches]/genpatches-2.6/tags/2.6.15-4/4100_sky2-0.15.patch
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Contents of /genpatches-2.6/tags/2.6.15-4/4100_sky2-0.15.patch

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Revision 288 - (show annotations) (download)
Tue Jan 31 11:46:46 2006 UTC (12 years, 3 months ago) by dsd
File size: 169984 byte(s)
2.6.15-4 release
1 sky2 v0.15 without msi stuff
2
3 --- linux-2.6.15/drivers/net/sky2.c 1970-01-01 01:00:00.000000000 +0100
4 +++ linux-2.6.15-gentoo-r2/drivers/net/sky2.c 2006-01-31 11:34:53.000000000 +0000
5 @@ -0,0 +1,3333 @@
6 +/*
7 + * New driver for Marvell Yukon 2 chipset.
8 + * Based on earlier sk98lin, and skge driver.
9 + *
10 + * This driver intentionally does not support all the features
11 + * of the original driver such as link fail-over and link management because
12 + * those should be done at higher levels.
13 + *
14 + * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
15 + *
16 + * This program is free software; you can redistribute it and/or modify
17 + * it under the terms of the GNU General Public License as published by
18 + * the Free Software Foundation; either version 2 of the License, or
19 + * (at your option) any later version.
20 + *
21 + * This program is distributed in the hope that it will be useful,
22 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 + * GNU General Public License for more details.
25 + *
26 + * You should have received a copy of the GNU General Public License
27 + * along with this program; if not, write to the Free Software
28 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 + */
30 +
31 +#include <linux/config.h>
32 +#include <linux/crc32.h>
33 +#include <linux/kernel.h>
34 +#include <linux/version.h>
35 +#include <linux/module.h>
36 +#include <linux/netdevice.h>
37 +#include <linux/dma-mapping.h>
38 +#include <linux/etherdevice.h>
39 +#include <linux/ethtool.h>
40 +#include <linux/pci.h>
41 +#include <linux/ip.h>
42 +#include <linux/tcp.h>
43 +#include <linux/in.h>
44 +#include <linux/delay.h>
45 +#include <linux/workqueue.h>
46 +#include <linux/if_vlan.h>
47 +#include <linux/prefetch.h>
48 +#include <linux/mii.h>
49 +
50 +#include <asm/irq.h>
51 +
52 +#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
53 +#define SKY2_VLAN_TAG_USED 1
54 +#endif
55 +
56 +#include "sky2.h"
57 +
58 +#define DRV_NAME "sky2"
59 +#define DRV_VERSION "0.15"
60 +#define PFX DRV_NAME " "
61 +
62 +/*
63 + * The Yukon II chipset takes 64 bit command blocks (called list elements)
64 + * that are organized into three (receive, transmit, status) different rings
65 + * similar to Tigon3. A transmit can require several elements;
66 + * a receive requires one (or two if using 64 bit dma).
67 + */
68 +
69 +#define is_ec_a1(hw) \
70 + unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
71 + (hw)->chip_rev == CHIP_REV_YU_EC_A1)
72 +
73 +#define RX_LE_SIZE 512
74 +#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
75 +#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
76 +#define RX_DEF_PENDING RX_MAX_PENDING
77 +#define RX_SKB_ALIGN 8
78 +
79 +#define TX_RING_SIZE 512
80 +#define TX_DEF_PENDING (TX_RING_SIZE - 1)
81 +#define TX_MIN_PENDING 64
82 +#define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
83 +
84 +#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
85 +#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
86 +#define ETH_JUMBO_MTU 9000
87 +#define TX_WATCHDOG (5 * HZ)
88 +#define NAPI_WEIGHT 64
89 +#define PHY_RETRIES 1000
90 +
91 +static const u32 default_msg =
92 + NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
93 + | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
94 + | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
95 +
96 +static int debug = -1; /* defaults above */
97 +module_param(debug, int, 0);
98 +MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
99 +
100 +static int copybreak __read_mostly = 256;
101 +module_param(copybreak, int, 0);
102 +MODULE_PARM_DESC(copybreak, "Receive copy threshold");
103 +
104 +static const struct pci_device_id sky2_id_table[] = {
105 + { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
106 + { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
107 + { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
108 + { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
109 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
110 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
111 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
112 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
113 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
114 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
115 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
116 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
117 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
118 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
119 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
120 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
121 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
122 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
123 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
124 + { 0 }
125 +};
126 +
127 +MODULE_DEVICE_TABLE(pci, sky2_id_table);
128 +
129 +/* Avoid conditionals by using array */
130 +static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
131 +static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
132 +
133 +/* This driver supports yukon2 chipset only */
134 +static const char *yukon2_name[] = {
135 + "XL", /* 0xb3 */
136 + "EC Ultra", /* 0xb4 */
137 + "UNKNOWN", /* 0xb5 */
138 + "EC", /* 0xb6 */
139 + "FE", /* 0xb7 */
140 +};
141 +
142 +/* Access to external PHY */
143 +static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
144 +{
145 + int i;
146 +
147 + gma_write16(hw, port, GM_SMI_DATA, val);
148 + gma_write16(hw, port, GM_SMI_CTRL,
149 + GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
150 +
151 + for (i = 0; i < PHY_RETRIES; i++) {
152 + if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
153 + return 0;
154 + udelay(1);
155 + }
156 +
157 + printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
158 + return -ETIMEDOUT;
159 +}
160 +
161 +static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
162 +{
163 + int i;
164 +
165 + gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
166 + | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
167 +
168 + for (i = 0; i < PHY_RETRIES; i++) {
169 + if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
170 + *val = gma_read16(hw, port, GM_SMI_DATA);
171 + return 0;
172 + }
173 +
174 + udelay(1);
175 + }
176 +
177 + return -ETIMEDOUT;
178 +}
179 +
180 +static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
181 +{
182 + u16 v;
183 +
184 + if (__gm_phy_read(hw, port, reg, &v) != 0)
185 + printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
186 + return v;
187 +}
188 +
189 +static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
190 +{
191 + u16 power_control;
192 + u32 reg1;
193 + int vaux;
194 + int ret = 0;
195 +
196 + pr_debug("sky2_set_power_state %d\n", state);
197 + sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
198 +
199 + pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control);
200 + vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
201 + (power_control & PCI_PM_CAP_PME_D3cold);
202 +
203 + pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control);
204 +
205 + power_control |= PCI_PM_CTRL_PME_STATUS;
206 + power_control &= ~(PCI_PM_CTRL_STATE_MASK);
207 +
208 + switch (state) {
209 + case PCI_D0:
210 + /* switch power to VCC (WA for VAUX problem) */
211 + sky2_write8(hw, B0_POWER_CTRL,
212 + PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
213 +
214 + /* disable Core Clock Division, */
215 + sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
216 +
217 + if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
218 + /* enable bits are inverted */
219 + sky2_write8(hw, B2_Y2_CLK_GATE,
220 + Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
221 + Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
222 + Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
223 + else
224 + sky2_write8(hw, B2_Y2_CLK_GATE, 0);
225 +
226 + /* Turn off phy power saving */
227 + pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
228 + reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
229 +
230 + /* looks like this XL is back asswards .. */
231 + if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
232 + reg1 |= PCI_Y2_PHY1_COMA;
233 + if (hw->ports > 1)
234 + reg1 |= PCI_Y2_PHY2_COMA;
235 + }
236 + pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
237 + break;
238 +
239 + case PCI_D3hot:
240 + case PCI_D3cold:
241 + /* Turn on phy power saving */
242 + pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
243 + if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
244 + reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
245 + else
246 + reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
247 + pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
248 +
249 + if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
250 + sky2_write8(hw, B2_Y2_CLK_GATE, 0);
251 + else
252 + /* enable bits are inverted */
253 + sky2_write8(hw, B2_Y2_CLK_GATE,
254 + Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
255 + Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
256 + Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
257 +
258 + /* switch power to VAUX */
259 + if (vaux && state != PCI_D3cold)
260 + sky2_write8(hw, B0_POWER_CTRL,
261 + (PC_VAUX_ENA | PC_VCC_ENA |
262 + PC_VAUX_ON | PC_VCC_OFF));
263 + break;
264 + default:
265 + printk(KERN_ERR PFX "Unknown power state %d\n", state);
266 + ret = -1;
267 + }
268 +
269 + pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control);
270 + sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
271 + return ret;
272 +}
273 +
274 +static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
275 +{
276 + u16 reg;
277 +
278 + /* disable all GMAC IRQ's */
279 + sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
280 + /* disable PHY IRQs */
281 + gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
282 +
283 + gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
284 + gma_write16(hw, port, GM_MC_ADDR_H2, 0);
285 + gma_write16(hw, port, GM_MC_ADDR_H3, 0);
286 + gma_write16(hw, port, GM_MC_ADDR_H4, 0);
287 +
288 + reg = gma_read16(hw, port, GM_RX_CTRL);
289 + reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
290 + gma_write16(hw, port, GM_RX_CTRL, reg);
291 +}
292 +
293 +static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
294 +{
295 + struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
296 + u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
297 +
298 + if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
299 + u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
300 +
301 + ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
302 + PHY_M_EC_MAC_S_MSK);
303 + ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
304 +
305 + if (hw->chip_id == CHIP_ID_YUKON_EC)
306 + ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
307 + else
308 + ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
309 +
310 + gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
311 + }
312 +
313 + ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
314 + if (hw->copper) {
315 + if (hw->chip_id == CHIP_ID_YUKON_FE) {
316 + /* enable automatic crossover */
317 + ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
318 + } else {
319 + /* disable energy detect */
320 + ctrl &= ~PHY_M_PC_EN_DET_MSK;
321 +
322 + /* enable automatic crossover */
323 + ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
324 +
325 + if (sky2->autoneg == AUTONEG_ENABLE &&
326 + hw->chip_id == CHIP_ID_YUKON_XL) {
327 + ctrl &= ~PHY_M_PC_DSC_MSK;
328 + ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
329 + }
330 + }
331 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
332 + } else {
333 + /* workaround for deviation #4.88 (CRC errors) */
334 + /* disable Automatic Crossover */
335 +
336 + ctrl &= ~PHY_M_PC_MDIX_MSK;
337 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
338 +
339 + if (hw->chip_id == CHIP_ID_YUKON_XL) {
340 + /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
341 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
342 + ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
343 + ctrl &= ~PHY_M_MAC_MD_MSK;
344 + ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
345 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
346 +
347 + /* select page 1 to access Fiber registers */
348 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
349 + }
350 + }
351 +
352 + ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
353 + if (sky2->autoneg == AUTONEG_DISABLE)
354 + ctrl &= ~PHY_CT_ANE;
355 + else
356 + ctrl |= PHY_CT_ANE;
357 +
358 + ctrl |= PHY_CT_RESET;
359 + gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
360 +
361 + ctrl = 0;
362 + ct1000 = 0;
363 + adv = PHY_AN_CSMA;
364 +
365 + if (sky2->autoneg == AUTONEG_ENABLE) {
366 + if (hw->copper) {
367 + if (sky2->advertising & ADVERTISED_1000baseT_Full)
368 + ct1000 |= PHY_M_1000C_AFD;
369 + if (sky2->advertising & ADVERTISED_1000baseT_Half)
370 + ct1000 |= PHY_M_1000C_AHD;
371 + if (sky2->advertising & ADVERTISED_100baseT_Full)
372 + adv |= PHY_M_AN_100_FD;
373 + if (sky2->advertising & ADVERTISED_100baseT_Half)
374 + adv |= PHY_M_AN_100_HD;
375 + if (sky2->advertising & ADVERTISED_10baseT_Full)
376 + adv |= PHY_M_AN_10_FD;
377 + if (sky2->advertising & ADVERTISED_10baseT_Half)
378 + adv |= PHY_M_AN_10_HD;
379 + } else /* special defines for FIBER (88E1011S only) */
380 + adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
381 +
382 + /* Set Flow-control capabilities */
383 + if (sky2->tx_pause && sky2->rx_pause)
384 + adv |= PHY_AN_PAUSE_CAP; /* symmetric */
385 + else if (sky2->rx_pause && !sky2->tx_pause)
386 + adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
387 + else if (!sky2->rx_pause && sky2->tx_pause)
388 + adv |= PHY_AN_PAUSE_ASYM; /* local */
389 +
390 + /* Restart Auto-negotiation */
391 + ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
392 + } else {
393 + /* forced speed/duplex settings */
394 + ct1000 = PHY_M_1000C_MSE;
395 +
396 + if (sky2->duplex == DUPLEX_FULL)
397 + ctrl |= PHY_CT_DUP_MD;
398 +
399 + switch (sky2->speed) {
400 + case SPEED_1000:
401 + ctrl |= PHY_CT_SP1000;
402 + break;
403 + case SPEED_100:
404 + ctrl |= PHY_CT_SP100;
405 + break;
406 + }
407 +
408 + ctrl |= PHY_CT_RESET;
409 + }
410 +
411 + if (hw->chip_id != CHIP_ID_YUKON_FE)
412 + gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
413 +
414 + gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
415 + gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
416 +
417 + /* Setup Phy LED's */
418 + ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
419 + ledover = 0;
420 +
421 + switch (hw->chip_id) {
422 + case CHIP_ID_YUKON_FE:
423 + /* on 88E3082 these bits are at 11..9 (shifted left) */
424 + ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
425 +
426 + ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
427 +
428 + /* delete ACT LED control bits */
429 + ctrl &= ~PHY_M_FELP_LED1_MSK;
430 + /* change ACT LED control to blink mode */
431 + ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
432 + gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
433 + break;
434 +
435 + case CHIP_ID_YUKON_XL:
436 + pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
437 +
438 + /* select page 3 to access LED control register */
439 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
440 +
441 + /* set LED Function Control register */
442 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
443 + PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
444 + PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
445 + PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
446 +
447 + /* set Polarity Control register */
448 + gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
449 + (PHY_M_POLC_LS1_P_MIX(4) |
450 + PHY_M_POLC_IS0_P_MIX(4) |
451 + PHY_M_POLC_LOS_CTRL(2) |
452 + PHY_M_POLC_INIT_CTRL(2) |
453 + PHY_M_POLC_STA1_CTRL(2) |
454 + PHY_M_POLC_STA0_CTRL(2)));
455 +
456 + /* restore page register */
457 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
458 + break;
459 +
460 + default:
461 + /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
462 + ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
463 + /* turn off the Rx LED (LED_RX) */
464 + ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
465 + }
466 +
467 + gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
468 +
469 + if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
470 + /* turn on 100 Mbps LED (LED_LINK100) */
471 + ledover |= PHY_M_LED_MO_100(MO_LED_ON);
472 + }
473 +
474 + if (ledover)
475 + gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
476 +
477 + /* Enable phy interrupt on auto-negotiation complete (or link up) */
478 + if (sky2->autoneg == AUTONEG_ENABLE)
479 + gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
480 + else
481 + gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
482 +}
483 +
484 +/* Force a renegotiation */
485 +static void sky2_phy_reinit(struct sky2_port *sky2)
486 +{
487 + down(&sky2->phy_sema);
488 + sky2_phy_init(sky2->hw, sky2->port);
489 + up(&sky2->phy_sema);
490 +}
491 +
492 +static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
493 +{
494 + struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
495 + u16 reg;
496 + int i;
497 + const u8 *addr = hw->dev[port]->dev_addr;
498 +
499 + sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
500 + sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
501 +
502 + sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
503 +
504 + if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
505 + /* WA DEV_472 -- looks like crossed wires on port 2 */
506 + /* clear GMAC 1 Control reset */
507 + sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
508 + do {
509 + sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
510 + sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
511 + } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
512 + gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
513 + gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
514 + }
515 +
516 + if (sky2->autoneg == AUTONEG_DISABLE) {
517 + reg = gma_read16(hw, port, GM_GP_CTRL);
518 + reg |= GM_GPCR_AU_ALL_DIS;
519 + gma_write16(hw, port, GM_GP_CTRL, reg);
520 + gma_read16(hw, port, GM_GP_CTRL);
521 +
522 + switch (sky2->speed) {
523 + case SPEED_1000:
524 + reg |= GM_GPCR_SPEED_1000;
525 + /* fallthru */
526 + case SPEED_100:
527 + reg |= GM_GPCR_SPEED_100;
528 + }
529 +
530 + if (sky2->duplex == DUPLEX_FULL)
531 + reg |= GM_GPCR_DUP_FULL;
532 + } else
533 + reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
534 +
535 + if (!sky2->tx_pause && !sky2->rx_pause) {
536 + sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
537 + reg |=
538 + GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
539 + } else if (sky2->tx_pause && !sky2->rx_pause) {
540 + /* disable Rx flow-control */
541 + reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
542 + }
543 +
544 + gma_write16(hw, port, GM_GP_CTRL, reg);
545 +
546 + sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
547 +
548 + down(&sky2->phy_sema);
549 + sky2_phy_init(hw, port);
550 + up(&sky2->phy_sema);
551 +
552 + /* MIB clear */
553 + reg = gma_read16(hw, port, GM_PHY_ADDR);
554 + gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
555 +
556 + for (i = 0; i < GM_MIB_CNT_SIZE; i++)
557 + gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
558 + gma_write16(hw, port, GM_PHY_ADDR, reg);
559 +
560 + /* transmit control */
561 + gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
562 +
563 + /* receive control reg: unicast + multicast + no FCS */
564 + gma_write16(hw, port, GM_RX_CTRL,
565 + GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
566 +
567 + /* transmit flow control */
568 + gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
569 +
570 + /* transmit parameter */
571 + gma_write16(hw, port, GM_TX_PARAM,
572 + TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
573 + TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
574 + TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
575 + TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
576 +
577 + /* serial mode register */
578 + reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
579 + GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
580 +
581 + if (hw->dev[port]->mtu > ETH_DATA_LEN)
582 + reg |= GM_SMOD_JUMBO_ENA;
583 +
584 + gma_write16(hw, port, GM_SERIAL_MODE, reg);
585 +
586 + /* virtual address for data */
587 + gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
588 +
589 + /* physical address: used for pause frames */
590 + gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
591 +
592 + /* ignore counter overflows */
593 + gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
594 + gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
595 + gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
596 +
597 + /* Configure Rx MAC FIFO */
598 + sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
599 + sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
600 + GMF_RX_CTRL_DEF);
601 +
602 + /* Flush Rx MAC FIFO on any flow control or error */
603 + sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
604 +
605 + /* Set threshold to 0xa (64 bytes)
606 + * ASF disabled so no need to do WA dev #4.30
607 + */
608 + sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
609 +
610 + /* Configure Tx MAC FIFO */
611 + sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
612 + sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
613 +
614 + if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
615 + sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
616 + sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
617 + if (hw->dev[port]->mtu > ETH_DATA_LEN) {
618 + /* set Tx GMAC FIFO Almost Empty Threshold */
619 + sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
620 + /* Disable Store & Forward mode for TX */
621 + sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
622 + }
623 + }
624 +
625 +}
626 +
627 +/* Assign Ram Buffer allocation.
628 + * start and end are in units of 4k bytes
629 + * ram registers are in units of 64bit words
630 + */
631 +static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
632 +{
633 + u32 start, end;
634 +
635 + start = startk * 4096/8;
636 + end = (endk * 4096/8) - 1;
637 +
638 + sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
639 + sky2_write32(hw, RB_ADDR(q, RB_START), start);
640 + sky2_write32(hw, RB_ADDR(q, RB_END), end);
641 + sky2_write32(hw, RB_ADDR(q, RB_WP), start);
642 + sky2_write32(hw, RB_ADDR(q, RB_RP), start);
643 +
644 + if (q == Q_R1 || q == Q_R2) {
645 + u32 space = (endk - startk) * 4096/8;
646 + u32 tp = space - space/4;
647 +
648 + /* On receive queue's set the thresholds
649 + * give receiver priority when > 3/4 full
650 + * send pause when down to 2K
651 + */
652 + sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
653 + sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
654 +
655 + tp = space - 2048/8;
656 + sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
657 + sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
658 + } else {
659 + /* Enable store & forward on Tx queue's because
660 + * Tx FIFO is only 1K on Yukon
661 + */
662 + sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
663 + }
664 +
665 + sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
666 + sky2_read8(hw, RB_ADDR(q, RB_CTRL));
667 +}
668 +
669 +/* Setup Bus Memory Interface */
670 +static void sky2_qset(struct sky2_hw *hw, u16 q)
671 +{
672 + sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
673 + sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
674 + sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
675 + sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
676 +}
677 +
678 +/* Setup prefetch unit registers. This is the interface between
679 + * hardware and driver list elements
680 + */
681 +static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
682 + u64 addr, u32 last)
683 +{
684 + sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
685 + sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
686 + sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
687 + sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
688 + sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
689 + sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
690 +
691 + sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
692 +}
693 +
694 +static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
695 +{
696 + struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
697 +
698 + sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
699 + return le;
700 +}
701 +
702 +/*
703 + * This is a workaround code taken from SysKonnect sk98lin driver
704 + * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
705 + */
706 +static void sky2_put_idx(struct sky2_hw *hw, unsigned q,
707 + u16 idx, u16 *last, u16 size)
708 +{
709 + wmb();
710 + if (is_ec_a1(hw) && idx < *last) {
711 + u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
712 +
713 + if (hwget == 0) {
714 + /* Start prefetching again */
715 + sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
716 + goto setnew;
717 + }
718 +
719 + if (hwget == size - 1) {
720 + /* set watermark to one list element */
721 + sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
722 +
723 + /* set put index to first list element */
724 + sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
725 + } else /* have hardware go to end of list */
726 + sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
727 + size - 1);
728 + } else {
729 +setnew:
730 + sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
731 + }
732 + *last = idx;
733 + mmiowb();
734 +}
735 +
736 +
737 +static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
738 +{
739 + struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
740 + sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
741 + return le;
742 +}
743 +
744 +/* Return high part of DMA address (could be 32 or 64 bit) */
745 +static inline u32 high32(dma_addr_t a)
746 +{
747 + return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
748 +}
749 +
750 +/* Build description to hardware about buffer */
751 +static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
752 +{
753 + struct sky2_rx_le *le;
754 + u32 hi = high32(map);
755 + u16 len = sky2->rx_bufsize;
756 +
757 + if (sky2->rx_addr64 != hi) {
758 + le = sky2_next_rx(sky2);
759 + le->addr = cpu_to_le32(hi);
760 + le->ctrl = 0;
761 + le->opcode = OP_ADDR64 | HW_OWNER;
762 + sky2->rx_addr64 = high32(map + len);
763 + }
764 +
765 + le = sky2_next_rx(sky2);
766 + le->addr = cpu_to_le32((u32) map);
767 + le->length = cpu_to_le16(len);
768 + le->ctrl = 0;
769 + le->opcode = OP_PACKET | HW_OWNER;
770 +}
771 +
772 +
773 +/* Tell chip where to start receive checksum.
774 + * Actually has two checksums, but set both same to avoid possible byte
775 + * order problems.
776 + */
777 +static void rx_set_checksum(struct sky2_port *sky2)
778 +{
779 + struct sky2_rx_le *le;
780 +
781 + le = sky2_next_rx(sky2);
782 + le->addr = (ETH_HLEN << 16) | ETH_HLEN;
783 + le->ctrl = 0;
784 + le->opcode = OP_TCPSTART | HW_OWNER;
785 +
786 + sky2_write32(sky2->hw,
787 + Q_ADDR(rxqaddr[sky2->port], Q_CSR),
788 + sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
789 +
790 +}
791 +
792 +/*
793 + * The RX Stop command will not work for Yukon-2 if the BMU does not
794 + * reach the end of packet and since we can't make sure that we have
795 + * incoming data, we must reset the BMU while it is not doing a DMA
796 + * transfer. Since it is possible that the RX path is still active,
797 + * the RX RAM buffer will be stopped first, so any possible incoming
798 + * data will not trigger a DMA. After the RAM buffer is stopped, the
799 + * BMU is polled until any DMA in progress is ended and only then it
800 + * will be reset.
801 + */
802 +static void sky2_rx_stop(struct sky2_port *sky2)
803 +{
804 + struct sky2_hw *hw = sky2->hw;
805 + unsigned rxq = rxqaddr[sky2->port];
806 + int i;
807 +
808 + /* disable the RAM Buffer receive queue */
809 + sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
810 +
811 + for (i = 0; i < 0xffff; i++)
812 + if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
813 + == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
814 + goto stopped;
815 +
816 + printk(KERN_WARNING PFX "%s: receiver stop failed\n",
817 + sky2->netdev->name);
818 +stopped:
819 + sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
820 +
821 + /* reset the Rx prefetch unit */
822 + sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
823 +}
824 +
825 +/* Clean out receive buffer area, assumes receiver hardware stopped */
826 +static void sky2_rx_clean(struct sky2_port *sky2)
827 +{
828 + unsigned i;
829 +
830 + memset(sky2->rx_le, 0, RX_LE_BYTES);
831 + for (i = 0; i < sky2->rx_pending; i++) {
832 + struct ring_info *re = sky2->rx_ring + i;
833 +
834 + if (re->skb) {
835 + pci_unmap_single(sky2->hw->pdev,
836 + re->mapaddr, sky2->rx_bufsize,
837 + PCI_DMA_FROMDEVICE);
838 + kfree_skb(re->skb);
839 + re->skb = NULL;
840 + }
841 + }
842 +}
843 +
844 +/* Basic MII support */
845 +static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
846 +{
847 + struct mii_ioctl_data *data = if_mii(ifr);
848 + struct sky2_port *sky2 = netdev_priv(dev);
849 + struct sky2_hw *hw = sky2->hw;
850 + int err = -EOPNOTSUPP;
851 +
852 + if (!netif_running(dev))
853 + return -ENODEV; /* Phy still in reset */
854 +
855 + switch(cmd) {
856 + case SIOCGMIIPHY:
857 + data->phy_id = PHY_ADDR_MARV;
858 +
859 + /* fallthru */
860 + case SIOCGMIIREG: {
861 + u16 val = 0;
862 +
863 + down(&sky2->phy_sema);
864 + err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
865 + up(&sky2->phy_sema);
866 +
867 + data->val_out = val;
868 + break;
869 + }
870 +
871 + case SIOCSMIIREG:
872 + if (!capable(CAP_NET_ADMIN))
873 + return -EPERM;
874 +
875 + down(&sky2->phy_sema);
876 + err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
877 + data->val_in);
878 + up(&sky2->phy_sema);
879 + break;
880 + }
881 + return err;
882 +}
883 +
884 +#ifdef SKY2_VLAN_TAG_USED
885 +static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
886 +{
887 + struct sky2_port *sky2 = netdev_priv(dev);
888 + struct sky2_hw *hw = sky2->hw;
889 + u16 port = sky2->port;
890 +
891 + spin_lock_bh(&sky2->tx_lock);
892 +
893 + sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
894 + sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
895 + sky2->vlgrp = grp;
896 +
897 + spin_unlock_bh(&sky2->tx_lock);
898 +}
899 +
900 +static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
901 +{
902 + struct sky2_port *sky2 = netdev_priv(dev);
903 + struct sky2_hw *hw = sky2->hw;
904 + u16 port = sky2->port;
905 +
906 + spin_lock_bh(&sky2->tx_lock);
907 +
908 + sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
909 + sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
910 + if (sky2->vlgrp)
911 + sky2->vlgrp->vlan_devices[vid] = NULL;
912 +
913 + spin_unlock_bh(&sky2->tx_lock);
914 +}
915 +#endif
916 +
917 +/*
918 + * It appears the hardware has a bug in the FIFO logic that
919 + * cause it to hang if the FIFO gets overrun and the receive buffer
920 + * is not aligned. ALso alloc_skb() won't align properly if slab
921 + * debugging is enabled.
922 + */
923 +static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
924 +{
925 + struct sk_buff *skb;
926 +
927 + skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
928 + if (likely(skb)) {
929 + unsigned long p = (unsigned long) skb->data;
930 + skb_reserve(skb,
931 + ((p + RX_SKB_ALIGN - 1) & ~(RX_SKB_ALIGN - 1)) - p);
932 + }
933 +
934 + return skb;
935 +}
936 +
937 +/*
938 + * Allocate and setup receiver buffer pool.
939 + * In case of 64 bit dma, there are 2X as many list elements
940 + * available as ring entries
941 + * and need to reserve one list element so we don't wrap around.
942 + */
943 +static int sky2_rx_start(struct sky2_port *sky2)
944 +{
945 + struct sky2_hw *hw = sky2->hw;
946 + unsigned rxq = rxqaddr[sky2->port];
947 + int i;
948 +
949 + sky2->rx_put = sky2->rx_next = 0;
950 + sky2_qset(hw, rxq);
951 + sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
952 +
953 + rx_set_checksum(sky2);
954 + for (i = 0; i < sky2->rx_pending; i++) {
955 + struct ring_info *re = sky2->rx_ring + i;
956 +
957 + re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
958 + if (!re->skb)
959 + goto nomem;
960 +
961 + re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
962 + sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
963 + sky2_rx_add(sky2, re->mapaddr);
964 + }
965 +
966 + /* Tell chip about available buffers */
967 + sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
968 + sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
969 + return 0;
970 +nomem:
971 + sky2_rx_clean(sky2);
972 + return -ENOMEM;
973 +}
974 +
975 +/* Bring up network interface. */
976 +static int sky2_up(struct net_device *dev)
977 +{
978 + struct sky2_port *sky2 = netdev_priv(dev);
979 + struct sky2_hw *hw = sky2->hw;
980 + unsigned port = sky2->port;
981 + u32 ramsize, rxspace;
982 + int err = -ENOMEM;
983 +
984 + if (netif_msg_ifup(sky2))
985 + printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
986 +
987 + /* must be power of 2 */
988 + sky2->tx_le = pci_alloc_consistent(hw->pdev,
989 + TX_RING_SIZE *
990 + sizeof(struct sky2_tx_le),
991 + &sky2->tx_le_map);
992 + if (!sky2->tx_le)
993 + goto err_out;
994 +
995 + sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
996 + GFP_KERNEL);
997 + if (!sky2->tx_ring)
998 + goto err_out;
999 + sky2->tx_prod = sky2->tx_cons = 0;
1000 +
1001 + sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1002 + &sky2->rx_le_map);
1003 + if (!sky2->rx_le)
1004 + goto err_out;
1005 + memset(sky2->rx_le, 0, RX_LE_BYTES);
1006 +
1007 + sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
1008 + GFP_KERNEL);
1009 + if (!sky2->rx_ring)
1010 + goto err_out;
1011 +
1012 + sky2_mac_init(hw, port);
1013 +
1014 + /* Determine available ram buffer space (in 4K blocks).
1015 + * Note: not sure about the FE setting below yet
1016 + */
1017 + if (hw->chip_id == CHIP_ID_YUKON_FE)
1018 + ramsize = 4;
1019 + else
1020 + ramsize = sky2_read8(hw, B2_E_0);
1021 +
1022 + /* Give transmitter one third (rounded up) */
1023 + rxspace = ramsize - (ramsize + 2) / 3;
1024 +
1025 + sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1026 + sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
1027 +
1028 + /* Make sure SyncQ is disabled */
1029 + sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1030 + RB_RST_SET);
1031 +
1032 + sky2_qset(hw, txqaddr[port]);
1033 + if (hw->chip_id == CHIP_ID_YUKON_EC_U)
1034 + sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1035 +
1036 +
1037 + sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1038 + TX_RING_SIZE - 1);
1039 +
1040 + err = sky2_rx_start(sky2);
1041 + if (err)
1042 + goto err_out;
1043 +
1044 + /* Enable interrupts from phy/mac for port */
1045 + hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1046 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
1047 + return 0;
1048 +
1049 +err_out:
1050 + if (sky2->rx_le) {
1051 + pci_free_consistent(hw->pdev, RX_LE_BYTES,
1052 + sky2->rx_le, sky2->rx_le_map);
1053 + sky2->rx_le = NULL;
1054 + }
1055 + if (sky2->tx_le) {
1056 + pci_free_consistent(hw->pdev,
1057 + TX_RING_SIZE * sizeof(struct sky2_tx_le),
1058 + sky2->tx_le, sky2->tx_le_map);
1059 + sky2->tx_le = NULL;
1060 + }
1061 + kfree(sky2->tx_ring);
1062 + kfree(sky2->rx_ring);
1063 +
1064 + sky2->tx_ring = NULL;
1065 + sky2->rx_ring = NULL;
1066 + return err;
1067 +}
1068 +
1069 +/* Modular subtraction in ring */
1070 +static inline int tx_dist(unsigned tail, unsigned head)
1071 +{
1072 + return (head - tail) % TX_RING_SIZE;
1073 +}
1074 +
1075 +/* Number of list elements available for next tx */
1076 +static inline int tx_avail(const struct sky2_port *sky2)
1077 +{
1078 + return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1079 +}
1080 +
1081 +/* Estimate of number of transmit list elements required */
1082 +static unsigned tx_le_req(const struct sk_buff *skb)
1083 +{
1084 + unsigned count;
1085 +
1086 + count = sizeof(dma_addr_t) / sizeof(u32);
1087 + count += skb_shinfo(skb)->nr_frags * count;
1088 +
1089 + if (skb_shinfo(skb)->tso_size)
1090 + ++count;
1091 +
1092 + if (skb->ip_summed == CHECKSUM_HW)
1093 + ++count;
1094 +
1095 + return count;
1096 +}
1097 +
1098 +/*
1099 + * Put one packet in ring for transmit.
1100 + * A single packet can generate multiple list elements, and
1101 + * the number of ring elements will probably be less than the number
1102 + * of list elements used.
1103 + *
1104 + * No BH disabling for tx_lock here (like tg3)
1105 + */
1106 +static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1107 +{
1108 + struct sky2_port *sky2 = netdev_priv(dev);
1109 + struct sky2_hw *hw = sky2->hw;
1110 + struct sky2_tx_le *le = NULL;
1111 + struct tx_ring_info *re;
1112 + unsigned i, len;
1113 + dma_addr_t mapping;
1114 + u32 addr64;
1115 + u16 mss;
1116 + u8 ctrl;
1117 +
1118 + /* No BH disabling for tx_lock here. We are running in BH disabled
1119 + * context and TX reclaim runs via poll inside of a software
1120 + * interrupt, and no related locks in IRQ processing.
1121 + */
1122 + if (!spin_trylock(&sky2->tx_lock))
1123 + return NETDEV_TX_LOCKED;
1124 +
1125 + if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1126 + /* There is a known but harmless race with lockless tx
1127 + * and netif_stop_queue.
1128 + */
1129 + if (!netif_queue_stopped(dev)) {
1130 + netif_stop_queue(dev);
1131 + if (net_ratelimit())
1132 + printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1133 + dev->name);
1134 + }
1135 + spin_unlock(&sky2->tx_lock);
1136 +
1137 + return NETDEV_TX_BUSY;
1138 + }
1139 +
1140 + if (unlikely(netif_msg_tx_queued(sky2)))
1141 + printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1142 + dev->name, sky2->tx_prod, skb->len);
1143 +
1144 + len = skb_headlen(skb);
1145 + mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1146 + addr64 = high32(mapping);
1147 +
1148 + re = sky2->tx_ring + sky2->tx_prod;
1149 +
1150 + /* Send high bits if changed or crosses boundary */
1151 + if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1152 + le = get_tx_le(sky2);
1153 + le->tx.addr = cpu_to_le32(addr64);
1154 + le->ctrl = 0;
1155 + le->opcode = OP_ADDR64 | HW_OWNER;
1156 + sky2->tx_addr64 = high32(mapping + len);
1157 + }
1158 +
1159 + /* Check for TCP Segmentation Offload */
1160 + mss = skb_shinfo(skb)->tso_size;
1161 + if (mss != 0) {
1162 + /* just drop the packet if non-linear expansion fails */
1163 + if (skb_header_cloned(skb) &&
1164 + pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
1165 + dev_kfree_skb_any(skb);
1166 + goto out_unlock;
1167 + }
1168 +
1169 + mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1170 + mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1171 + mss += ETH_HLEN;
1172 + }
1173 +
1174 + if (mss != sky2->tx_last_mss) {
1175 + le = get_tx_le(sky2);
1176 + le->tx.tso.size = cpu_to_le16(mss);
1177 + le->tx.tso.rsvd = 0;
1178 + le->opcode = OP_LRGLEN | HW_OWNER;
1179 + le->ctrl = 0;
1180 + sky2->tx_last_mss = mss;
1181 + }
1182 +
1183 + ctrl = 0;
1184 +#ifdef SKY2_VLAN_TAG_USED
1185 + /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1186 + if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1187 + if (!le) {
1188 + le = get_tx_le(sky2);
1189 + le->tx.addr = 0;
1190 + le->opcode = OP_VLAN|HW_OWNER;
1191 + le->ctrl = 0;
1192 + } else
1193 + le->opcode |= OP_VLAN;
1194 + le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1195 + ctrl |= INS_VLAN;
1196 + }
1197 +#endif
1198 +
1199 + /* Handle TCP checksum offload */
1200 + if (skb->ip_summed == CHECKSUM_HW) {
1201 + u16 hdr = skb->h.raw - skb->data;
1202 + u16 offset = hdr + skb->csum;
1203 +
1204 + ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1205 + if (skb->nh.iph->protocol == IPPROTO_UDP)
1206 + ctrl |= UDPTCP;
1207 +
1208 + le = get_tx_le(sky2);
1209 + le->tx.csum.start = cpu_to_le16(hdr);
1210 + le->tx.csum.offset = cpu_to_le16(offset);
1211 + le->length = 0; /* initial checksum value */
1212 + le->ctrl = 1; /* one packet */
1213 + le->opcode = OP_TCPLISW | HW_OWNER;
1214 + }
1215 +
1216 + le = get_tx_le(sky2);
1217 + le->tx.addr = cpu_to_le32((u32) mapping);
1218 + le->length = cpu_to_le16(len);
1219 + le->ctrl = ctrl;
1220 + le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1221 +
1222 + /* Record the transmit mapping info */
1223 + re->skb = skb;
1224 + pci_unmap_addr_set(re, mapaddr, mapping);
1225 +
1226 + for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1227 + skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1228 + struct tx_ring_info *fre;
1229 +
1230 + mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1231 + frag->size, PCI_DMA_TODEVICE);
1232 + addr64 = high32(mapping);
1233 + if (addr64 != sky2->tx_addr64) {
1234 + le = get_tx_le(sky2);
1235 + le->tx.addr = cpu_to_le32(addr64);
1236 + le->ctrl = 0;
1237 + le->opcode = OP_ADDR64 | HW_OWNER;
1238 + sky2->tx_addr64 = addr64;
1239 + }
1240 +
1241 + le = get_tx_le(sky2);
1242 + le->tx.addr = cpu_to_le32((u32) mapping);
1243 + le->length = cpu_to_le16(frag->size);
1244 + le->ctrl = ctrl;
1245 + le->opcode = OP_BUFFER | HW_OWNER;
1246 +
1247 + fre = sky2->tx_ring
1248 + + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
1249 + pci_unmap_addr_set(fre, mapaddr, mapping);
1250 + }
1251 +
1252 + re->idx = sky2->tx_prod;
1253 + le->ctrl |= EOP;
1254 +
1255 + sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
1256 + &sky2->tx_last_put, TX_RING_SIZE);
1257 +
1258 + if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1259 + netif_stop_queue(dev);
1260 +
1261 +out_unlock:
1262 + spin_unlock(&sky2->tx_lock);
1263 +
1264 + dev->trans_start = jiffies;
1265 + return NETDEV_TX_OK;
1266 +}
1267 +
1268 +/*
1269 + * Free ring elements from starting at tx_cons until "done"
1270 + *
1271 + * NB: the hardware will tell us about partial completion of multi-part
1272 + * buffers; these are deferred until completion.
1273 + */
1274 +static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1275 +{
1276 + struct net_device *dev = sky2->netdev;
1277 + struct pci_dev *pdev = sky2->hw->pdev;
1278 + u16 nxt, put;
1279 + unsigned i;
1280 +
1281 + BUG_ON(done >= TX_RING_SIZE);
1282 +
1283 + if (unlikely(netif_msg_tx_done(sky2)))
1284 + printk(KERN_DEBUG "%s: tx done, up to %u\n",
1285 + dev->name, done);
1286 +
1287 + for (put = sky2->tx_cons; put != done; put = nxt) {
1288 + struct tx_ring_info *re = sky2->tx_ring + put;
1289 + struct sk_buff *skb = re->skb;
1290 +
1291 + nxt = re->idx;
1292 + BUG_ON(nxt >= TX_RING_SIZE);
1293 + prefetch(sky2->tx_ring + nxt);
1294 +
1295 + /* Check for partial status */
1296 + if (tx_dist(put, done) < tx_dist(put, nxt))
1297 + break;
1298 +
1299 + skb = re->skb;
1300 + pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1301 + skb_headlen(skb), PCI_DMA_TODEVICE);
1302 +
1303 + for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1304 + struct tx_ring_info *fre;
1305 + fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE;
1306 + pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
1307 + skb_shinfo(skb)->frags[i].size,
1308 + PCI_DMA_TODEVICE);
1309 + }
1310 +
1311 + dev_kfree_skb_any(skb);
1312 + }
1313 +
1314 + sky2->tx_cons = put;
1315 + if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
1316 + netif_wake_queue(dev);
1317 +}
1318 +
1319 +/* Cleanup all untransmitted buffers, assume transmitter not running */
1320 +static void sky2_tx_clean(struct sky2_port *sky2)
1321 +{
1322 + spin_lock_bh(&sky2->tx_lock);
1323 + sky2_tx_complete(sky2, sky2->tx_prod);
1324 + spin_unlock_bh(&sky2->tx_lock);
1325 +}
1326 +
1327 +/* Network shutdown */
1328 +static int sky2_down(struct net_device *dev)
1329 +{
1330 + struct sky2_port *sky2 = netdev_priv(dev);
1331 + struct sky2_hw *hw = sky2->hw;
1332 + unsigned port = sky2->port;
1333 + u16 ctrl;
1334 +
1335 + /* Never really got started! */
1336 + if (!sky2->tx_le)
1337 + return 0;
1338 +
1339 + if (netif_msg_ifdown(sky2))
1340 + printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1341 +
1342 + /* Stop more packets from being queued */
1343 + netif_stop_queue(dev);
1344 +
1345 + /* Disable port IRQ */
1346 + local_irq_disable();
1347 + hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1348 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
1349 + local_irq_enable();
1350 +
1351 + flush_scheduled_work();
1352 +
1353 + sky2_phy_reset(hw, port);
1354 +
1355 + /* Stop transmitter */
1356 + sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1357 + sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1358 +
1359 + sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1360 + RB_RST_SET | RB_DIS_OP_MD);
1361 +
1362 + ctrl = gma_read16(hw, port, GM_GP_CTRL);
1363 + ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1364 + gma_write16(hw, port, GM_GP_CTRL, ctrl);
1365 +
1366 + sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1367 +
1368 + /* Workaround shared GMAC reset */
1369 + if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1370 + && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1371 + sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1372 +
1373 + /* Disable Force Sync bit and Enable Alloc bit */
1374 + sky2_write8(hw, SK_REG(port, TXA_CTRL),
1375 + TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1376 +
1377 + /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1378 + sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1379 + sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1380 +
1381 + /* Reset the PCI FIFO of the async Tx queue */
1382 + sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1383 + BMU_RST_SET | BMU_FIFO_RST);
1384 +
1385 + /* Reset the Tx prefetch units */
1386 + sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1387 + PREF_UNIT_RST_SET);
1388 +
1389 + sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1390 +
1391 + sky2_rx_stop(sky2);
1392 +
1393 + sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1394 + sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1395 +
1396 + /* turn off LED's */
1397 + sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1398 +
1399 + synchronize_irq(hw->pdev->irq);
1400 +
1401 + sky2_tx_clean(sky2);
1402 + sky2_rx_clean(sky2);
1403 +
1404 + pci_free_consistent(hw->pdev, RX_LE_BYTES,
1405 + sky2->rx_le, sky2->rx_le_map);
1406 + kfree(sky2->rx_ring);
1407 +
1408 + pci_free_consistent(hw->pdev,
1409 + TX_RING_SIZE * sizeof(struct sky2_tx_le),
1410 + sky2->tx_le, sky2->tx_le_map);
1411 + kfree(sky2->tx_ring);
1412 +
1413 + sky2->tx_le = NULL;
1414 + sky2->rx_le = NULL;
1415 +
1416 + sky2->rx_ring = NULL;
1417 + sky2->tx_ring = NULL;
1418 +
1419 + return 0;
1420 +}
1421 +
1422 +static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1423 +{
1424 + if (!hw->copper)
1425 + return SPEED_1000;
1426 +
1427 + if (hw->chip_id == CHIP_ID_YUKON_FE)
1428 + return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1429 +
1430 + switch (aux & PHY_M_PS_SPEED_MSK) {
1431 + case PHY_M_PS_SPEED_1000:
1432 + return SPEED_1000;
1433 + case PHY_M_PS_SPEED_100:
1434 + return SPEED_100;
1435 + default:
1436 + return SPEED_10;
1437 + }
1438 +}
1439 +
1440 +static void sky2_link_up(struct sky2_port *sky2)
1441 +{
1442 + struct sky2_hw *hw = sky2->hw;
1443 + unsigned port = sky2->port;
1444 + u16 reg;
1445 +
1446 + /* Enable Transmit FIFO Underrun */
1447 + sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1448 +
1449 + reg = gma_read16(hw, port, GM_GP_CTRL);
1450 + if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1451 + reg |= GM_GPCR_DUP_FULL;
1452 +
1453 + /* enable Rx/Tx */
1454 + reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1455 + gma_write16(hw, port, GM_GP_CTRL, reg);
1456 + gma_read16(hw, port, GM_GP_CTRL);
1457 +
1458 + gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1459 +
1460 + netif_carrier_on(sky2->netdev);
1461 + netif_wake_queue(sky2->netdev);
1462 +
1463 + /* Turn on link LED */
1464 + sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1465 + LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1466 +
1467 + if (hw->chip_id == CHIP_ID_YUKON_XL) {
1468 + u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1469 +
1470 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1471 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1472 + PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1473 + SPEED_10 ? 7 : 0) |
1474 + PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1475 + SPEED_100 ? 7 : 0) |
1476 + PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1477 + SPEED_1000 ? 7 : 0));
1478 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1479 + }
1480 +
1481 + if (netif_msg_link(sky2))
1482 + printk(KERN_INFO PFX
1483 + "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1484 + sky2->netdev->name, sky2->speed,
1485 + sky2->duplex == DUPLEX_FULL ? "full" : "half",
1486 + (sky2->tx_pause && sky2->rx_pause) ? "both" :
1487 + sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1488 +}
1489 +
1490 +static void sky2_link_down(struct sky2_port *sky2)
1491 +{
1492 + struct sky2_hw *hw = sky2->hw;
1493 + unsigned port = sky2->port;
1494 + u16 reg;
1495 +
1496 + gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1497 +
1498 + reg = gma_read16(hw, port, GM_GP_CTRL);
1499 + reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1500 + gma_write16(hw, port, GM_GP_CTRL, reg);
1501 + gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1502 +
1503 + if (sky2->rx_pause && !sky2->tx_pause) {
1504 + /* restore Asymmetric Pause bit */
1505 + gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1506 + gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1507 + | PHY_M_AN_ASP);
1508 + }
1509 +
1510 + netif_carrier_off(sky2->netdev);
1511 + netif_stop_queue(sky2->netdev);
1512 +
1513 + /* Turn on link LED */
1514 + sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1515 +
1516 + if (netif_msg_link(sky2))
1517 + printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1518 + sky2_phy_init(hw, port);
1519 +}
1520 +
1521 +static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1522 +{
1523 + struct sky2_hw *hw = sky2->hw;
1524 + unsigned port = sky2->port;
1525 + u16 lpa;
1526 +
1527 + lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1528 +
1529 + if (lpa & PHY_M_AN_RF) {
1530 + printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1531 + return -1;
1532 + }
1533 +
1534 + if (hw->chip_id != CHIP_ID_YUKON_FE &&
1535 + gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1536 + printk(KERN_ERR PFX "%s: master/slave fault",
1537 + sky2->netdev->name);
1538 + return -1;
1539 + }
1540 +
1541 + if (!(aux & PHY_M_PS_SPDUP_RES)) {
1542 + printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1543 + sky2->netdev->name);
1544 + return -1;
1545 + }
1546 +
1547 + sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1548 +
1549 + sky2->speed = sky2_phy_speed(hw, aux);
1550 +
1551 + /* Pause bits are offset (9..8) */
1552 + if (hw->chip_id == CHIP_ID_YUKON_XL)
1553 + aux >>= 6;
1554 +
1555 + sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1556 + sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1557 +
1558 + if ((sky2->tx_pause || sky2->rx_pause)
1559 + && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1560 + sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1561 + else
1562 + sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1563 +
1564 + return 0;
1565 +}
1566 +
1567 +/*
1568 + * Interrupt from PHY are handled outside of interrupt context
1569 + * because accessing phy registers requires spin wait which might
1570 + * cause excess interrupt latency.
1571 + */
1572 +static void sky2_phy_task(void *arg)
1573 +{
1574 + struct sky2_port *sky2 = arg;
1575 + struct sky2_hw *hw = sky2->hw;
1576 + u16 istatus, phystat;
1577 +
1578 + down(&sky2->phy_sema);
1579 + istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1580 + phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
1581 +
1582 + if (netif_msg_intr(sky2))
1583 + printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1584 + sky2->netdev->name, istatus, phystat);
1585 +
1586 + if (istatus & PHY_M_IS_AN_COMPL) {
1587 + if (sky2_autoneg_done(sky2, phystat) == 0)
1588 + sky2_link_up(sky2);
1589 + goto out;
1590 + }
1591 +
1592 + if (istatus & PHY_M_IS_LSP_CHANGE)
1593 + sky2->speed = sky2_phy_speed(hw, phystat);
1594 +
1595 + if (istatus & PHY_M_IS_DUP_CHANGE)
1596 + sky2->duplex =
1597 + (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1598 +
1599 + if (istatus & PHY_M_IS_LST_CHANGE) {
1600 + if (phystat & PHY_M_PS_LINK_UP)
1601 + sky2_link_up(sky2);
1602 + else
1603 + sky2_link_down(sky2);
1604 + }
1605 +out:
1606 + up(&sky2->phy_sema);
1607 +
1608 + local_irq_disable();
1609 + hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
1610 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
1611 + local_irq_enable();
1612 +}
1613 +
1614 +
1615 +/* Transmit timeout is only called if we are running, carries is up
1616 + * and tx queue is full (stopped).
1617 + */
1618 +static void sky2_tx_timeout(struct net_device *dev)
1619 +{
1620 + struct sky2_port *sky2 = netdev_priv(dev);
1621 + struct sky2_hw *hw = sky2->hw;
1622 + unsigned txq = txqaddr[sky2->port];
1623 + u16 ridx;
1624 +
1625 + /* Maybe we just missed an status interrupt */
1626 + spin_lock(&sky2->tx_lock);
1627 + ridx = sky2_read16(hw,
1628 + sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1629 + sky2_tx_complete(sky2, ridx);
1630 + spin_unlock(&sky2->tx_lock);
1631 +
1632 + if (!netif_queue_stopped(dev)) {
1633 + if (net_ratelimit())
1634 + pr_info(PFX "transmit interrupt missed? recovered\n");
1635 + return;
1636 + }
1637 +
1638 + if (netif_msg_timer(sky2))
1639 + printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1640 +
1641 + sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1642 + sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1643 +
1644 + sky2_tx_clean(sky2);
1645 +
1646 + sky2_qset(hw, txq);
1647 + sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1648 +}
1649 +
1650 +
1651 +#define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
1652 +/* Want receive buffer size to be multiple of 64 bits, and incl room for vlan */
1653 +static inline unsigned sky2_buf_size(int mtu)
1654 +{
1655 + return roundup(mtu + ETH_HLEN + 4, 8);
1656 +}
1657 +
1658 +static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1659 +{
1660 + struct sky2_port *sky2 = netdev_priv(dev);
1661 + struct sky2_hw *hw = sky2->hw;
1662 + int err;
1663 + u16 ctl, mode;
1664 +
1665 + if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1666 + return -EINVAL;
1667 +
1668 + if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1669 + return -EINVAL;
1670 +
1671 + if (!netif_running(dev)) {
1672 + dev->mtu = new_mtu;
1673 + return 0;
1674 + }
1675 +
1676 + sky2_write32(hw, B0_IMSK, 0);
1677 +
1678 + dev->trans_start = jiffies; /* prevent tx timeout */
1679 + netif_stop_queue(dev);
1680 + netif_poll_disable(hw->dev[0]);
1681 +
1682 + ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1683 + gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1684 + sky2_rx_stop(sky2);
1685 + sky2_rx_clean(sky2);
1686 +
1687 + dev->mtu = new_mtu;
1688 + sky2->rx_bufsize = sky2_buf_size(new_mtu);
1689 + mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1690 + GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1691 +
1692 + if (dev->mtu > ETH_DATA_LEN)
1693 + mode |= GM_SMOD_JUMBO_ENA;
1694 +
1695 + gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1696 +
1697 + sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1698 +
1699 + err = sky2_rx_start(sky2);
1700 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
1701 +
1702 + if (err)
1703 + dev_close(dev);
1704 + else {
1705 + gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1706 +
1707 + netif_poll_enable(hw->dev[0]);
1708 + netif_wake_queue(dev);
1709 + }
1710 +
1711 + return err;
1712 +}
1713 +
1714 +/*
1715 + * Receive one packet.
1716 + * For small packets or errors, just reuse existing skb.
1717 + * For larger packets, get new buffer.
1718 + */
1719 +static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1720 + u16 length, u32 status)
1721 +{
1722 + struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1723 + struct sk_buff *skb = NULL;
1724 +
1725 + if (unlikely(netif_msg_rx_status(sky2)))
1726 + printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1727 + sky2->netdev->name, sky2->rx_next, status, length);
1728 +
1729 + sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1730 + prefetch(sky2->rx_ring + sky2->rx_next);
1731 +
1732 + if (status & GMR_FS_ANY_ERR)
1733 + goto error;
1734 +
1735 + if (!(status & GMR_FS_RX_OK))
1736 + goto resubmit;
1737 +
1738 + if ((status >> 16) != length || length > sky2->rx_bufsize)
1739 + goto oversize;
1740 +
1741 + if (length < copybreak) {
1742 + skb = alloc_skb(length + 2, GFP_ATOMIC);
1743 + if (!skb)
1744 + goto resubmit;
1745 +
1746 + skb_reserve(skb, 2);
1747 + pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1748 + length, PCI_DMA_FROMDEVICE);
1749 + memcpy(skb->data, re->skb->data, length);
1750 + skb->ip_summed = re->skb->ip_summed;
1751 + skb->csum = re->skb->csum;
1752 + pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1753 + length, PCI_DMA_FROMDEVICE);
1754 + } else {
1755 + struct sk_buff *nskb;
1756 +
1757 + nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
1758 + if (!nskb)
1759 + goto resubmit;
1760 +
1761 + skb = re->skb;
1762 + re->skb = nskb;
1763 + pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1764 + sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1765 + prefetch(skb->data);
1766 +
1767 + re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1768 + sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1769 + }
1770 +
1771 + skb_put(skb, length);
1772 +resubmit:
1773 + re->skb->ip_summed = CHECKSUM_NONE;
1774 + sky2_rx_add(sky2, re->mapaddr);
1775 +
1776 + /* Tell receiver about new buffers. */
1777 + sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
1778 + &sky2->rx_last_put, RX_LE_SIZE);
1779 +
1780 + return skb;
1781 +
1782 +oversize:
1783 + ++sky2->net_stats.rx_over_errors;
1784 + goto resubmit;
1785 +
1786 +error:
1787 + ++sky2->net_stats.rx_errors;
1788 +
1789 + if (netif_msg_rx_err(sky2) && net_ratelimit())
1790 + printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1791 + sky2->netdev->name, status, length);
1792 +
1793 + if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1794 + sky2->net_stats.rx_length_errors++;
1795 + if (status & GMR_FS_FRAGMENT)
1796 + sky2->net_stats.rx_frame_errors++;
1797 + if (status & GMR_FS_CRC_ERR)
1798 + sky2->net_stats.rx_crc_errors++;
1799 + if (status & GMR_FS_RX_FF_OV)
1800 + sky2->net_stats.rx_fifo_errors++;
1801 +
1802 + goto resubmit;
1803 +}
1804 +
1805 +/*
1806 + * Check for transmit complete
1807 + */
1808 +#define TX_NO_STATUS 0xffff
1809 +
1810 +static void sky2_tx_check(struct sky2_hw *hw, int port, u16 last)
1811 +{
1812 + if (last != TX_NO_STATUS) {
1813 + struct net_device *dev = hw->dev[port];
1814 + if (dev && netif_running(dev)) {
1815 + struct sky2_port *sky2 = netdev_priv(dev);
1816 +
1817 + spin_lock(&sky2->tx_lock);
1818 + sky2_tx_complete(sky2, last);
1819 + spin_unlock(&sky2->tx_lock);
1820 + }
1821 + }
1822 +}
1823 +
1824 +/*
1825 + * Both ports share the same status interrupt, therefore there is only
1826 + * one poll routine.
1827 + */
1828 +static int sky2_poll(struct net_device *dev0, int *budget)
1829 +{
1830 + struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1831 + unsigned int to_do = min(dev0->quota, *budget);
1832 + unsigned int work_done = 0;
1833 + u16 hwidx;
1834 + u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS };
1835 +
1836 + sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1837 +
1838 + hwidx = sky2_read16(hw, STAT_PUT_IDX);
1839 + BUG_ON(hwidx >= STATUS_RING_SIZE);
1840 + rmb();
1841 +
1842 + while (hwidx != hw->st_idx) {
1843 + struct sky2_status_le *le = hw->st_le + hw->st_idx;
1844 + struct net_device *dev;
1845 + struct sky2_port *sky2;
1846 + struct sk_buff *skb;
1847 + u32 status;
1848 + u16 length;
1849 +
1850 + le = hw->st_le + hw->st_idx;
1851 + hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
1852 + prefetch(hw->st_le + hw->st_idx);
1853 +
1854 + BUG_ON(le->link >= 2);
1855 + dev = hw->dev[le->link];
1856 + if (dev == NULL || !netif_running(dev))
1857 + continue;
1858 +
1859 + sky2 = netdev_priv(dev);
1860 + status = le32_to_cpu(le->status);
1861 + length = le16_to_cpu(le->length);
1862 +
1863 + switch (le->opcode & ~HW_OWNER) {
1864 + case OP_RXSTAT:
1865 + skb = sky2_receive(sky2, length, status);
1866 + if (!skb)
1867 + break;
1868 +
1869 + skb->dev = dev;
1870 + skb->protocol = eth_type_trans(skb, dev);
1871 + dev->last_rx = jiffies;
1872 +
1873 +#ifdef SKY2_VLAN_TAG_USED
1874 + if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1875 + vlan_hwaccel_receive_skb(skb,
1876 + sky2->vlgrp,
1877 + be16_to_cpu(sky2->rx_tag));
1878 + } else
1879 +#endif
1880 + netif_receive_skb(skb);
1881 +
1882 + if (++work_done >= to_do)
1883 + goto exit_loop;
1884 + break;
1885 +
1886 +#ifdef SKY2_VLAN_TAG_USED
1887 + case OP_RXVLAN:
1888 + sky2->rx_tag = length;
1889 + break;
1890 +
1891 + case OP_RXCHKSVLAN:
1892 + sky2->rx_tag = length;
1893 + /* fall through */
1894 +#endif
1895 + case OP_RXCHKS:
1896 + skb = sky2->rx_ring[sky2->rx_next].skb;
1897 + skb->ip_summed = CHECKSUM_HW;
1898 + skb->csum = le16_to_cpu(status);
1899 + break;
1900 +
1901 + case OP_TXINDEXLE:
1902 + /* TX index reports status for both ports */
1903 + tx_done[0] = status & 0xffff;
1904 + tx_done[1] = ((status >> 24) & 0xff)
1905 + | (u16)(length & 0xf) << 8;
1906 + break;
1907 +
1908 + default:
1909 + if (net_ratelimit())
1910 + printk(KERN_WARNING PFX
1911 + "unknown status opcode 0x%x\n", le->opcode);
1912 + break;
1913 + }
1914 + }
1915 +
1916 +exit_loop:
1917 + sky2_tx_check(hw, 0, tx_done[0]);
1918 + sky2_tx_check(hw, 1, tx_done[1]);
1919 +
1920 + if (likely(work_done < to_do)) {
1921 + /* need to restart TX timer */
1922 + if (is_ec_a1(hw)) {
1923 + sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1924 + sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1925 + }
1926 +
1927 + netif_rx_complete(dev0);
1928 + hw->intr_mask |= Y2_IS_STAT_BMU;
1929 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
1930 + return 0;
1931 + } else {
1932 + *budget -= work_done;
1933 + dev0->quota -= work_done;
1934 + return 1;
1935 + }
1936 +}
1937 +
1938 +static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1939 +{
1940 + struct net_device *dev = hw->dev[port];
1941 +
1942 + if (net_ratelimit())
1943 + printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1944 + dev->name, status);
1945 +
1946 + if (status & Y2_IS_PAR_RD1) {
1947 + if (net_ratelimit())
1948 + printk(KERN_ERR PFX "%s: ram data read parity error\n",
1949 + dev->name);
1950 + /* Clear IRQ */
1951 + sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1952 + }
1953 +
1954 + if (status & Y2_IS_PAR_WR1) {
1955 + if (net_ratelimit())
1956 + printk(KERN_ERR PFX "%s: ram data write parity error\n",
1957 + dev->name);
1958 +
1959 + sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1960 + }
1961 +
1962 + if (status & Y2_IS_PAR_MAC1) {
1963 + if (net_ratelimit())
1964 + printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
1965 + sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1966 + }
1967 +
1968 + if (status & Y2_IS_PAR_RX1) {
1969 + if (net_ratelimit())
1970 + printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
1971 + sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1972 + }
1973 +
1974 + if (status & Y2_IS_TCP_TXA1) {
1975 + if (net_ratelimit())
1976 + printk(KERN_ERR PFX "%s: TCP segmentation error\n",
1977 + dev->name);
1978 + sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1979 + }
1980 +}
1981 +
1982 +static void sky2_hw_intr(struct sky2_hw *hw)
1983 +{
1984 + u32 status = sky2_read32(hw, B0_HWE_ISRC);
1985 +
1986 + if (status & Y2_IS_TIST_OV)
1987 + sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1988 +
1989 + if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
1990 + u16 pci_err;
1991 +
1992 + pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
1993 + if (net_ratelimit())
1994 + printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
1995 + pci_name(hw->pdev), pci_err);
1996 +
1997 + sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1998 + pci_write_config_word(hw->pdev, PCI_STATUS,
1999 + pci_err | PCI_STATUS_ERROR_BITS);
2000 + sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2001 + }
2002 +
2003 + if (status & Y2_IS_PCI_EXP) {
2004 + /* PCI-Express uncorrectable Error occurred */
2005 + u32 pex_err;
2006 +
2007 + pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
2008 +
2009 + if (net_ratelimit())
2010 + printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2011 + pci_name(hw->pdev), pex_err);
2012 +
2013 + /* clear the interrupt */
2014 + sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2015 + pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
2016 + 0xffffffffUL);
2017 + sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2018 +
2019 + if (pex_err & PEX_FATAL_ERRORS) {
2020 + u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2021 + hwmsk &= ~Y2_IS_PCI_EXP;
2022 + sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2023 + }
2024 + }
2025 +
2026 + if (status & Y2_HWE_L1_MASK)
2027 + sky2_hw_error(hw, 0, status);
2028 + status >>= 8;
2029 + if (status & Y2_HWE_L1_MASK)
2030 + sky2_hw_error(hw, 1, status);
2031 +}
2032 +
2033 +static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2034 +{
2035 + struct net_device *dev = hw->dev[port];
2036 + struct sky2_port *sky2 = netdev_priv(dev);
2037 + u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2038 +
2039 + if (netif_msg_intr(sky2))
2040 + printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2041 + dev->name, status);
2042 +
2043 + if (status & GM_IS_RX_FF_OR) {
2044 + ++sky2->net_stats.rx_fifo_errors;
2045 + sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2046 + }
2047 +
2048 + if (status & GM_IS_TX_FF_UR) {
2049 + ++sky2->net_stats.tx_fifo_errors;
2050 + sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2051 + }
2052 +}
2053 +
2054 +static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2055 +{
2056 + struct net_device *dev = hw->dev[port];
2057 + struct sky2_port *sky2 = netdev_priv(dev);
2058 +
2059 + hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
2060 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
2061 + schedule_work(&sky2->phy_task);
2062 +}
2063 +
2064 +static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2065 +{
2066 + struct sky2_hw *hw = dev_id;
2067 + struct net_device *dev0 = hw->dev[0];
2068 + u32 status;
2069 +
2070 + status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2071 + if (status == 0 || status == ~0)
2072 + return IRQ_NONE;
2073 +
2074 + if (status & Y2_IS_HW_ERR)
2075 + sky2_hw_intr(hw);
2076 +
2077 + /* Do NAPI for Rx and Tx status */
2078 + if (status & Y2_IS_STAT_BMU) {
2079 + hw->intr_mask &= ~Y2_IS_STAT_BMU;
2080 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
2081 +
2082 + if (likely(__netif_rx_schedule_prep(dev0))) {
2083 + prefetch(&hw->st_le[hw->st_idx]);
2084 + __netif_rx_schedule(dev0);
2085 + }
2086 + }
2087 +
2088 + if (status & Y2_IS_IRQ_PHY1)
2089 + sky2_phy_intr(hw, 0);
2090 +
2091 + if (status & Y2_IS_IRQ_PHY2)
2092 + sky2_phy_intr(hw, 1);
2093 +
2094 + if (status & Y2_IS_IRQ_MAC1)
2095 + sky2_mac_intr(hw, 0);
2096 +
2097 + if (status & Y2_IS_IRQ_MAC2)
2098 + sky2_mac_intr(hw, 1);
2099 +
2100 + sky2_write32(hw, B0_Y2_SP_ICR, 2);
2101 +
2102 + sky2_read32(hw, B0_IMSK);
2103 +
2104 + return IRQ_HANDLED;
2105 +}
2106 +
2107 +#ifdef CONFIG_NET_POLL_CONTROLLER
2108 +static void sky2_netpoll(struct net_device *dev)
2109 +{
2110 + struct sky2_port *sky2 = netdev_priv(dev);
2111 +
2112 + sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
2113 +}
2114 +#endif
2115 +
2116 +/* Chip internal frequency for clock calculations */
2117 +static inline u32 sky2_mhz(const struct sky2_hw *hw)
2118 +{
2119 + switch (hw->chip_id) {
2120 + case CHIP_ID_YUKON_EC:
2121 + case CHIP_ID_YUKON_EC_U:
2122 + return 125; /* 125 Mhz */
2123 + case CHIP_ID_YUKON_FE:
2124 + return 100; /* 100 Mhz */
2125 + default: /* YUKON_XL */
2126 + return 156; /* 156 Mhz */
2127 + }
2128 +}
2129 +
2130 +static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2131 +{
2132 + return sky2_mhz(hw) * us;
2133 +}
2134 +
2135 +static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2136 +{
2137 + return clk / sky2_mhz(hw);
2138 +}
2139 +
2140 +
2141 +static int sky2_reset(struct sky2_hw *hw)
2142 +{
2143 + u16 status;
2144 + u8 t8, pmd_type;
2145 + int i, err;
2146 +
2147 + sky2_write8(hw, B0_CTST, CS_RST_CLR);
2148 +
2149 + hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2150 + if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2151 + printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2152 + pci_name(hw->pdev), hw->chip_id);
2153 + return -EOPNOTSUPP;
2154 + }
2155 +
2156 + /* disable ASF */
2157 + if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2158 + sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2159 + sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2160 + }
2161 +
2162 + /* do a SW reset */
2163 + sky2_write8(hw, B0_CTST, CS_RST_SET);
2164 + sky2_write8(hw, B0_CTST, CS_RST_CLR);
2165 +
2166 + /* clear PCI errors, if any */
2167 + err = pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2168 + if (err)
2169 + goto pci_err;
2170 +
2171 + sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2172 + err = pci_write_config_word(hw->pdev, PCI_STATUS,
2173 + status | PCI_STATUS_ERROR_BITS);
2174 + if (err)
2175 + goto pci_err;
2176 +
2177 + sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2178 +
2179 + /* clear any PEX errors */
2180 + if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) {
2181 + err = pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
2182 + 0xffffffffUL);
2183 + if (err)
2184 + goto pci_err;
2185 + }
2186 +
2187 + pmd_type = sky2_read8(hw, B2_PMD_TYP);
2188 + hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2189 +
2190 + hw->ports = 1;
2191 + t8 = sky2_read8(hw, B2_Y2_HW_RES);
2192 + if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2193 + if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2194 + ++hw->ports;
2195 + }
2196 + hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2197 +
2198 + sky2_set_power_state(hw, PCI_D0);
2199 +
2200 + for (i = 0; i < hw->ports; i++) {
2201 + sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2202 + sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2203 + }
2204 +
2205 + sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2206 +
2207 + /* Clear I2C IRQ noise */
2208 + sky2_write32(hw, B2_I2C_IRQ, 1);
2209 +
2210 + /* turn off hardware timer (unused) */
2211 + sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2212 + sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2213 +
2214 + sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2215 +
2216 + /* Turn off descriptor polling */
2217 + sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2218 +
2219 + /* Turn off receive timestamp */
2220 + sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2221 + sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2222 +
2223 + /* enable the Tx Arbiters */
2224 + for (i = 0; i < hw->ports; i++)
2225 + sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2226 +
2227 + /* Initialize ram interface */
2228 + for (i = 0; i < hw->ports; i++) {
2229 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2230 +
2231 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2232 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2233 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2234 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2235 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2236 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2237 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2238 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2239 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2240 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2241 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2242 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2243 + }
2244 +
2245 + sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2246 +
2247 + for (i = 0; i < hw->ports; i++)
2248 + sky2_phy_reset(hw, i);
2249 +
2250 + memset(hw->st_le, 0, STATUS_LE_BYTES);
2251 + hw->st_idx = 0;
2252 +
2253 + sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2254 + sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2255 +
2256 + sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2257 + sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2258 +
2259 + /* Set the list last index */
2260 + sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2261 +
2262 + /* These status setup values are copied from SysKonnect's driver */
2263 + if (is_ec_a1(hw)) {
2264 + /* WA for dev. #4.3 */
2265 + sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
2266 +
2267 + /* set Status-FIFO watermark */
2268 + sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
2269 +
2270 + /* set Status-FIFO ISR watermark */
2271 + sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
2272 + sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 10000));
2273 + } else {
2274 + sky2_write16(hw, STAT_TX_IDX_TH, 10);
2275 + sky2_write8(hw, STAT_FIFO_WM, 16);
2276 +
2277 + /* set Status-FIFO ISR watermark */
2278 + if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2279 + sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2280 + else
2281 + sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2282 +
2283 + sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2284 + sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2285 + sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2286 + }
2287 +
2288 + /* enable status unit */
2289 + sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2290 +
2291 + sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2292 + sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2293 + sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2294 +
2295 + return 0;
2296 +
2297 +pci_err:
2298 + /* This is to catch a BIOS bug workaround where
2299 + * mmconfig table doesn't have other buses.
2300 + */
2301 + printk(KERN_ERR PFX "%s: can't access PCI config space\n",
2302 + pci_name(hw->pdev));
2303 + return err;
2304 +}
2305 +
2306 +static u32 sky2_supported_modes(const struct sky2_hw *hw)
2307 +{
2308 + u32 modes;
2309 + if (hw->copper) {
2310 + modes = SUPPORTED_10baseT_Half
2311 + | SUPPORTED_10baseT_Full
2312 + | SUPPORTED_100baseT_Half
2313 + | SUPPORTED_100baseT_Full
2314 + | SUPPORTED_Autoneg | SUPPORTED_TP;
2315 +
2316 + if (hw->chip_id != CHIP_ID_YUKON_FE)
2317 + modes |= SUPPORTED_1000baseT_Half
2318 + | SUPPORTED_1000baseT_Full;
2319 + } else
2320 + modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
2321 + | SUPPORTED_Autoneg;
2322 + return modes;
2323 +}
2324 +
2325 +static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2326 +{
2327 + struct sky2_port *sky2 = netdev_priv(dev);
2328 + struct sky2_hw *hw = sky2->hw;
2329 +
2330 + ecmd->transceiver = XCVR_INTERNAL;
2331 + ecmd->supported = sky2_supported_modes(hw);
2332 + ecmd->phy_address = PHY_ADDR_MARV;
2333 + if (hw->copper) {
2334 + ecmd->supported = SUPPORTED_10baseT_Half
2335 + | SUPPORTED_10baseT_Full
2336 + | SUPPORTED_100baseT_Half
2337 + | SUPPORTED_100baseT_Full
2338 + | SUPPORTED_1000baseT_Half
2339 + | SUPPORTED_1000baseT_Full
2340 + | SUPPORTED_Autoneg | SUPPORTED_TP;
2341 + ecmd->port = PORT_TP;
2342 + } else
2343 + ecmd->port = PORT_FIBRE;
2344 +
2345 + ecmd->advertising = sky2->advertising;
2346 + ecmd->autoneg = sky2->autoneg;
2347 + ecmd->speed = sky2->speed;
2348 + ecmd->duplex = sky2->duplex;
2349 + return 0;
2350 +}
2351 +
2352 +static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2353 +{
2354 + struct sky2_port *sky2 = netdev_priv(dev);
2355 + const struct sky2_hw *hw = sky2->hw;
2356 + u32 supported = sky2_supported_modes(hw);
2357 +
2358 + if (ecmd->autoneg == AUTONEG_ENABLE) {
2359 + ecmd->advertising = supported;
2360 + sky2->duplex = -1;
2361 + sky2->speed = -1;
2362 + } else {
2363 + u32 setting;
2364 +
2365 + switch (ecmd->speed) {
2366 + case SPEED_1000:
2367 + if (ecmd->duplex == DUPLEX_FULL)
2368 + setting = SUPPORTED_1000baseT_Full;
2369 + else if (ecmd->duplex == DUPLEX_HALF)
2370 + setting = SUPPORTED_1000baseT_Half;
2371 + else
2372 + return -EINVAL;
2373 + break;
2374 + case SPEED_100:
2375 + if (ecmd->duplex == DUPLEX_FULL)
2376 + setting = SUPPORTED_100baseT_Full;
2377 + else if (ecmd->duplex == DUPLEX_HALF)
2378 + setting = SUPPORTED_100baseT_Half;
2379 + else
2380 + return -EINVAL;
2381 + break;
2382 +
2383 + case SPEED_10:
2384 + if (ecmd->duplex == DUPLEX_FULL)
2385 + setting = SUPPORTED_10baseT_Full;
2386 + else if (ecmd->duplex == DUPLEX_HALF)
2387 + setting = SUPPORTED_10baseT_Half;
2388 + else
2389 + return -EINVAL;
2390 + break;
2391 + default:
2392 + return -EINVAL;
2393 + }
2394 +
2395 + if ((setting & supported) == 0)
2396 + return -EINVAL;
2397 +
2398 + sky2->speed = ecmd->speed;
2399 + sky2->duplex = ecmd->duplex;
2400 + }
2401 +
2402 + sky2->autoneg = ecmd->autoneg;
2403 + sky2->advertising = ecmd->advertising;
2404 +
2405 + if (netif_running(dev))
2406 + sky2_phy_reinit(sky2);
2407 +
2408 + return 0;
2409 +}
2410 +
2411 +static void sky2_get_drvinfo(struct net_device *dev,
2412 + struct ethtool_drvinfo *info)
2413 +{
2414 + struct sky2_port *sky2 = netdev_priv(dev);
2415 +
2416 + strcpy(info->driver, DRV_NAME);
2417 + strcpy(info->version, DRV_VERSION);
2418 + strcpy(info->fw_version, "N/A");
2419 + strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2420 +}
2421 +
2422 +static const struct sky2_stat {
2423 + char name[ETH_GSTRING_LEN];
2424 + u16 offset;
2425 +} sky2_stats[] = {
2426 + { "tx_bytes", GM_TXO_OK_HI },
2427 + { "rx_bytes", GM_RXO_OK_HI },
2428 + { "tx_broadcast", GM_TXF_BC_OK },
2429 + { "rx_broadcast", GM_RXF_BC_OK },
2430 + { "tx_multicast", GM_TXF_MC_OK },
2431 + { "rx_multicast", GM_RXF_MC_OK },
2432 + { "tx_unicast", GM_TXF_UC_OK },
2433 + { "rx_unicast", GM_RXF_UC_OK },
2434 + { "tx_mac_pause", GM_TXF_MPAUSE },
2435 + { "rx_mac_pause", GM_RXF_MPAUSE },
2436 + { "collisions", GM_TXF_SNG_COL },
2437 + { "late_collision",GM_TXF_LAT_COL },
2438 + { "aborted", GM_TXF_ABO_COL },
2439 + { "multi_collisions", GM_TXF_MUL_COL },
2440 + { "fifo_underrun", GM_TXE_FIFO_UR },
2441 + { "fifo_overflow", GM_RXE_FIFO_OV },
2442 + { "rx_toolong", GM_RXF_LNG_ERR },
2443 + { "rx_jabber", GM_RXF_JAB_PKT },
2444 + { "rx_runt", GM_RXE_FRAG },
2445 + { "rx_too_long", GM_RXF_LNG_ERR },
2446 + { "rx_fcs_error", GM_RXF_FCS_ERR },
2447 +};
2448 +
2449 +static u32 sky2_get_rx_csum(struct net_device *dev)
2450 +{
2451 + struct sky2_port *sky2 = netdev_priv(dev);
2452 +
2453 + return sky2->rx_csum;
2454 +}
2455 +
2456 +static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2457 +{
2458 + struct sky2_port *sky2 = netdev_priv(dev);
2459 +
2460 + sky2->rx_csum = data;
2461 +
2462 + sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2463 + data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2464 +
2465 + return 0;
2466 +}
2467 +
2468 +static u32 sky2_get_msglevel(struct net_device *netdev)
2469 +{
2470 + struct sky2_port *sky2 = netdev_priv(netdev);
2471 + return sky2->msg_enable;
2472 +}
2473 +
2474 +static int sky2_nway_reset(struct net_device *dev)
2475 +{
2476 + struct sky2_port *sky2 = netdev_priv(dev);
2477 +
2478 + if (sky2->autoneg != AUTONEG_ENABLE)
2479 + return -EINVAL;
2480 +
2481 + sky2_phy_reinit(sky2);
2482 +
2483 + return 0;
2484 +}
2485 +
2486 +static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2487 +{
2488 + struct sky2_hw *hw = sky2->hw;
2489 + unsigned port = sky2->port;
2490 + int i;
2491 +
2492 + data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2493 + | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2494 + data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2495 + | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2496 +
2497 + for (i = 2; i < count; i++)
2498 + data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2499 +}
2500 +
2501 +static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2502 +{
2503 + struct sky2_port *sky2 = netdev_priv(netdev);
2504 + sky2->msg_enable = value;
2505 +}
2506 +
2507 +static int sky2_get_stats_count(struct net_device *dev)
2508 +{
2509 + return ARRAY_SIZE(sky2_stats);
2510 +}
2511 +
2512 +static void sky2_get_ethtool_stats(struct net_device *dev,
2513 + struct ethtool_stats *stats, u64 * data)
2514 +{
2515 + struct sky2_port *sky2 = netdev_priv(dev);
2516 +
2517 + sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2518 +}
2519 +
2520 +static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2521 +{
2522 + int i;
2523 +
2524 + switch (stringset) {
2525 + case ETH_SS_STATS:
2526 + for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2527 + memcpy(data + i * ETH_GSTRING_LEN,
2528 + sky2_stats[i].name, ETH_GSTRING_LEN);
2529 + break;
2530 + }
2531 +}
2532 +
2533 +/* Use hardware MIB variables for critical path statistics and
2534 + * transmit feedback not reported at interrupt.
2535 + * Other errors are accounted for in interrupt handler.
2536 + */
2537 +static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2538 +{
2539 + struct sky2_port *sky2 = netdev_priv(dev);
2540 + u64 data[13];
2541 +
2542 + sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2543 +
2544 + sky2->net_stats.tx_bytes = data[0];
2545 + sky2->net_stats.rx_bytes = data[1];
2546 + sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2547 + sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2548 + sky2->net_stats.multicast = data[5] + data[7];
2549 + sky2->net_stats.collisions = data[10];
2550 + sky2->net_stats.tx_aborted_errors = data[12];
2551 +
2552 + return &sky2->net_stats;
2553 +}
2554 +
2555 +static int sky2_set_mac_address(struct net_device *dev, void *p)
2556 +{
2557 + struct sky2_port *sky2 = netdev_priv(dev);
2558 + struct sky2_hw *hw = sky2->hw;
2559 + unsigned port = sky2->port;
2560 + const struct sockaddr *addr = p;
2561 +
2562 + if (!is_valid_ether_addr(addr->sa_data))
2563 + return -EADDRNOTAVAIL;
2564 +
2565 + memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2566 + memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
2567 + dev->dev_addr, ETH_ALEN);
2568 + memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
2569 + dev->dev_addr, ETH_ALEN);
2570 +
2571 + /* virtual address for data */
2572 + gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2573 +
2574 + /* physical address: used for pause frames */
2575 + gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2576 +
2577 + return 0;
2578 +}
2579 +
2580 +static void sky2_set_multicast(struct net_device *dev)
2581 +{
2582 + struct sky2_port *sky2 = netdev_priv(dev);
2583 + struct sky2_hw *hw = sky2->hw;
2584 + unsigned port = sky2->port;
2585 + struct dev_mc_list *list = dev->mc_list;
2586 + u16 reg;
2587 + u8 filter[8];
2588 +
2589 + memset(filter, 0, sizeof(filter));
2590 +
2591 + reg = gma_read16(hw, port, GM_RX_CTRL);
2592 + reg |= GM_RXCR_UCF_ENA;
2593 +
2594 + if (dev->flags & IFF_PROMISC) /* promiscuous */
2595 + reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2596 + else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2597 + memset(filter, 0xff, sizeof(filter));
2598 + else if (dev->mc_count == 0) /* no multicast */
2599 + reg &= ~GM_RXCR_MCF_ENA;
2600 + else {
2601 + int i;
2602 + reg |= GM_RXCR_MCF_ENA;
2603 +
2604 + for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2605 + u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2606 + filter[bit / 8] |= 1 << (bit % 8);
2607 + }
2608 + }
2609 +
2610 + gma_write16(hw, port, GM_MC_ADDR_H1,
2611 + (u16) filter[0] | ((u16) filter[1] << 8));
2612 + gma_write16(hw, port, GM_MC_ADDR_H2,
2613 + (u16) filter[2] | ((u16) filter[3] << 8));
2614 + gma_write16(hw, port, GM_MC_ADDR_H3,
2615 + (u16) filter[4] | ((u16) filter[5] << 8));
2616 + gma_write16(hw, port, GM_MC_ADDR_H4,
2617 + (u16) filter[6] | ((u16) filter[7] << 8));
2618 +
2619 + gma_write16(hw, port, GM_RX_CTRL, reg);
2620 +}
2621 +
2622 +/* Can have one global because blinking is controlled by
2623 + * ethtool and that is always under RTNL mutex
2624 + */
2625 +static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2626 +{
2627 + u16 pg;
2628 +
2629 + switch (hw->chip_id) {
2630 + case CHIP_ID_YUKON_XL:
2631 + pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2632 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2633 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2634 + on ? (PHY_M_LEDC_LOS_CTRL(1) |
2635 + PHY_M_LEDC_INIT_CTRL(7) |
2636 + PHY_M_LEDC_STA1_CTRL(7) |
2637 + PHY_M_LEDC_STA0_CTRL(7))
2638 + : 0);
2639 +
2640 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2641 + break;
2642 +
2643 + default:
2644 + gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2645 + gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2646 + on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2647 + PHY_M_LED_MO_10(MO_LED_ON) |
2648 + PHY_M_LED_MO_100(MO_LED_ON) |
2649 + PHY_M_LED_MO_1000(MO_LED_ON) |
2650 + PHY_M_LED_MO_RX(MO_LED_ON)
2651 + : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2652 + PHY_M_LED_MO_10(MO_LED_OFF) |
2653 + PHY_M_LED_MO_100(MO_LED_OFF) |
2654 + PHY_M_LED_MO_1000(MO_LED_OFF) |
2655 + PHY_M_LED_MO_RX(MO_LED_OFF));
2656 +
2657 + }
2658 +}
2659 +
2660 +/* blink LED's for finding board */
2661 +static int sky2_phys_id(struct net_device *dev, u32 data)
2662 +{
2663 + struct sky2_port *sky2 = netdev_priv(dev);
2664 + struct sky2_hw *hw = sky2->hw;
2665 + unsigned port = sky2->port;
2666 + u16 ledctrl, ledover = 0;
2667 + long ms;
2668 + int interrupted;
2669 + int onoff = 1;
2670 +
2671 + if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2672 + ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2673 + else
2674 + ms = data * 1000;
2675 +
2676 + /* save initial values */
2677 + down(&sky2->phy_sema);
2678 + if (hw->chip_id == CHIP_ID_YUKON_XL) {
2679 + u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2680 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2681 + ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2682 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2683 + } else {
2684 + ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2685 + ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2686 + }
2687 +
2688 + interrupted = 0;
2689 + while (!interrupted && ms > 0) {
2690 + sky2_led(hw, port, onoff);
2691 + onoff = !onoff;
2692 +
2693 + up(&sky2->phy_sema);
2694 + interrupted = msleep_interruptible(250);
2695 + down(&sky2->phy_sema);
2696 +
2697 + ms -= 250;
2698 + }
2699 +
2700 + /* resume regularly scheduled programming */
2701 + if (hw->chip_id == CHIP_ID_YUKON_XL) {
2702 + u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2703 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2704 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2705 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2706 + } else {
2707 + gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2708 + gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2709 + }
2710 + up(&sky2->phy_sema);
2711 +
2712 + return 0;
2713 +}
2714 +
2715 +static void sky2_get_pauseparam(struct net_device *dev,
2716 + struct ethtool_pauseparam *ecmd)
2717 +{
2718 + struct sky2_port *sky2 = netdev_priv(dev);
2719 +
2720 + ecmd->tx_pause = sky2->tx_pause;
2721 + ecmd->rx_pause = sky2->rx_pause;
2722 + ecmd->autoneg = sky2->autoneg;
2723 +}
2724 +
2725 +static int sky2_set_pauseparam(struct net_device *dev,
2726 + struct ethtool_pauseparam *ecmd)
2727 +{
2728 + struct sky2_port *sky2 = netdev_priv(dev);
2729 + int err = 0;
2730 +
2731 + sky2->autoneg = ecmd->autoneg;
2732 + sky2->tx_pause = ecmd->tx_pause != 0;
2733 + sky2->rx_pause = ecmd->rx_pause != 0;
2734 +
2735 + sky2_phy_reinit(sky2);
2736 +
2737 + return err;
2738 +}
2739 +
2740 +#ifdef CONFIG_PM
2741 +static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2742 +{
2743 + struct sky2_port *sky2 = netdev_priv(dev);
2744 +
2745 + wol->supported = WAKE_MAGIC;
2746 + wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2747 +}
2748 +
2749 +static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2750 +{
2751 + struct sky2_port *sky2 = netdev_priv(dev);
2752 + struct sky2_hw *hw = sky2->hw;
2753 +
2754 + if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2755 + return -EOPNOTSUPP;
2756 +
2757 + sky2->wol = wol->wolopts == WAKE_MAGIC;
2758 +
2759 + if (sky2->wol) {
2760 + memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2761 +
2762 + sky2_write16(hw, WOL_CTRL_STAT,
2763 + WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2764 + WOL_CTL_ENA_MAGIC_PKT_UNIT);
2765 + } else
2766 + sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2767 +
2768 + return 0;
2769 +}
2770 +#endif
2771 +
2772 +static int sky2_get_coalesce(struct net_device *dev,
2773 + struct ethtool_coalesce *ecmd)
2774 +{
2775 + struct sky2_port *sky2 = netdev_priv(dev);
2776 + struct sky2_hw *hw = sky2->hw;
2777 +
2778 + if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2779 + ecmd->tx_coalesce_usecs = 0;
2780 + else {
2781 + u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2782 + ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2783 + }
2784 + ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2785 +
2786 + if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2787 + ecmd->rx_coalesce_usecs = 0;
2788 + else {
2789 + u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2790 + ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2791 + }
2792 + ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2793 +
2794 + if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2795 + ecmd->rx_coalesce_usecs_irq = 0;
2796 + else {
2797 + u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2798 + ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2799 + }
2800 +
2801 + ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2802 +
2803 + return 0;
2804 +}
2805 +
2806 +/* Note: this affect both ports */
2807 +static int sky2_set_coalesce(struct net_device *dev,
2808 + struct ethtool_coalesce *ecmd)
2809 +{
2810 + struct sky2_port *sky2 = netdev_priv(dev);
2811 + struct sky2_hw *hw = sky2->hw;
2812 + const u32 tmin = sky2_clk2us(hw, 1);
2813 + const u32 tmax = 5000;
2814 +
2815 + if (ecmd->tx_coalesce_usecs != 0 &&
2816 + (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax))
2817 + return -EINVAL;
2818 +
2819 + if (ecmd->rx_coalesce_usecs != 0 &&
2820 + (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax))
2821 + return -EINVAL;
2822 +
2823 + if (ecmd->rx_coalesce_usecs_irq != 0 &&
2824 + (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax))
2825 + return -EINVAL;
2826 +
2827 + if (ecmd->tx_max_coalesced_frames > 0xffff)
2828 + return -EINVAL;
2829 + if (ecmd->rx_max_coalesced_frames > 0xff)
2830 + return -EINVAL;
2831 + if (ecmd->rx_max_coalesced_frames_irq > 0xff)
2832 + return -EINVAL;
2833 +
2834 + if (ecmd->tx_coalesce_usecs == 0)
2835 + sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2836 + else {
2837 + sky2_write32(hw, STAT_TX_TIMER_INI,
2838 + sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2839 + sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2840 + }
2841 + sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2842 +
2843 + if (ecmd->rx_coalesce_usecs == 0)
2844 + sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2845 + else {
2846 + sky2_write32(hw, STAT_LEV_TIMER_INI,
2847 + sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2848 + sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2849 + }
2850 + sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2851 +
2852 + if (ecmd->rx_coalesce_usecs_irq == 0)
2853 + sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2854 + else {
2855 + sky2_write32(hw, STAT_ISR_TIMER_INI,
2856 + sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2857 + sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2858 + }
2859 + sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2860 + return 0;
2861 +}
2862 +
2863 +static void sky2_get_ringparam(struct net_device *dev,
2864 + struct ethtool_ringparam *ering)
2865 +{
2866 + struct sky2_port *sky2 = netdev_priv(dev);
2867 +
2868 + ering->rx_max_pending = RX_MAX_PENDING;
2869 + ering->rx_mini_max_pending = 0;
2870 + ering->rx_jumbo_max_pending = 0;
2871 + ering->tx_max_pending = TX_RING_SIZE - 1;
2872 +
2873 + ering->rx_pending = sky2->rx_pending;
2874 + ering->rx_mini_pending = 0;
2875 + ering->rx_jumbo_pending = 0;
2876 + ering->tx_pending = sky2->tx_pending;
2877 +}
2878 +
2879 +static int sky2_set_ringparam(struct net_device *dev,
2880 + struct ethtool_ringparam *ering)
2881 +{
2882 + struct sky2_port *sky2 = netdev_priv(dev);
2883 + int err = 0;
2884 +
2885 + if (ering->rx_pending > RX_MAX_PENDING ||
2886 + ering->rx_pending < 8 ||
2887 + ering->tx_pending < MAX_SKB_TX_LE ||
2888 + ering->tx_pending > TX_RING_SIZE - 1)
2889 + return -EINVAL;
2890 +
2891 + if (netif_running(dev))
2892 + sky2_down(dev);
2893 +
2894 + sky2->rx_pending = ering->rx_pending;
2895 + sky2->tx_pending = ering->tx_pending;
2896 +
2897 + if (netif_running(dev)) {
2898 + err = sky2_up(dev);
2899 + if (err)
2900 + dev_close(dev);
2901 + else
2902 + sky2_set_multicast(dev);
2903 + }
2904 +
2905 + return err;
2906 +}
2907 +
2908 +static int sky2_get_regs_len(struct net_device *dev)
2909 +{
2910 + return 0x4000;
2911 +}
2912 +
2913 +/*
2914 + * Returns copy of control register region
2915 + * Note: access to the RAM address register set will cause timeouts.
2916 + */
2917 +static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2918 + void *p)
2919 +{
2920 + const struct sky2_port *sky2 = netdev_priv(dev);
2921 + const void __iomem *io = sky2->hw->regs;
2922 +
2923 + BUG_ON(regs->len < B3_RI_WTO_R1);
2924 + regs->version = 1;
2925 + memset(p, 0, regs->len);
2926 +
2927 + memcpy_fromio(p, io, B3_RAM_ADDR);
2928 +
2929 + memcpy_fromio(p + B3_RI_WTO_R1,
2930 + io + B3_RI_WTO_R1,
2931 + regs->len - B3_RI_WTO_R1);
2932 +}
2933 +
2934 +static struct ethtool_ops sky2_ethtool_ops = {
2935 + .get_settings = sky2_get_settings,
2936 + .set_settings = sky2_set_settings,
2937 + .get_drvinfo = sky2_get_drvinfo,
2938 + .get_msglevel = sky2_get_msglevel,
2939 + .set_msglevel = sky2_set_msglevel,
2940 + .nway_reset = sky2_nway_reset,
2941 + .get_regs_len = sky2_get_regs_len,
2942 + .get_regs = sky2_get_regs,
2943 + .get_link = ethtool_op_get_link,
2944 + .get_sg = ethtool_op_get_sg,
2945 + .set_sg = ethtool_op_set_sg,
2946 + .get_tx_csum = ethtool_op_get_tx_csum,
2947 + .set_tx_csum = ethtool_op_set_tx_csum,
2948 + .get_tso = ethtool_op_get_tso,
2949 + .set_tso = ethtool_op_set_tso,
2950 + .get_rx_csum = sky2_get_rx_csum,
2951 + .set_rx_csum = sky2_set_rx_csum,
2952 + .get_strings = sky2_get_strings,
2953 + .get_coalesce = sky2_get_coalesce,
2954 + .set_coalesce = sky2_set_coalesce,
2955 + .get_ringparam = sky2_get_ringparam,
2956 + .set_ringparam = sky2_set_ringparam,
2957 + .get_pauseparam = sky2_get_pauseparam,
2958 + .set_pauseparam = sky2_set_pauseparam,
2959 +#ifdef CONFIG_PM
2960 + .get_wol = sky2_get_wol,
2961 + .set_wol = sky2_set_wol,
2962 +#endif
2963 + .phys_id = sky2_phys_id,
2964 + .get_stats_count = sky2_get_stats_count,
2965 + .get_ethtool_stats = sky2_get_ethtool_stats,
2966 + .get_perm_addr = ethtool_op_get_perm_addr,
2967 +};
2968 +
2969 +/* Initialize network device */
2970 +static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2971 + unsigned port, int highmem)
2972 +{
2973 + struct sky2_port *sky2;
2974 + struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2975 +
2976 + if (!dev) {
2977 + printk(KERN_ERR "sky2 etherdev alloc failed");
2978 + return NULL;
2979 + }
2980 +
2981 + SET_MODULE_OWNER(dev);
2982 + SET_NETDEV_DEV(dev, &hw->pdev->dev);
2983 + dev->irq = hw->pdev->irq;
2984 + dev->open = sky2_up;
2985 + dev->stop = sky2_down;
2986 + dev->do_ioctl = sky2_ioctl;
2987 + dev->hard_start_xmit = sky2_xmit_frame;
2988 + dev->get_stats = sky2_get_stats;
2989 + dev->set_multicast_list = sky2_set_multicast;
2990 + dev->set_mac_address = sky2_set_mac_address;
2991 + dev->change_mtu = sky2_change_mtu;
2992 + SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
2993 + dev->tx_timeout = sky2_tx_timeout;
2994 + dev->watchdog_timeo = TX_WATCHDOG;
2995 + if (port == 0)
2996 + dev->poll = sky2_poll;
2997 + dev->weight = NAPI_WEIGHT;
2998 +#ifdef CONFIG_NET_POLL_CONTROLLER
2999 + dev->poll_controller = sky2_netpoll;
3000 +#endif
3001 +
3002 + sky2 = netdev_priv(dev);
3003 + sky2->netdev = dev;
3004 + sky2->hw = hw;
3005 + sky2->msg_enable = netif_msg_init(debug, default_msg);
3006 +
3007 + spin_lock_init(&sky2->tx_lock);
3008 + /* Auto speed and flow control */
3009 + sky2->autoneg = AUTONEG_ENABLE;
3010 + sky2->tx_pause = 1;
3011 + sky2->rx_pause = 1;
3012 + sky2->duplex = -1;
3013 + sky2->speed = -1;
3014 + sky2->advertising = sky2_supported_modes(hw);
3015 +
3016 + /* Receive checksum disabled for Yukon XL
3017 + * because of observed problems with incorrect
3018 + * values when multiple packets are received in one interrupt
3019 + */
3020 + sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
3021 +
3022 + INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2);
3023 + init_MUTEX(&sky2->phy_sema);
3024 + sky2->tx_pending = TX_DEF_PENDING;
3025 + sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
3026 + sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
3027 +
3028 + hw->dev[port] = dev;
3029 +
3030 + sky2->port = port;
3031 +
3032 + dev->features |= NETIF_F_LLTX;
3033 + if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3034 + dev->features |= NETIF_F_TSO;
3035 + if (highmem)
3036 + dev->features |= NETIF_F_HIGHDMA;
3037 + dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3038 +
3039 +#ifdef SKY2_VLAN_TAG_USED
3040 + dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3041 + dev->vlan_rx_register = sky2_vlan_rx_register;
3042 + dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3043 +#endif
3044 +
3045 + /* read the mac address */
3046 + memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3047 + memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3048 +
3049 + /* device is off until link detection */
3050 + netif_carrier_off(dev);
3051 + netif_stop_queue(dev);
3052 +
3053 + return dev;
3054 +}
3055 +
3056 +static void __devinit sky2_show_addr(struct net_device *dev)
3057 +{
3058 + const struct sky2_port *sky2 = netdev_priv(dev);
3059 +
3060 + if (netif_msg_probe(sky2))
3061 + printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3062 + dev->name,
3063 + dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3064 + dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3065 +}
3066 +
3067 +static int __devinit sky2_probe(struct pci_dev *pdev,
3068 + const struct pci_device_id *ent)
3069 +{
3070 + struct net_device *dev, *dev1 = NULL;
3071 + struct sky2_hw *hw;
3072 + int err, pm_cap, using_dac = 0;
3073 +
3074 + err = pci_enable_device(pdev);
3075 + if (err) {
3076 + printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3077 + pci_name(pdev));
3078 + goto err_out;
3079 + }
3080 +
3081 + err = pci_request_regions(pdev, DRV_NAME);
3082 + if (err) {
3083 + printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3084 + pci_name(pdev));
3085 + goto err_out;
3086 + }
3087 +
3088 + pci_set_master(pdev);
3089 +
3090 + /* Find power-management capability. */
3091 + pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3092 + if (pm_cap == 0) {
3093 + printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3094 + "aborting.\n");
3095 + err = -EIO;
3096 + goto err_out_free_regions;
3097 + }
3098 +
3099 + if (sizeof(dma_addr_t) > sizeof(u32) &&
3100 + !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3101 + using_dac = 1;
3102 + err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3103 + if (err < 0) {
3104 + printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3105 + "for consistent allocations\n", pci_name(pdev));
3106 + goto err_out_free_regions;
3107 + }
3108 +
3109 + } else {
3110 + err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3111 + if (err) {
3112 + printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3113 + pci_name(pdev));
3114 + goto err_out_free_regions;
3115 + }
3116 + }
3117 +
3118 +#ifdef __BIG_ENDIAN
3119 + /* byte swap descriptors in hardware */
3120 + {
3121 + u32 reg;
3122 +
3123 + pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3124 + reg |= PCI_REV_DESC;
3125 + pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3126 + }
3127 +#endif
3128 +
3129 + err = -ENOMEM;
3130 + hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3131 + if (!hw) {
3132 + printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3133 + pci_name(pdev));
3134 + goto err_out_free_regions;
3135 + }
3136 +
3137 + hw->pdev = pdev;
3138 +
3139 + hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3140 + if (!hw->regs) {
3141 + printk(KERN_ERR PFX "%s: cannot map device registers\n",
3142 + pci_name(pdev));
3143 + goto err_out_free_hw;
3144 + }
3145 + hw->pm_cap = pm_cap;
3146 +
3147 + /* ring for status responses */
3148 + hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3149 + &hw->st_dma);
3150 + if (!hw->st_le)
3151 + goto err_out_iounmap;
3152 +
3153 + err = sky2_reset(hw);
3154 + if (err)
3155 + goto err_out_iounmap;
3156 +
3157 + printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3158 + DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
3159 + yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3160 + hw->chip_id, hw->chip_rev);
3161 +
3162 + dev = sky2_init_netdev(hw, 0, using_dac);
3163 + if (!dev)
3164 + goto err_out_free_pci;
3165 +
3166 + err = register_netdev(dev);
3167 + if (err) {
3168 + printk(KERN_ERR PFX "%s: cannot register net device\n",
3169 + pci_name(pdev));
3170 + goto err_out_free_netdev;
3171 + }
3172 +
3173 + sky2_show_addr(dev);
3174 +
3175 + if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3176 + if (register_netdev(dev1) == 0)
3177 + sky2_show_addr(dev1);
3178 + else {
3179 + /* Failure to register second port need not be fatal */
3180 + printk(KERN_WARNING PFX
3181 + "register of second port failed\n");
3182 + hw->dev[1] = NULL;
3183 + free_netdev(dev1);
3184 + }
3185 + }
3186 +
3187 + err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
3188 + if (err) {
3189 + printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3190 + pci_name(pdev), pdev->irq);
3191 + goto err_out_unregister;
3192 + }
3193 +
3194 + hw->intr_mask = Y2_IS_BASE;
3195 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
3196 +
3197 + pci_set_drvdata(pdev, hw);
3198 +
3199 + return 0;
3200 +
3201 +err_out_unregister:
3202 + if (dev1) {
3203 + unregister_netdev(dev1);
3204 + free_netdev(dev1);
3205 + }
3206 + unregister_netdev(dev);
3207 +err_out_free_netdev:
3208 + free_netdev(dev);
3209 +err_out_free_pci:
3210 + sky2_write8(hw, B0_CTST, CS_RST_SET);
3211 + pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3212 +err_out_iounmap:
3213 + iounmap(hw->regs);
3214 +err_out_free_hw:
3215 + kfree(hw);
3216 +err_out_free_regions:
3217 + pci_release_regions(pdev);
3218 + pci_disable_device(pdev);
3219 +err_out:
3220 + return err;
3221 +}
3222 +
3223 +static void __devexit sky2_remove(struct pci_dev *pdev)
3224 +{
3225 + struct sky2_hw *hw = pci_get_drvdata(pdev);
3226 + struct net_device *dev0, *dev1;
3227 +
3228 + if (!hw)
3229 + return;
3230 +
3231 + dev0 = hw->dev[0];
3232 + dev1 = hw->dev[1];
3233 + if (dev1)
3234 + unregister_netdev(dev1);
3235 + unregister_netdev(dev0);
3236 +
3237 + sky2_write32(hw, B0_IMSK, 0);
3238 + sky2_set_power_state(hw, PCI_D3hot);
3239 + sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3240 + sky2_write8(hw, B0_CTST, CS_RST_SET);
3241 + sky2_read8(hw, B0_CTST);
3242 +
3243 + free_irq(pdev->irq, hw);
3244 + pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3245 + pci_release_regions(pdev);
3246 + pci_disable_device(pdev);
3247 +
3248 + if (dev1)
3249 + free_netdev(dev1);
3250 + free_netdev(dev0);
3251 + iounmap(hw->regs);
3252 + kfree(hw);
3253 +
3254 + pci_set_drvdata(pdev, NULL);
3255 +}
3256 +
3257 +#ifdef CONFIG_PM
3258 +static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3259 +{
3260 + struct sky2_hw *hw = pci_get_drvdata(pdev);
3261 + int i;
3262 +
3263 + for (i = 0; i < 2; i++) {
3264 + struct net_device *dev = hw->dev[i];
3265 +
3266 + if (dev) {
3267 + if (!netif_running(dev))
3268 + continue;
3269 +
3270 + sky2_down(dev);
3271 + netif_device_detach(dev);
3272 + }
3273 + }
3274 +
3275 + return sky2_set_power_state(hw, pci_choose_state(pdev, state));
3276 +}
3277 +
3278 +static int sky2_resume(struct pci_dev *pdev)
3279 +{
3280 + struct sky2_hw *hw = pci_get_drvdata(pdev);
3281 + int i, err;
3282 +
3283 + pci_restore_state(pdev);
3284 + pci_enable_wake(pdev, PCI_D0, 0);
3285 + err = sky2_set_power_state(hw, PCI_D0);
3286 + if (err)
3287 + goto out;
3288 +
3289 + err = sky2_reset(hw);
3290 + if (err)
3291 + goto out;
3292 +
3293 + for (i = 0; i < 2; i++) {
3294 + struct net_device *dev = hw->dev[i];
3295 + if (dev && netif_running(dev)) {
3296 + netif_device_attach(dev);
3297 + err = sky2_up(dev);
3298 + if (err) {
3299 + printk(KERN_ERR PFX "%s: could not up: %d\n",
3300 + dev->name, err);
3301 + dev_close(dev);
3302 + break;
3303 + }
3304 + }
3305 + }
3306 +out:
3307 + return err;
3308 +}
3309 +#endif
3310 +
3311 +static struct pci_driver sky2_driver = {
3312 + .name = DRV_NAME,
3313 + .id_table = sky2_id_table,
3314 + .probe = sky2_probe,
3315 + .remove = __devexit_p(sky2_remove),
3316 +#ifdef CONFIG_PM
3317 + .suspend = sky2_suspend,
3318 + .resume = sky2_resume,
3319 +#endif
3320 +};
3321 +
3322 +static int __init sky2_init_module(void)
3323 +{
3324 + return pci_register_driver(&sky2_driver);
3325 +}
3326 +
3327 +static void __exit sky2_cleanup_module(void)
3328 +{
3329 + pci_unregister_driver(&sky2_driver);
3330 +}
3331 +
3332 +module_init(sky2_init_module);
3333 +module_exit(sky2_cleanup_module);
3334 +
3335 +MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3336 +MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3337 +MODULE_LICENSE("GPL");
3338 +MODULE_VERSION(DRV_VERSION);
3339 --- linux-2.6.15/drivers/net/sky2.h 1970-01-01 01:00:00.000000000 +0100
3340 +++ linux-2.6.15-gentoo-r2/drivers/net/sky2.h 2006-01-31 11:33:50.000000000 +0000
3341 @@ -0,0 +1,1914 @@
3342 +/*
3343 + * Definitions for the new Marvell Yukon 2 driver.
3344 + */
3345 +#ifndef _SKY2_H
3346 +#define _SKY2_H
3347 +
3348 +/* PCI config registers */
3349 +#define PCI_DEV_REG1 0x40
3350 +#define PCI_DEV_REG2 0x44
3351 +#define PCI_DEV_STATUS 0x7c
3352 +#define PCI_OS_PCI_X (1<<26)
3353 +
3354 +#define PEX_LNK_STAT 0xf2
3355 +#define PEX_UNC_ERR_STAT 0x104
3356 +#define PEX_DEV_CTRL 0xe8
3357 +
3358 +/* Yukon-2 */
3359 +enum pci_dev_reg_1 {
3360 + PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
3361 + PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
3362 + PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
3363 + PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
3364 + PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
3365 + PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
3366 +};
3367 +
3368 +enum pci_dev_reg_2 {
3369 + PCI_VPD_WR_THR = 0xffL<<24, /* Bit 31..24: VPD Write Threshold */
3370 + PCI_DEV_SEL = 0x7fL<<17, /* Bit 23..17: EEPROM Device Select */
3371 + PCI_VPD_ROM_SZ = 7L<<14, /* Bit 16..14: VPD ROM Size */
3372 +
3373 + PCI_PATCH_DIR = 0xfL<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */
3374 + PCI_EXT_PATCHS = 0xfL<<4, /* Bit 7.. 4: Extended Patches 3..0 */
3375 + PCI_EN_DUMMY_RD = 1<<3, /* Enable Dummy Read */
3376 + PCI_REV_DESC = 1<<2, /* Reverse Desc. Bytes */
3377 +
3378 + PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */
3379 +};
3380 +
3381 +
3382 +#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
3383 + PCI_STATUS_SIG_SYSTEM_ERROR | \
3384 + PCI_STATUS_REC_MASTER_ABORT | \
3385 + PCI_STATUS_REC_TARGET_ABORT | \
3386 + PCI_STATUS_PARITY)
3387 +
3388 +enum pex_dev_ctrl {
3389 + PEX_DC_MAX_RRS_MSK = 7<<12, /* Bit 14..12: Max. Read Request Size */
3390 + PEX_DC_EN_NO_SNOOP = 1<<11,/* Enable No Snoop */
3391 + PEX_DC_EN_AUX_POW = 1<<10,/* Enable AUX Power */
3392 + PEX_DC_EN_PHANTOM = 1<<9, /* Enable Phantom Functions */
3393 + PEX_DC_EN_EXT_TAG = 1<<8, /* Enable Extended Tag Field */
3394 + PEX_DC_MAX_PLS_MSK = 7<<5, /* Bit 7.. 5: Max. Payload Size Mask */
3395 + PEX_DC_EN_REL_ORD = 1<<4, /* Enable Relaxed Ordering */
3396 + PEX_DC_EN_UNS_RQ_RP = 1<<3, /* Enable Unsupported Request Reporting */
3397 + PEX_DC_EN_FAT_ER_RP = 1<<2, /* Enable Fatal Error Reporting */
3398 + PEX_DC_EN_NFA_ER_RP = 1<<1, /* Enable Non-Fatal Error Reporting */
3399 + PEX_DC_EN_COR_ER_RP = 1<<0, /* Enable Correctable Error Reporting */
3400 +};
3401 +#define PEX_DC_MAX_RD_RQ_SIZE(x) (((x)<<12) & PEX_DC_MAX_RRS_MSK)
3402 +
3403 +/* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */
3404 +enum pex_err {
3405 + PEX_UNSUP_REQ = 1<<20, /* Unsupported Request Error */
3406 +
3407 + PEX_MALFOR_TLP = 1<<18, /* Malformed TLP */
3408 +
3409 + PEX_UNEXP_COMP = 1<<16, /* Unexpected Completion */
3410 +
3411 + PEX_COMP_TO = 1<<14, /* Completion Timeout */
3412 + PEX_FLOW_CTRL_P = 1<<13, /* Flow Control Protocol Error */
3413 + PEX_POIS_TLP = 1<<12, /* Poisoned TLP */
3414 +
3415 + PEX_DATA_LINK_P = 1<<4, /* Data Link Protocol Error */
3416 + PEX_FATAL_ERRORS= (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P),
3417 +};
3418 +
3419 +
3420 +enum csr_regs {
3421 + B0_RAP = 0x0000,
3422 + B0_CTST = 0x0004,
3423 + B0_Y2LED = 0x0005,
3424 + B0_POWER_CTRL = 0x0007,
3425 + B0_ISRC = 0x0008,
3426 + B0_IMSK = 0x000c,
3427 + B0_HWE_ISRC = 0x0010,
3428 + B0_HWE_IMSK = 0x0014,
3429 +
3430 + /* Special ISR registers (Yukon-2 only) */
3431 + B0_Y2_SP_ISRC2 = 0x001c,
3432 + B0_Y2_SP_ISRC3 = 0x0020,
3433 + B0_Y2_SP_EISR = 0x0024,
3434 + B0_Y2_SP_LISR = 0x0028,
3435 + B0_Y2_SP_ICR = 0x002c,
3436 +
3437 + B2_MAC_1 = 0x0100,
3438 + B2_MAC_2 = 0x0108,
3439 + B2_MAC_3 = 0x0110,
3440 + B2_CONN_TYP = 0x0118,
3441 + B2_PMD_TYP = 0x0119,
3442 + B2_MAC_CFG = 0x011a,
3443 + B2_CHIP_ID = 0x011b,
3444 + B2_E_0 = 0x011c,
3445 +
3446 + B2_Y2_CLK_GATE = 0x011d,
3447 + B2_Y2_HW_RES = 0x011e,
3448 + B2_E_3 = 0x011f,
3449 + B2_Y2_CLK_CTRL = 0x0120,
3450 +
3451 + B2_TI_INI = 0x0130,
3452 + B2_TI_VAL = 0x0134,
3453 + B2_TI_CTRL = 0x0138,
3454 + B2_TI_TEST = 0x0139,
3455 +
3456 + B2_TST_CTRL1 = 0x0158,
3457 + B2_TST_CTRL2 = 0x0159,
3458 + B2_GP_IO = 0x015c,
3459 +
3460 + B2_I2C_CTRL = 0x0160,
3461 + B2_I2C_DATA = 0x0164,
3462 + B2_I2C_IRQ = 0x0168,
3463 + B2_I2C_SW = 0x016c,
3464 +
3465 + B3_RAM_ADDR = 0x0180,
3466 + B3_RAM_DATA_LO = 0x0184,
3467 + B3_RAM_DATA_HI = 0x0188,
3468 +
3469 +/* RAM Interface Registers */
3470 +/* Yukon-2: use RAM_BUFFER() to access the RAM buffer */
3471 +/*
3472 + * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
3473 + * not usable in SW. Please notice these are NOT real timeouts, these are
3474 + * the number of qWords transferred continuously.
3475 + */
3476 +#define RAM_BUFFER(port, reg) (reg | (port <<6))
3477 +
3478 + B3_RI_WTO_R1 = 0x0190,
3479 + B3_RI_WTO_XA1 = 0x0191,
3480 + B3_RI_WTO_XS1 = 0x0192,
3481 + B3_RI_RTO_R1 = 0x0193,
3482 + B3_RI_RTO_XA1 = 0x0194,
3483 + B3_RI_RTO_XS1 = 0x0195,
3484 + B3_RI_WTO_R2 = 0x0196,
3485 + B3_RI_WTO_XA2 = 0x0197,
3486 + B3_RI_WTO_XS2 = 0x0198,
3487 + B3_RI_RTO_R2 = 0x0199,
3488 + B3_RI_RTO_XA2 = 0x019a,
3489 + B3_RI_RTO_XS2 = 0x019b,
3490 + B3_RI_TO_VAL = 0x019c,
3491 + B3_RI_CTRL = 0x01a0,
3492 + B3_RI_TEST = 0x01a2,
3493 + B3_MA_TOINI_RX1 = 0x01b0,
3494 + B3_MA_TOINI_RX2 = 0x01b1,
3495 + B3_MA_TOINI_TX1 = 0x01b2,
3496 + B3_MA_TOINI_TX2 = 0x01b3,
3497 + B3_MA_TOVAL_RX1 = 0x01b4,
3498 + B3_MA_TOVAL_RX2 = 0x01b5,
3499 + B3_MA_TOVAL_TX1 = 0x01b6,
3500 + B3_MA_TOVAL_TX2 = 0x01b7,
3501 + B3_MA_TO_CTRL = 0x01b8,
3502 + B3_MA_TO_TEST = 0x01ba,
3503 + B3_MA_RCINI_RX1 = 0x01c0,
3504 + B3_MA_RCINI_RX2 = 0x01c1,
3505 + B3_MA_RCINI_TX1 = 0x01c2,
3506 + B3_MA_RCINI_TX2 = 0x01c3,
3507 + B3_MA_RCVAL_RX1 = 0x01c4,
3508 + B3_MA_RCVAL_RX2 = 0x01c5,
3509 + B3_MA_RCVAL_TX1 = 0x01c6,
3510 + B3_MA_RCVAL_TX2 = 0x01c7,
3511 + B3_MA_RC_CTRL = 0x01c8,
3512 + B3_MA_RC_TEST = 0x01ca,
3513 + B3_PA_TOINI_RX1 = 0x01d0,
3514 + B3_PA_TOINI_RX2 = 0x01d4,
3515 + B3_PA_TOINI_TX1 = 0x01d8,
3516 + B3_PA_TOINI_TX2 = 0x01dc,
3517 + B3_PA_TOVAL_RX1 = 0x01e0,
3518 + B3_PA_TOVAL_RX2 = 0x01e4,
3519 + B3_PA_TOVAL_TX1 = 0x01e8,
3520 + B3_PA_TOVAL_TX2 = 0x01ec,
3521 + B3_PA_CTRL = 0x01f0,
3522 + B3_PA_TEST = 0x01f2,
3523 +
3524 + Y2_CFG_SPC = 0x1c00,
3525 +};
3526 +
3527 +/* B0_CTST 16 bit Control/Status register */
3528 +enum {
3529 + Y2_VMAIN_AVAIL = 1<<17,/* VMAIN available (YUKON-2 only) */
3530 + Y2_VAUX_AVAIL = 1<<16,/* VAUX available (YUKON-2 only) */
3531 + Y2_ASF_ENABLE = 1<<13,/* ASF Unit Enable (YUKON-2 only) */
3532 + Y2_ASF_DISABLE = 1<<12,/* ASF Unit Disable (YUKON-2 only) */
3533 + Y2_CLK_RUN_ENA = 1<<11,/* CLK_RUN Enable (YUKON-2 only) */
3534 + Y2_CLK_RUN_DIS = 1<<10,/* CLK_RUN Disable (YUKON-2 only) */
3535 + Y2_LED_STAT_ON = 1<<9, /* Status LED On (YUKON-2 only) */
3536 + Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */
3537 +
3538 + CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
3539 + CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
3540 + CS_STOP_DONE = 1<<5, /* Stop Master is finished */
3541 + CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
3542 + CS_MRST_CLR = 1<<3, /* Clear Master reset */
3543 + CS_MRST_SET = 1<<2, /* Set Master reset */
3544 + CS_RST_CLR = 1<<1, /* Clear Software reset */
3545 + CS_RST_SET = 1, /* Set Software reset */
3546 +};
3547 +
3548 +/* B0_LED 8 Bit LED register */
3549 +enum {
3550 +/* Bit 7.. 2: reserved */
3551 + LED_STAT_ON = 1<<1, /* Status LED on */
3552 + LED_STAT_OFF = 1, /* Status LED off */
3553 +};
3554 +
3555 +/* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
3556 +enum {
3557 + PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
3558 + PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
3559 + PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
3560 + PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
3561 + PC_VAUX_ON = 1<<3, /* Switch VAUX On */
3562 + PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
3563 + PC_VCC_ON = 1<<1, /* Switch VCC On */
3564 + PC_VCC_OFF = 1<<0, /* Switch VCC Off */
3565 +};
3566 +
3567 +/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
3568 +
3569 +/* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */
3570 +/* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */
3571 +/* B0_Y2_SP_EISR 32 bit Enter ISR Reg */
3572 +/* B0_Y2_SP_LISR 32 bit Leave ISR Reg */
3573 +enum {
3574 + Y2_IS_HW_ERR = 1<<31, /* Interrupt HW Error */
3575 + Y2_IS_STAT_BMU = 1<<30, /* Status BMU Interrupt */
3576 + Y2_IS_ASF = 1<<29, /* ASF subsystem Interrupt */
3577 +
3578 + Y2_IS_POLL_CHK = 1<<27, /* Check IRQ from polling unit */
3579 + Y2_IS_TWSI_RDY = 1<<26, /* IRQ on end of TWSI Tx */
3580 + Y2_IS_IRQ_SW = 1<<25, /* SW forced IRQ */
3581 + Y2_IS_TIMINT = 1<<24, /* IRQ from Timer */
3582 +
3583 + Y2_IS_IRQ_PHY2 = 1<<12, /* Interrupt from PHY 2 */
3584 + Y2_IS_IRQ_MAC2 = 1<<11, /* Interrupt from MAC 2 */
3585 + Y2_IS_CHK_RX2 = 1<<10, /* Descriptor error Rx 2 */
3586 + Y2_IS_CHK_TXS2 = 1<<9, /* Descriptor error TXS 2 */
3587 + Y2_IS_CHK_TXA2 = 1<<8, /* Descriptor error TXA 2 */
3588 +
3589 + Y2_IS_IRQ_PHY1 = 1<<4, /* Interrupt from PHY 1 */
3590 + Y2_IS_IRQ_MAC1 = 1<<3, /* Interrupt from MAC 1 */
3591 + Y2_IS_CHK_RX1 = 1<<2, /* Descriptor error Rx 1 */
3592 + Y2_IS_CHK_TXS1 = 1<<1, /* Descriptor error TXS 1 */
3593 + Y2_IS_CHK_TXA1 = 1<<0, /* Descriptor error TXA 1 */
3594 +
3595 + Y2_IS_BASE = Y2_IS_HW_ERR | Y2_IS_STAT_BMU |
3596 + Y2_IS_POLL_CHK | Y2_IS_TWSI_RDY |
3597 + Y2_IS_IRQ_SW | Y2_IS_TIMINT,
3598 + Y2_IS_PORT_1 = Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1 |
3599 + Y2_IS_CHK_RX1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXS1,
3600 + Y2_IS_PORT_2 = Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 |
3601 + Y2_IS_CHK_RX2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_TXS2,
3602 +};
3603 +
3604 +/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
3605 +enum {
3606 + IS_ERR_MSK = 0x00003fff,/* All Error bits */
3607 +
3608 + IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
3609 + IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
3610 + IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
3611 + IS_IRQ_STAT = 1<<10, /* IRQ status exception */
3612 + IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
3613 + IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
3614 + IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
3615 + IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
3616 + IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
3617 + IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
3618 + IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
3619 + IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
3620 + IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
3621 + IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
3622 +};
3623 +
3624 +/* Hardware error interrupt mask for Yukon 2 */
3625 +enum {
3626 + Y2_IS_TIST_OV = 1<<29,/* Time Stamp Timer overflow interrupt */
3627 + Y2_IS_SENSOR = 1<<28, /* Sensor interrupt */
3628 + Y2_IS_MST_ERR = 1<<27, /* Master error interrupt */
3629 + Y2_IS_IRQ_STAT = 1<<26, /* Status exception interrupt */
3630 + Y2_IS_PCI_EXP = 1<<25, /* PCI-Express interrupt */
3631 + Y2_IS_PCI_NEXP = 1<<24, /* PCI-Express error similar to PCI error */
3632 + /* Link 2 */
3633 + Y2_IS_PAR_RD2 = 1<<13, /* Read RAM parity error interrupt */
3634 + Y2_IS_PAR_WR2 = 1<<12, /* Write RAM parity error interrupt */
3635 + Y2_IS_PAR_MAC2 = 1<<11, /* MAC hardware fault interrupt */
3636 + Y2_IS_PAR_RX2 = 1<<10, /* Parity Error Rx Queue 2 */
3637 + Y2_IS_TCP_TXS2 = 1<<9, /* TCP length mismatch sync Tx queue IRQ */
3638 + Y2_IS_TCP_TXA2 = 1<<8, /* TCP length mismatch async Tx queue IRQ */
3639 + /* Link 1 */
3640 + Y2_IS_PAR_RD1 = 1<<5, /* Read RAM parity error interrupt */
3641 + Y2_IS_PAR_WR1 = 1<<4, /* Write RAM parity error interrupt */
3642 + Y2_IS_PAR_MAC1 = 1<<3, /* MAC hardware fault interrupt */
3643 + Y2_IS_PAR_RX1 = 1<<2, /* Parity Error Rx Queue 1 */
3644 + Y2_IS_TCP_TXS1 = 1<<1, /* TCP length mismatch sync Tx queue IRQ */
3645 + Y2_IS_TCP_TXA1 = 1<<0, /* TCP length mismatch async Tx queue IRQ */
3646 +
3647 + Y2_HWE_L1_MASK = Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |
3648 + Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1,
3649 + Y2_HWE_L2_MASK = Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |
3650 + Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2,
3651 +
3652 + Y2_HWE_ALL_MASK = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT |
3653 + Y2_IS_PCI_EXP |
3654 + Y2_HWE_L1_MASK | Y2_HWE_L2_MASK,
3655 +};
3656 +
3657 +/* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
3658 +enum {
3659 + DPT_START = 1<<1,
3660 + DPT_STOP = 1<<0,
3661 +};
3662 +
3663 +/* B2_TST_CTRL1 8 bit Test Control Register 1 */
3664 +enum {
3665 + TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
3666 + TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
3667 + TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
3668 + TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
3669 + TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
3670 + TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
3671 + TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
3672 + TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
3673 +};
3674 +
3675 +/* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
3676 +enum {
3677 + CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
3678 + /* Bit 3.. 2: reserved */
3679 + CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
3680 + CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
3681 +};
3682 +
3683 +/* B2_CHIP_ID 8 bit Chip Identification Number */
3684 +enum {
3685 + CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */
3686 + CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */
3687 + CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
3688 + CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
3689 + CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
3690 + CHIP_ID_YUKON_EC_U = 0xb4, /* Chip ID for YUKON-2 EC Ultra */
3691 + CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
3692 + CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
3693 +
3694 + CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */
3695 + CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */
3696 + CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */
3697 +};
3698 +
3699 +/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
3700 +enum {
3701 + Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactive (0 = active) */
3702 + Y2_CLK_GAT_LNK2_DIS = 1<<6, /* Disable clock gating Link 2 */
3703 + Y2_COR_CLK_LNK2_DIS = 1<<5, /* Disable Core clock Link 2 */
3704 + Y2_PCI_CLK_LNK2_DIS = 1<<4, /* Disable PCI clock Link 2 */
3705 + Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactive (0 = active) */
3706 + Y2_CLK_GAT_LNK1_DIS = 1<<2, /* Disable clock gating Link 1 */
3707 + Y2_COR_CLK_LNK1_DIS = 1<<1, /* Disable Core clock Link 1 */
3708 + Y2_PCI_CLK_LNK1_DIS = 1<<0, /* Disable PCI clock Link 1 */
3709 +};
3710 +
3711 +/* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
3712 +enum {
3713 + CFG_LED_MODE_MSK = 7<<2, /* Bit 4.. 2: LED Mode Mask */
3714 + CFG_LINK_2_AVAIL = 1<<1, /* Link 2 available */
3715 + CFG_LINK_1_AVAIL = 1<<0, /* Link 1 available */
3716 +};
3717 +#define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2)
3718 +#define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)
3719 +
3720 +
3721 +/* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */
3722 +enum {
3723 + Y2_CLK_DIV_VAL_MSK = 0xff<<16,/* Bit 23..16: Clock Divisor Value */
3724 +#define Y2_CLK_DIV_VAL(x) (((x)<<16) & Y2_CLK_DIV_VAL_MSK)
3725 + Y2_CLK_DIV_VAL2_MSK = 7<<21, /* Bit 23..21: Clock Divisor Value */
3726 + Y2_CLK_SELECT2_MSK = 0x1f<<16,/* Bit 20..16: Clock Select */
3727 +#define Y2_CLK_DIV_VAL_2(x) (((x)<<21) & Y2_CLK_DIV_VAL2_MSK)
3728 +#define Y2_CLK_SEL_VAL_2(x) (((x)<<16) & Y2_CLK_SELECT2_MSK)
3729 + Y2_CLK_DIV_ENA = 1<<1, /* Enable Core Clock Division */
3730 + Y2_CLK_DIV_DIS = 1<<0, /* Disable Core Clock Division */
3731 +};
3732 +
3733 +/* B2_TI_CTRL 8 bit Timer control */
3734 +/* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
3735 +enum {
3736 + TIM_START = 1<<2, /* Start Timer */
3737 + TIM_STOP = 1<<1, /* Stop Timer */
3738 + TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
3739 +};
3740 +
3741 +/* B2_TI_TEST 8 Bit Timer Test */
3742 +/* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
3743 +/* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
3744 +enum {
3745 + TIM_T_ON = 1<<2, /* Test mode on */
3746 + TIM_T_OFF = 1<<1, /* Test mode off */
3747 + TIM_T_STEP = 1<<0, /* Test step */
3748 +};
3749 +
3750 +/* B3_RAM_ADDR 32 bit RAM Address, to read or write */
3751 + /* Bit 31..19: reserved */
3752 +#define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
3753 +/* RAM Interface Registers */
3754 +
3755 +/* B3_RI_CTRL 16 bit RAM Interface Control Register */
3756 +enum {
3757 + RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
3758 + RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
3759 +
3760 + RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
3761 + RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
3762 +};
3763 +
3764 +#define SK_RI_TO_53 36 /* RAM interface timeout */
3765 +
3766 +
3767 +/* Port related registers FIFO, and Arbiter */
3768 +#define SK_REG(port,reg) (((port)<<7)+(reg))
3769 +
3770 +/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
3771 +/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
3772 +/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
3773 +/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
3774 +/* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
3775 +
3776 +#define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
3777 +
3778 +/* TXA_CTRL 8 bit Tx Arbiter Control Register */
3779 +enum {
3780 + TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
3781 + TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
3782 + TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
3783 + TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
3784 + TXA_START_RC = 1<<3, /* Start sync Rate Control */
3785 + TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
3786 + TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
3787 + TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
3788 +};
3789 +
3790 +/*
3791 + * Bank 4 - 5
3792 + */
3793 +/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
3794 +enum {
3795 + TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
3796 + TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
3797 + TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
3798 + TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
3799 + TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
3800 + TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
3801 + TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
3802 +};
3803 +
3804 +
3805 +enum {
3806 + B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
3807 + B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
3808 + B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
3809 + B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
3810 + B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
3811 + B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
3812 + B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
3813 + B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
3814 + B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
3815 +};
3816 +
3817 +/* Queue Register Offsets, use Q_ADDR() to access */
3818 +enum {
3819 + B8_Q_REGS = 0x0400, /* base of Queue registers */
3820 + Q_D = 0x00, /* 8*32 bit Current Descriptor */
3821 + Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */
3822 + Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */
3823 + Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
3824 + Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
3825 + Q_BC = 0x30, /* 32 bit Current Byte Counter */
3826 + Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
3827 + Q_F = 0x38, /* 32 bit Flag Register */
3828 + Q_T1 = 0x3c, /* 32 bit Test Register 1 */
3829 + Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */
3830 + Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */
3831 + Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */
3832 + Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */
3833 + Q_T2 = 0x40, /* 32 bit Test Register 2 */
3834 + Q_T3 = 0x44, /* 32 bit Test Register 3 */
3835 +
3836 +/* Yukon-2 */
3837 + Q_DONE = 0x24, /* 16 bit Done Index (Yukon-2 only) */
3838 + Q_WM = 0x40, /* 16 bit FIFO Watermark */
3839 + Q_AL = 0x42, /* 8 bit FIFO Alignment */
3840 + Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */
3841 + Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */
3842 + Q_RP = 0x48, /* 8 bit FIFO Read Pointer */
3843 + Q_RL = 0x4a, /* 8 bit FIFO Read Level */
3844 + Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */
3845 + Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */
3846 + Q_WL = 0x4e, /* 8 bit FIFO Write Level */
3847 + Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */
3848 +};
3849 +#define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
3850 +
3851 +
3852 +/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
3853 +enum {
3854 + Y2_B8_PREF_REGS = 0x0450,
3855 +
3856 + PREF_UNIT_CTRL = 0x00, /* 32 bit Control register */
3857 + PREF_UNIT_LAST_IDX = 0x04, /* 16 bit Last Index */
3858 + PREF_UNIT_ADDR_LO = 0x08, /* 32 bit List start addr, low part */
3859 + PREF_UNIT_ADDR_HI = 0x0c, /* 32 bit List start addr, high part*/
3860 + PREF_UNIT_GET_IDX = 0x10, /* 16 bit Get Index */
3861 + PREF_UNIT_PUT_IDX = 0x14, /* 16 bit Put Index */
3862 + PREF_UNIT_FIFO_WP = 0x20, /* 8 bit FIFO write pointer */
3863 + PREF_UNIT_FIFO_RP = 0x24, /* 8 bit FIFO read pointer */
3864 + PREF_UNIT_FIFO_WM = 0x28, /* 8 bit FIFO watermark */
3865 + PREF_UNIT_FIFO_LEV = 0x2c, /* 8 bit FIFO level */
3866 +
3867 + PREF_UNIT_MASK_IDX = 0x0fff,
3868 +};
3869 +#define Y2_QADDR(q,reg) (Y2_B8_PREF_REGS + (q) + (reg))
3870 +
3871 +/* RAM Buffer Register Offsets */
3872 +enum {
3873 +
3874 + RB_START = 0x00,/* 32 bit RAM Buffer Start Address */
3875 + RB_END = 0x04,/* 32 bit RAM Buffer End Address */
3876 + RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
3877 + RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
3878 + RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
3879 + RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
3880 + RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */
3881 + RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
3882 + /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
3883 + RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
3884 + RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
3885 + RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
3886 + RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
3887 + RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
3888 +};
3889 +
3890 +/* Receive and Transmit Queues */
3891 +enum {
3892 + Q_R1 = 0x0000, /* Receive Queue 1 */
3893 + Q_R2 = 0x0080, /* Receive Queue 2 */
3894 + Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
3895 + Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
3896 + Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
3897 + Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
3898 +};
3899 +
3900 +/* Different PHY Types */
3901 +enum {
3902 + PHY_ADDR_MARV = 0,
3903 +};
3904 +
3905 +#define RB_ADDR(offs, queue) (B16_RAM_REGS + (queue) + (offs))
3906 +
3907 +
3908 +enum {
3909 + LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
3910 + LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
3911 + LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
3912 + LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
3913 +
3914 + LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
3915 +
3916 +/* Receive GMAC FIFO (YUKON and Yukon-2) */
3917 +
3918 + RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
3919 + RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
3920 + RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
3921 + RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
3922 + RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
3923 + RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
3924 + RX_GMF_UP_THR = 0x0c58,/* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */
3925 + RX_GMF_LP_THR = 0x0c5a,/* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */
3926 + RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
3927 + RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
3928 +
3929 + RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
3930 +
3931 + RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
3932 +
3933 + RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
3934 +};
3935 +
3936 +
3937 +/* Q_BC 32 bit Current Byte Counter */
3938 +
3939 +/* BMU Control Status Registers */
3940 +/* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
3941 +/* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
3942 +/* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
3943 +/* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
3944 +/* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
3945 +/* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
3946 +/* Q_CSR 32 bit BMU Control/Status Register */
3947 +
3948 +/* Rx BMU Control / Status Registers (Yukon-2) */
3949 +enum {
3950 + BMU_IDLE = 1<<31, /* BMU Idle State */
3951 + BMU_RX_TCP_PKT = 1<<30, /* Rx TCP Packet (when RSS Hash enabled) */
3952 + BMU_RX_IP_PKT = 1<<29, /* Rx IP Packet (when RSS Hash enabled) */
3953 +
3954 + BMU_ENA_RX_RSS_HASH = 1<<15, /* Enable Rx RSS Hash */
3955 + BMU_DIS_RX_RSS_HASH = 1<<14, /* Disable Rx RSS Hash */
3956 + BMU_ENA_RX_CHKSUM = 1<<13, /* Enable Rx TCP/IP Checksum Check */
3957 + BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */
3958 + BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */
3959 + BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment. error (Tx) */
3960 + BMU_CLR_IRQ_CHK = 1<<10, /* Clear IRQ Check */
3961 + BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */
3962 + BMU_START = 1<<8, /* Start Rx/Tx Queue */
3963 + BMU_FIFO_OP_ON = 1<<7, /* FIFO Operational On */
3964 + BMU_FIFO_OP_OFF = 1<<6, /* FIFO Operational Off */
3965 + BMU_FIFO_ENA = 1<<5, /* Enable FIFO */
3966 + BMU_FIFO_RST = 1<<4, /* Reset FIFO */
3967 + BMU_OP_ON = 1<<3, /* BMU Operational On */
3968 + BMU_OP_OFF = 1<<2, /* BMU Operational Off */
3969 + BMU_RST_CLR = 1<<1, /* Clear BMU Reset (Enable) */
3970 + BMU_RST_SET = 1<<0, /* Set BMU Reset */
3971 +
3972 + BMU_CLR_RESET = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR,
3973 + BMU_OPER_INIT = BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START |
3974 + BMU_FIFO_ENA | BMU_OP_ON,
3975 +
3976 + BMU_WM_DEFAULT = 0x600,
3977 +};
3978 +
3979 +/* Tx BMU Control / Status Registers (Yukon-2) */
3980 + /* Bit 31: same as for Rx */
3981 +enum {
3982 + BMU_TX_IPIDINCR_ON = 1<<13, /* Enable IP ID Increment */
3983 + BMU_TX_IPIDINCR_OFF = 1<<12, /* Disable IP ID Increment */
3984 + BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment length mismatch */
3985 +};
3986 +
3987 +/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
3988 +/* PREF_UNIT_CTRL 32 bit Prefetch Control register */
3989 +enum {
3990 + PREF_UNIT_OP_ON = 1<<3, /* prefetch unit operational */
3991 + PREF_UNIT_OP_OFF = 1<<2, /* prefetch unit not operational */
3992 + PREF_UNIT_RST_CLR = 1<<1, /* Clear Prefetch Unit Reset */
3993 + PREF_UNIT_RST_SET = 1<<0, /* Set Prefetch Unit Reset */
3994 +};
3995 +
3996 +/* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
3997 +/* RB_START 32 bit RAM Buffer Start Address */
3998 +/* RB_END 32 bit RAM Buffer End Address */
3999 +/* RB_WP 32 bit RAM Buffer Write Pointer */
4000 +/* RB_RP 32 bit RAM Buffer Read Pointer */
4001 +/* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
4002 +/* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
4003 +/* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
4004 +/* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
4005 +/* RB_PC 32 bit RAM Buffer Packet Counter */
4006 +/* RB_LEV 32 bit RAM Buffer Level Register */
4007 +
4008 +#define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
4009 +/* RB_TST2 8 bit RAM Buffer Test Register 2 */
4010 +/* RB_TST1 8 bit RAM Buffer Test Register 1 */
4011 +
4012 +/* RB_CTRL 8 bit RAM Buffer Control Register */
4013 +enum {
4014 + RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
4015 + RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
4016 + RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
4017 + RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
4018 + RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
4019 + RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
4020 +};
4021 +
4022 +
4023 +/* Transmit GMAC FIFO (YUKON only) */
4024 +enum {
4025 + TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
4026 + TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
4027 + TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
4028 +
4029 + TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
4030 + TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
4031 + TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
4032 +
4033 + TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
4034 + TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
4035 + TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
4036 +};
4037 +
4038 +/* Descriptor Poll Timer Registers */
4039 +enum {
4040 + B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
4041 + B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
4042 + B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
4043 +
4044 + B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
4045 +};
4046 +
4047 +/* Time Stamp Timer Registers (YUKON only) */
4048 +enum {
4049 + GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
4050 + GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
4051 + GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
4052 +};
4053 +
4054 +/* Polling Unit Registers (Yukon-2 only) */
4055 +enum {
4056 + POLL_CTRL = 0x0e20, /* 32 bit Polling Unit Control Reg */
4057 + POLL_LAST_IDX = 0x0e24,/* 16 bit Polling Unit List Last Index */
4058 +
4059 + POLL_LIST_ADDR_LO= 0x0e28,/* 32 bit Poll. List Start Addr (low) */
4060 + POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */
4061 +};
4062 +
4063 +/* ASF Subsystem Registers (Yukon-2 only) */
4064 +enum {
4065 + B28_Y2_SMB_CONFIG = 0x0e40,/* 32 bit ASF SMBus Config Register */
4066 + B28_Y2_SMB_CSD_REG = 0x0e44,/* 32 bit ASF SMB Control/Status/Data */
4067 + B28_Y2_ASF_IRQ_V_BASE=0x0e60,/* 32 bit ASF IRQ Vector Base */
4068 +
4069 + B28_Y2_ASF_STAT_CMD= 0x0e68,/* 32 bit ASF Status and Command Reg */
4070 + B28_Y2_ASF_HOST_COM= 0x0e6c,/* 32 bit ASF Host Communication Reg */
4071 + B28_Y2_DATA_REG_1 = 0x0e70,/* 32 bit ASF/Host Data Register 1 */
4072 + B28_Y2_DATA_REG_2 = 0x0e74,/* 32 bit ASF/Host Data Register 2 */
4073 + B28_Y2_DATA_REG_3 = 0x0e78,/* 32 bit ASF/Host Data Register 3 */
4074 + B28_Y2_DATA_REG_4 = 0x0e7c,/* 32 bit ASF/Host Data Register 4 */
4075 +};
4076 +
4077 +/* Status BMU Registers (Yukon-2 only)*/
4078 +enum {
4079 + STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */
4080 + STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */
4081 +
4082 + STAT_LIST_ADDR_LO= 0x0e88,/* 32 bit Status List Start Addr (low) */
4083 + STAT_LIST_ADDR_HI= 0x0e8c,/* 32 bit Status List Start Addr (high) */
4084 + STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */
4085 + STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */
4086 + STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */
4087 + STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */
4088 + STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */
4089 + STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */
4090 +
4091 +/* FIFO Control/Status Registers (Yukon-2 only)*/
4092 + STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */
4093 + STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */
4094 + STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */
4095 + STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */
4096 + STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */
4097 + STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */
4098 + STAT_FIFO_ISR_WM= 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */
4099 +
4100 +/* Level and ISR Timer Registers (Yukon-2 only)*/
4101 + STAT_LEV_TIMER_INI= 0x0eb0,/* 32 bit Level Timer Init. Value Reg */
4102 + STAT_LEV_TIMER_CNT= 0x0eb4,/* 32 bit Level Timer Counter Reg */
4103 + STAT_LEV_TIMER_CTRL= 0x0eb8,/* 8 bit Level Timer Control Reg */
4104 + STAT_LEV_TIMER_TEST= 0x0eb9,/* 8 bit Level Timer Test Reg */
4105 + STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */
4106 + STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */
4107 + STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */
4108 + STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */
4109 + STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */
4110 + STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */
4111 + STAT_ISR_TIMER_CTRL= 0x0ed8,/* 8 bit ISR Timer Control Reg */
4112 + STAT_ISR_TIMER_TEST= 0x0ed9,/* 8 bit ISR Timer Test Reg */
4113 +};
4114 +
4115 +enum {
4116 + LINKLED_OFF = 0x01,
4117 + LINKLED_ON = 0x02,
4118 + LINKLED_LINKSYNC_OFF = 0x04,
4119 + LINKLED_LINKSYNC_ON = 0x08,
4120 + LINKLED_BLINK_OFF = 0x10,
4121 + LINKLED_BLINK_ON = 0x20,
4122 +};
4123 +
4124 +/* GMAC and GPHY Control Registers (YUKON only) */
4125 +enum {
4126 + GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
4127 + GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
4128 + GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
4129 + GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
4130 + GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
4131 +
4132 +/* Wake-up Frame Pattern Match Control Registers (YUKON only) */
4133 +
4134 + WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
4135 +
4136 + WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
4137 + WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
4138 + WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
4139 + WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
4140 + WOL_PATT_PME = 0x0f2a,/* 8 bit WOL PME Match Enable (Yukon-2) */
4141 + WOL_PATT_ASFM = 0x0f2b,/* 8 bit WOL ASF Match Enable (Yukon-2) */
4142 + WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
4143 +
4144 +/* WOL Pattern Length Registers (YUKON only) */
4145 +
4146 + WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
4147 + WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
4148 +
4149 +/* WOL Pattern Counter Registers (YUKON only) */
4150 +
4151 +
4152 + WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
4153 + WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
4154 +};
4155 +
4156 +enum {
4157 + WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
4158 + WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
4159 +};
4160 +
4161 +enum {
4162 + BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
4163 + BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
4164 +};
4165 +
4166 +/*
4167 + * Marvel-PHY Registers, indirect addressed over GMAC
4168 + */
4169 +enum {
4170 + PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
4171 + PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
4172 + PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
4173 + PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
4174 + PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
4175 + PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
4176 + PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
4177 + PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
4178 + PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
4179 + /* Marvel-specific registers */
4180 + PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
4181 + PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
4182 + PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
4183 + PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
4184 + PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
4185 + PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
4186 + PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
4187 + PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
4188 + PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
4189 + PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
4190 + PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
4191 + PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
4192 + PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
4193 + PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
4194 + PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
4195 + PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
4196 + PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
4197 + PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
4198 +
4199 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
4200 + PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
4201 + PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
4202 + PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
4203 + PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
4204 + PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
4205 +};
4206 +
4207 +enum {
4208 + PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
4209 + PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
4210 + PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
4211 + PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
4212 + PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
4213 + PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
4214 + PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
4215 + PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
4216 + PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
4217 + PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
4218 +};
4219 +
4220 +enum {
4221 + PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
4222 + PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
4223 + PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
4224 +};
4225 +
4226 +enum {
4227 + PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
4228 +
4229 + PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
4230 + PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
4231 + PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */
4232 + PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
4233 + PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
4234 + PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
4235 + PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
4236 +};
4237 +
4238 +enum {
4239 + PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
4240 + PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
4241 + PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
4242 +};
4243 +
4244 +/* different Marvell PHY Ids */
4245 +enum {
4246 + PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
4247 +
4248 + PHY_BCOM_ID1_A1 = 0x6041,
4249 + PHY_BCOM_ID1_B2 = 0x6043,
4250 + PHY_BCOM_ID1_C0 = 0x6044,
4251 + PHY_BCOM_ID1_C5 = 0x6047,
4252 +
4253 + PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
4254 + PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
4255 + PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
4256 + PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
4257 +};
4258 +
4259 +/* Advertisement register bits */
4260 +enum {
4261 + PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
4262 + PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
4263 + PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */
4264 +
4265 + PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
4266 + PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */
4267 + PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */
4268 + PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
4269 + PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
4270 + PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
4271 + PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
4272 + PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
4273 + PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
4274 + PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
4275 + PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL |
4276 + PHY_AN_100HALF | PHY_AN_100FULL,
4277 +};
4278 +
4279 +/***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
4280 +/***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
4281 +enum {
4282 + PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
4283 + PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
4284 + PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
4285 + PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
4286 + PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
4287 + PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
4288 + /* Bit 9..8: reserved */
4289 + PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
4290 +};
4291 +
4292 +/** Marvell-Specific */
4293 +enum {
4294 + PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
4295 + PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */
4296 + PHY_M_AN_RF = 1<<13, /* Remote Fault */
4297 +
4298 + PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */
4299 + PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */
4300 + PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
4301 + PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
4302 + PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
4303 + PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
4304 + PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
4305 + PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
4306 +};
4307 +
4308 +/* special defines for FIBER (88E1011S only) */
4309 +enum {
4310 + PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
4311 + PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
4312 + PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
4313 + PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
4314 +};
4315 +
4316 +/* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
4317 +enum {
4318 + PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
4319 + PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
4320 + PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
4321 + PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
4322 +};
4323 +
4324 +/***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
4325 +enum {
4326 + PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
4327 + PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
4328 + PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
4329 + PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
4330 + PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
4331 + PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
4332 +};
4333 +
4334 +/***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
4335 +enum {
4336 + PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
4337 + PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
4338 + PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
4339 + PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */
4340 + PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
4341 + PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */
4342 + PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
4343 + PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */
4344 + PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */
4345 + PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */
4346 + PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */
4347 + PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */
4348 +};
4349 +
4350 +enum {
4351 + PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */
4352 + PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
4353 +};
4354 +
4355 +#define PHY_M_PC_MDI_XMODE(x) (((x)<<5) & PHY_M_PC_MDIX_MSK)
4356 +
4357 +enum {
4358 + PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
4359 + PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */
4360 + PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
4361 +};
4362 +
4363 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
4364 +enum {
4365 + PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
4366 + PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */
4367 + PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */
4368 + PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */
4369 + PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
4370 +
4371 + PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */
4372 + PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
4373 +
4374 + PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */
4375 + PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
4376 +};
4377 +
4378 +/***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
4379 +enum {
4380 + PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
4381 + PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */
4382 + PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */
4383 + PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */
4384 + PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */
4385 + PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */
4386 + PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */
4387 + PHY_M_PS_LINK_UP = 1<<10, /* Link Up */
4388 + PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
4389 + PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */
4390 + PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */
4391 + PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */
4392 + PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */
4393 + PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */
4394 + PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */
4395 + PHY_M_PS_JABBER = 1<<0, /* Jabber */
4396 +};
4397 +
4398 +#define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
4399 +
4400 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
4401 +enum {
4402 + PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */
4403 + PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
4404 +};
4405 +
4406 +enum {
4407 + PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
4408 + PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */
4409 + PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */
4410 + PHY_M_IS_AN_PR = 1<<12, /* Page Received */
4411 + PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
4412 + PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */
4413 + PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */
4414 + PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */
4415 + PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */
4416 + PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */
4417 + PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */
4418 + PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */
4419 +
4420 + PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */
4421 + PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */
4422 + PHY_M_IS_JABBER = 1<<0, /* Jabber */
4423 +
4424 + PHY_M_DEF_MSK = PHY_M_IS_LSP_CHANGE | PHY_M_IS_LST_CHANGE
4425 + | PHY_M_IS_FIFO_ERROR,
4426 + PHY_M_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
4427 +};
4428 +
4429 +
4430 +/***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
4431 +enum {
4432 + PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
4433 + PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
4434 +
4435 + PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
4436 + PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
4437 + /* (88E1011 only) */
4438 + PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */
4439 + /* (88E1011 only) */
4440 + PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */
4441 + /* (88E1111 only) */
4442 + PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
4443 + /* !!! Errata in spec. (1 = disable) */
4444 + PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
4445 + PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */
4446 + PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
4447 + PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
4448 + PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
4449 + PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};
4450 +
4451 +#define PHY_M_EC_M_DSC(x) ((x)<<10 & PHY_M_EC_M_DSC_MSK)
4452 + /* 00=1x; 01=2x; 10=3x; 11=4x */
4453 +#define PHY_M_EC_S_DSC(x) ((x)<<8 & PHY_M_EC_S_DSC_MSK)
4454 + /* 00=dis; 01=1x; 10=2x; 11=3x */
4455 +#define PHY_M_EC_DSC_2(x) ((x)<<9 & PHY_M_EC_M_DSC_MSK2)
4456 + /* 000=1x; 001=2x; 010=3x; 011=4x */
4457 +#define PHY_M_EC_MAC_S(x) ((x)<<4 & PHY_M_EC_MAC_S_MSK)
4458 + /* 01X=0; 110=2.5; 111=25 (MHz) */
4459 +
4460 +/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
4461 +enum {
4462 + PHY_M_PC_DIS_LINK_Pa = 1<<15,/* Disable Link Pulses */
4463 + PHY_M_PC_DSC_MSK = 7<<12,/* Bit 14..12: Downshift Counter */
4464 + PHY_M_PC_DOWN_S_ENA = 1<<11,/* Downshift Enable */
4465 +};
4466 +/* !!! Errata in spec. (1 = disable) */
4467 +
4468 +#define PHY_M_PC_DSC(x) (((x)<<12) & PHY_M_PC_DSC_MSK)
4469 + /* 100=5x; 101=6x; 110=7x; 111=8x */
4470 +enum {
4471 + MAC_TX_CLK_0_MHZ = 2,
4472 + MAC_TX_CLK_2_5_MHZ = 6,
4473 + MAC_TX_CLK_25_MHZ = 7,
4474 +};
4475 +
4476 +/***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
4477 +enum {
4478 + PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */
4479 + PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
4480 + PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
4481 + PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
4482 + PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
4483 + PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
4484 + PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
4485 + /* (88E1111 only) */
4486 +};
4487 +
4488 +enum {
4489 + PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */
4490 + /* (88E1011 only) */
4491 + PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
4492 + PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
4493 + PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
4494 + PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
4495 + PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
4496 +};
4497 +
4498 +#define PHY_M_LED_PULS_DUR(x) (((x)<<12) & PHY_M_LEDC_PULS_MSK)
4499 +
4500 +/***** PHY_MARV_PHY_STAT (page 3)16 bit r/w Polarity Control Reg. *****/
4501 +enum {
4502 + PHY_M_POLC_LS1M_MSK = 0xf<<12, /* Bit 15..12: LOS,STAT1 Mix % Mask */
4503 + PHY_M_POLC_IS0M_MSK = 0xf<<8, /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
4504 + PHY_M_POLC_LOS_MSK = 0x3<<6, /* Bit 7.. 6: LOS Pol. Ctrl. Mask */
4505 + PHY_M_POLC_INIT_MSK = 0x3<<4, /* Bit 5.. 4: INIT Pol. Ctrl. Mask */
4506 + PHY_M_POLC_STA1_MSK = 0x3<<2, /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */
4507 + PHY_M_POLC_STA0_MSK = 0x3, /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */
4508 +};
4509 +
4510 +#define PHY_M_POLC_LS1_P_MIX(x) (((x)<<12) & PHY_M_POLC_LS1M_MSK)
4511 +#define PHY_M_POLC_IS0_P_MIX(x) (((x)<<8) & PHY_M_POLC_IS0M_MSK)
4512 +#define PHY_M_POLC_LOS_CTRL(x) (((x)<<6) & PHY_M_POLC_LOS_MSK)
4513 +#define PHY_M_POLC_INIT_CTRL(x) (((x)<<4) & PHY_M_POLC_INIT_MSK)
4514 +#define PHY_M_POLC_STA1_CTRL(x) (((x)<<2) & PHY_M_POLC_STA1_MSK)
4515 +#define PHY_M_POLC_STA0_CTRL(x) (((x)<<0) & PHY_M_POLC_STA0_MSK)
4516 +
4517 +enum {
4518 + PULS_NO_STR = 0,/* no pulse stretching */
4519 + PULS_21MS = 1,/* 21 ms to 42 ms */
4520 + PULS_42MS = 2,/* 42 ms to 84 ms */
4521 + PULS_84MS = 3,/* 84 ms to 170 ms */
4522 + PULS_170MS = 4,/* 170 ms to 340 ms */
4523 + PULS_340MS = 5,/* 340 ms to 670 ms */
4524 + PULS_670MS = 6,/* 670 ms to 1.3 s */
4525 + PULS_1300MS = 7,/* 1.3 s to 2.7 s */
4526 +};
4527 +
4528 +#define PHY_M_LED_BLINK_RT(x) (((x)<<8) & PHY_M_LEDC_BL_R_MSK)
4529 +
4530 +enum {
4531 + BLINK_42MS = 0,/* 42 ms */
4532 + BLINK_84MS = 1,/* 84 ms */
4533 + BLINK_170MS = 2,/* 170 ms */
4534 + BLINK_340MS = 3,/* 340 ms */
4535 + BLINK_670MS = 4,/* 670 ms */
4536 +};
4537 +
4538 +/***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
4539 +#define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */
4540 + /* Bit 13..12: reserved */
4541 +#define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */
4542 +#define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */
4543 +#define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */
4544 +#define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */
4545 +#define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */
4546 +#define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */
4547 +
4548 +enum {
4549 + MO_LED_NORM = 0,
4550 + MO_LED_BLINK = 1,
4551 + MO_LED_OFF = 2,
4552 + MO_LED_ON = 3,
4553 +};
4554 +
4555 +/***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
4556 +enum {
4557 + PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */
4558 + PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */
4559 + PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
4560 + PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */
4561 + PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */
4562 +};
4563 +
4564 +/***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
4565 +enum {
4566 + PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
4567 + PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */
4568 + PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */
4569 + PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */
4570 + PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */
4571 + PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */
4572 + PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */
4573 + /* (88E1111 only) */
4574 +
4575 + PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
4576 + PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */
4577 + PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
4578 +};
4579 +
4580 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
4581 +/***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
4582 + /* Bit 15..12: reserved (used internally) */
4583 +enum {
4584 + PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
4585 + PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
4586 + PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
4587 +};
4588 +
4589 +#define PHY_M_FELP_LED2_CTRL(x) (((x)<<8) & PHY_M_FELP_LED2_MSK)
4590 +#define PHY_M_FELP_LED1_CTRL(x) (((x)<<4) & PHY_M_FELP_LED1_MSK)
4591 +#define PHY_M_FELP_LED0_CTRL(x) (((x)<<0) & PHY_M_FELP_LED0_MSK)
4592 +
4593 +enum {
4594 + LED_PAR_CTRL_COLX = 0x00,
4595 + LED_PAR_CTRL_ERROR = 0x01,
4596 + LED_PAR_CTRL_DUPLEX = 0x02,
4597 + LED_PAR_CTRL_DP_COL = 0x03,
4598 + LED_PAR_CTRL_SPEED = 0x04,
4599 + LED_PAR_CTRL_LINK = 0x05,
4600 + LED_PAR_CTRL_TX = 0x06,
4601 + LED_PAR_CTRL_RX = 0x07,
4602 + LED_PAR_CTRL_ACT = 0x08,
4603 + LED_PAR_CTRL_LNK_RX = 0x09,
4604 + LED_PAR_CTRL_LNK_AC = 0x0a,
4605 + LED_PAR_CTRL_ACT_BL = 0x0b,
4606 + LED_PAR_CTRL_TX_BL = 0x0c,
4607 + LED_PAR_CTRL_RX_BL = 0x0d,
4608 + LED_PAR_CTRL_COL_BL = 0x0e,
4609 + LED_PAR_CTRL_INACT = 0x0f
4610 +};
4611 +
4612 +/*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
4613 +enum {
4614 + PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */
4615 + PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
4616 + PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
4617 +};
4618 +
4619 +/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
4620 +/***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
4621 +enum {
4622 + PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */
4623 + PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */
4624 + PHY_M_MAC_MD_COPPER = 5,/* Copper only */
4625 + PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */
4626 +};
4627 +#define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK)
4628 +
4629 +/***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
4630 +enum {
4631 + PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */
4632 + PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
4633 + PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */
4634 + PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
4635 +};
4636 +
4637 +#define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK)
4638 +#define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK)
4639 +#define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK)
4640 +#define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK)
4641 +
4642 +/* GMAC registers */
4643 +/* Port Registers */
4644 +enum {
4645 + GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
4646 + GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
4647 + GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
4648 + GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
4649 + GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
4650 + GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
4651 + GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
4652 +/* Source Address Registers */
4653 + GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
4654 + GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
4655 + GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
4656 + GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
4657 + GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
4658 + GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
4659 +
4660 +/* Multicast Address Hash Registers */
4661 + GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
4662 + GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
4663 + GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
4664 + GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
4665 +
4666 +/* Interrupt Source Registers */
4667 + GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
4668 + GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
4669 + GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
4670 +
4671 +/* Interrupt Mask Registers */
4672 + GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
4673 + GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
4674 + GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
4675 +
4676 +/* Serial Management Interface (SMI) Registers */
4677 + GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
4678 + GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
4679 + GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
4680 +};
4681 +
4682 +/* MIB Counters */
4683 +#define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */
4684 +#define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */
4685 +
4686 +/*
4687 + * MIB Counters base address definitions (low word) -
4688 + * use offset 4 for access to high word (32 bit r/o)
4689 + */
4690 +enum {
4691 + GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */
4692 + GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */
4693 + GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
4694 + GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
4695 + GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
4696 + /* GM_MIB_CNT_BASE + 40: reserved */
4697 + GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
4698 + GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
4699 + GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
4700 + GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */
4701 + GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
4702 + GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
4703 + GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
4704 + GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */
4705 + GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */
4706 + GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */
4707 + GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */
4708 + GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */
4709 + GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */
4710 + GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152, /* Rx Frame too Long Error */
4711 + GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160, /* Rx Jabber Packet Frame */
4712 + /* GM_MIB_CNT_BASE + 168: reserved */
4713 + GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176, /* Rx FIFO overflow Event */
4714 + /* GM_MIB_CNT_BASE + 184: reserved */
4715 + GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192, /* Unicast Frames Xmitted OK */
4716 + GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200, /* Broadcast Frames Xmitted OK */
4717 + GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208, /* Pause MAC Ctrl Frames Xmitted */
4718 + GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216, /* Multicast Frames Xmitted OK */
4719 + GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224, /* Octets Transmitted OK Low */
4720 + GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232, /* Octets Transmitted OK High */
4721 + GM_TXF_64B = GM_MIB_CNT_BASE + 240, /* 64 Byte Tx Frame */
4722 + GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */
4723 + GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */
4724 + GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */
4725 + GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */
4726 + GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */
4727 + GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */
4728 +
4729 + GM_TXF_COL = GM_MIB_CNT_BASE + 304, /* Tx Collision */
4730 + GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312, /* Tx Late Collision */
4731 + GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320, /* Tx aborted due to Exces. Col. */
4732 + GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328, /* Tx Multiple Collision */
4733 + GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336, /* Tx Single Collision */
4734 + GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344, /* Tx FIFO Underrun Event */
4735 +};
4736 +
4737 +/* GMAC Bit Definitions */
4738 +/* GM_GP_STAT 16 bit r/o General Purpose Status Register */
4739 +enum {
4740 + GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */
4741 + GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
4742 + GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
4743 + GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
4744 + GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
4745 + GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
4746 + GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occured */
4747 + GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occured */
4748 +
4749 + GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
4750 + GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
4751 + GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */
4752 + GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
4753 + GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
4754 +};
4755 +
4756 +/* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
4757 +enum {
4758 + GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
4759 + GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
4760 + GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
4761 + GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
4762 + GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
4763 + GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
4764 + GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
4765 + GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */
4766 + GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */
4767 + GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
4768 + GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
4769 + GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */
4770 + GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
4771 + GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
4772 + GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
4773 +};
4774 +
4775 +#define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
4776 +#define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
4777 +
4778 +/* GM_TX_CTRL 16 bit r/w Transmit Control Register */
4779 +enum {
4780 + GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
4781 + GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
4782 + GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
4783 + GM_TXCR_COL_THR_MSK = 1<<10, /* Bit 12..10: Collision Threshold */
4784 +};
4785 +
4786 +#define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
4787 +#define TX_COL_DEF 0x04
4788 +
4789 +/* GM_RX_CTRL 16 bit r/w Receive Control Register */
4790 +enum {
4791 + GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
4792 + GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
4793 + GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
4794 + GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
4795 +};
4796 +
4797 +/* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
4798 +enum {
4799 + GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
4800 + GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */
4801 + GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */
4802 + GM_TXPA_BO_LIM_MSK = 0x0f, /* Bit 3.. 0: Backoff Limit Mask */
4803 +
4804 + TX_JAM_LEN_DEF = 0x03,
4805 + TX_JAM_IPG_DEF = 0x0b,
4806 + TX_IPG_JAM_DEF = 0x1c,
4807 + TX_BOF_LIM_DEF = 0x04,
4808 +};
4809 +
4810 +#define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK)
4811 +#define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK)
4812 +#define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK)
4813 +#define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK)
4814 +
4815 +
4816 +/* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
4817 +enum {
4818 + GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
4819 + GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */
4820 + GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */
4821 + GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
4822 + GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
4823 +};
4824 +
4825 +#define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
4826 +#define DATA_BLIND_DEF 0x04
4827 +
4828 +#define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
4829 +#define IPG_DATA_DEF 0x1e
4830 +
4831 +/* GM_SMI_CTRL 16 bit r/w SMI Control Register */
4832 +enum {
4833 + GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */
4834 + GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */
4835 + GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
4836 + GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
4837 + GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
4838 +};
4839 +
4840 +#define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
4841 +#define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK)
4842 +
4843 +/* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
4844 +enum {
4845 + GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
4846 + GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
4847 +};
4848 +
4849 +/* Receive Frame Status Encoding */
4850 +enum {
4851 + GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */
4852 + GMR_FS_VLAN = 1<<13, /* VLAN Packet */
4853 + GMR_FS_JABBER = 1<<12, /* Jabber Packet */
4854 + GMR_FS_UN_SIZE = 1<<11, /* Undersize Packet */
4855 + GMR_FS_MC = 1<<10, /* Multicast Packet */
4856 + GMR_FS_BC = 1<<9, /* Broadcast Packet */
4857 + GMR_FS_RX_OK = 1<<8, /* Receive OK (Good Packet) */
4858 + GMR_FS_GOOD_FC = 1<<7, /* Good Flow-Control Packet */
4859 + GMR_FS_BAD_FC = 1<<6, /* Bad Flow-Control Packet */
4860 + GMR_FS_MII_ERR = 1<<5, /* MII Error */
4861 + GMR_FS_LONG_ERR = 1<<4, /* Too Long Packet */
4862 + GMR_FS_FRAGMENT = 1<<3, /* Fragment */
4863 +
4864 + GMR_FS_CRC_ERR = 1<<1, /* CRC Error */
4865 + GMR_FS_RX_FF_OV = 1<<0, /* Rx FIFO Overflow */
4866 +
4867 + GMR_FS_ANY_ERR = GMR_FS_RX_FF_OV | GMR_FS_CRC_ERR |
4868 + GMR_FS_FRAGMENT | GMR_FS_LONG_ERR |
4869 + GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
4870 + GMR_FS_UN_SIZE | GMR_FS_JABBER,
4871 +};
4872 +
4873 +/* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
4874 +enum {
4875 + RX_TRUNC_ON = 1<<27, /* enable packet truncation */
4876 + RX_TRUNC_OFF = 1<<26, /* disable packet truncation */
4877 + RX_VLAN_STRIP_ON = 1<<25, /* enable VLAN stripping */
4878 + RX_VLAN_STRIP_OFF = 1<<24, /* disable VLAN stripping */
4879 +
4880 + GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */
4881 + GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */
4882 + GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */
4883 +
4884 + GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */
4885 + GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */
4886 + GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */
4887 + GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
4888 + GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
4889 + GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
4890 + GMF_CLI_RX_C = 1<<4, /* Clear IRQ Rx Frame Complete */
4891 +
4892 + GMF_OPER_ON = 1<<3, /* Operational Mode On */
4893 + GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
4894 + GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
4895 + GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */
4896 +
4897 + RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */
4898 +
4899 + GMF_RX_CTRL_DEF = GMF_OPER_ON | GMF_RX_F_FL_ON,
4900 +};
4901 +
4902 +
4903 +/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
4904 +enum {
4905 + TX_STFW_DIS = 1<<31,/* Disable Store & Forward (Yukon-EC Ultra) */
4906 + TX_STFW_ENA = 1<<30,/* Enable Store & Forward (Yukon-EC Ultra) */
4907 +
4908 + TX_VLAN_TAG_ON = 1<<25,/* enable VLAN tagging */
4909 + TX_VLAN_TAG_OFF = 1<<24,/* disable VLAN tagging */
4910 +
4911 + GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */
4912 + GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */
4913 + GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */
4914 +
4915 + GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */
4916 + GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
4917 + GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */
4918 +};
4919 +
4920 +/* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
4921 +enum {
4922 + GMT_ST_START = 1<<2, /* Start Time Stamp Timer */
4923 + GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */
4924 + GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */
4925 +};
4926 +
4927 +/* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */
4928 +enum {
4929 + Y2_ASF_OS_PRES = 1<<4, /* ASF operation system present */
4930 + Y2_ASF_RESET = 1<<3, /* ASF system in reset state */
4931 + Y2_ASF_RUNNING = 1<<2, /* ASF system operational */
4932 + Y2_ASF_CLR_HSTI = 1<<1, /* Clear ASF IRQ */
4933 + Y2_ASF_IRQ = 1<<0, /* Issue an IRQ to ASF system */
4934 +
4935 + Y2_ASF_UC_STATE = 3<<2, /* ASF uC State */
4936 + Y2_ASF_CLK_HALT = 0, /* ASF system clock stopped */
4937 +};
4938 +
4939 +/* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */
4940 +enum {
4941 + Y2_ASF_CLR_ASFI = 1<<1, /* Clear host IRQ */
4942 + Y2_ASF_HOST_IRQ = 1<<0, /* Issue an IRQ to HOST system */
4943 +};
4944 +
4945 +/* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
4946 +enum {
4947 + SC_STAT_CLR_IRQ = 1<<4, /* Status Burst IRQ clear */
4948 + SC_STAT_OP_ON = 1<<3, /* Operational Mode On */
4949 + SC_STAT_OP_OFF = 1<<2, /* Operational Mode Off */
4950 + SC_STAT_RST_CLR = 1<<1, /* Clear Status Unit Reset (Enable) */
4951 + SC_STAT_RST_SET = 1<<0, /* Set Status Unit Reset */
4952 +};
4953 +
4954 +/* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
4955 +enum {
4956 + GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */
4957 + GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
4958 + GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */
4959 + GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */
4960 + GMC_PAUSE_ON = 1<<3, /* Pause On */
4961 + GMC_PAUSE_OFF = 1<<2, /* Pause Off */
4962 + GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */
4963 + GMC_RST_SET = 1<<0, /* Set GMAC Reset */
4964 +};
4965 +
4966 +/* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
4967 +enum {
4968 + GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
4969 + GPC_INT_POL_HI = 1<<27, /* IRQ Polarity is Active HIGH */
4970 + GPC_75_OHM = 1<<26, /* Use 75 Ohm Termination instead of 50 */
4971 + GPC_DIS_FC = 1<<25, /* Disable Automatic Fiber/Copper Detection */
4972 + GPC_DIS_SLEEP = 1<<24, /* Disable Energy Detect */
4973 + GPC_HWCFG_M_3 = 1<<23, /* HWCFG_MODE[3] */
4974 + GPC_HWCFG_M_2 = 1<<22, /* HWCFG_MODE[2] */
4975 + GPC_HWCFG_M_1 = 1<<21, /* HWCFG_MODE[1] */
4976 + GPC_HWCFG_M_0 = 1<<20, /* HWCFG_MODE[0] */
4977 + GPC_ANEG_0 = 1<<19, /* ANEG[0] */
4978 + GPC_ENA_XC = 1<<18, /* Enable MDI crossover */
4979 + GPC_DIS_125 = 1<<17, /* Disable 125 MHz clock */
4980 + GPC_ANEG_3 = 1<<16, /* ANEG[3] */
4981 + GPC_ANEG_2 = 1<<15, /* ANEG[2] */
4982 + GPC_ANEG_1 = 1<<14, /* ANEG[1] */
4983 + GPC_ENA_PAUSE = 1<<13, /* Enable Pause (SYM_OR_REM) */
4984 + GPC_PHYADDR_4 = 1<<12, /* Bit 4 of Phy Addr */
4985 + GPC_PHYADDR_3 = 1<<11, /* Bit 3 of Phy Addr */
4986 + GPC_PHYADDR_2 = 1<<10, /* Bit 2 of Phy Addr */
4987 + GPC_PHYADDR_1 = 1<<9, /* Bit 1 of Phy Addr */
4988 + GPC_PHYADDR_0 = 1<<8, /* Bit 0 of Phy Addr */
4989 + /* Bits 7..2: reserved */
4990 + GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */
4991 + GPC_RST_SET = 1<<0, /* Set GPHY Reset */
4992 +};
4993 +
4994 +/* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
4995 +/* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
4996 +enum {
4997 + GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */
4998 + GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */
4999 + GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */
5000 + GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */
5001 + GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */
5002 + GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
5003 +
5004 +#define GMAC_DEF_MSK GM_IS_TX_FF_UR
5005 +
5006 +/* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
5007 + /* Bits 15.. 2: reserved */
5008 + GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */
5009 + GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */
5010 +
5011 +
5012 +/* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
5013 + WOL_CTL_LINK_CHG_OCC = 1<<15,
5014 + WOL_CTL_MAGIC_PKT_OCC = 1<<14,
5015 + WOL_CTL_PATTERN_OCC = 1<<13,
5016 + WOL_CTL_CLEAR_RESULT = 1<<12,
5017 + WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11,
5018 + WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10,
5019 + WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9,
5020 + WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8,
5021 + WOL_CTL_ENA_PME_ON_PATTERN = 1<<7,
5022 + WOL_CTL_DIS_PME_ON_PATTERN = 1<<6,
5023 + WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5,
5024 + WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4,
5025 + WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3,
5026 + WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2,
5027 + WOL_CTL_ENA_PATTERN_UNIT = 1<<1,
5028 + WOL_CTL_DIS_PATTERN_UNIT = 1<<0,
5029 +};
5030 +
5031 +#define WOL_CTL_DEFAULT \
5032 + (WOL_CTL_DIS_PME_ON_LINK_CHG | \
5033 + WOL_CTL_DIS_PME_ON_PATTERN | \
5034 + WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
5035 + WOL_CTL_DIS_LINK_CHG_UNIT | \
5036 + WOL_CTL_DIS_PATTERN_UNIT | \
5037 + WOL_CTL_DIS_MAGIC_PKT_UNIT)
5038 +
5039 +/* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
5040 +#define WOL_CTL_PATT_ENA(x) (1 << (x))
5041 +
5042 +
5043 +/* Control flags */
5044 +enum {
5045 + UDPTCP = 1<<0,
5046 + CALSUM = 1<<1,
5047 + WR_SUM = 1<<2,
5048 + INIT_SUM= 1<<3,
5049 + LOCK_SUM= 1<<4,
5050 + INS_VLAN= 1<<5,
5051 + FRC_STAT= 1<<6,
5052 + EOP = 1<<7,
5053 +};
5054 +
5055 +enum {
5056 + HW_OWNER = 1<<7,
5057 + OP_TCPWRITE = 0x11,
5058 + OP_TCPSTART = 0x12,
5059 + OP_TCPINIT = 0x14,
5060 + OP_TCPLCK = 0x18,
5061 + OP_TCPCHKSUM = OP_TCPSTART,
5062 + OP_TCPIS = OP_TCPINIT | OP_TCPSTART,
5063 + OP_TCPLW = OP_TCPLCK | OP_TCPWRITE,
5064 + OP_TCPLSW = OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE,
5065 + OP_TCPLISW = OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE,
5066 +
5067 + OP_ADDR64 = 0x21,
5068 + OP_VLAN = 0x22,
5069 + OP_ADDR64VLAN = OP_ADDR64 | OP_VLAN,
5070 + OP_LRGLEN = 0x24,
5071 + OP_LRGLENVLAN = OP_LRGLEN | OP_VLAN,
5072 + OP_BUFFER = 0x40,
5073 + OP_PACKET = 0x41,
5074 + OP_LARGESEND = 0x43,
5075 +
5076 +/* YUKON-2 STATUS opcodes defines */
5077 + OP_RXSTAT = 0x60,
5078 + OP_RXTIMESTAMP = 0x61,
5079 + OP_RXVLAN = 0x62,
5080 + OP_RXCHKS = 0x64,
5081 + OP_RXCHKSVLAN = OP_RXCHKS | OP_RXVLAN,
5082 + OP_RXTIMEVLAN = OP_RXTIMESTAMP | OP_RXVLAN,
5083 + OP_RSS_HASH = 0x65,
5084 + OP_TXINDEXLE = 0x68,
5085 +};
5086 +
5087 +/* Yukon 2 hardware interface
5088 + * Not tested on big endian
5089 + */
5090 +struct sky2_tx_le {
5091 + union {
5092 + __le32 addr;
5093 + struct {
5094 + __le16 offset;
5095 + __le16 start;
5096 + } csum __attribute((packed));
5097 + struct {
5098 + __le16 size;
5099 + __le16 rsvd;
5100 + } tso __attribute((packed));
5101 + } tx;
5102 + __le16 length; /* also vlan tag or checksum start */
5103 + u8 ctrl;
5104 + u8 opcode;
5105 +} __attribute((packed));
5106 +
5107 +struct sky2_rx_le {
5108 + __le32 addr;
5109 + __le16 length;
5110 + u8 ctrl;
5111 + u8 opcode;
5112 +} __attribute((packed));;
5113 +
5114 +struct sky2_status_le {
5115 + __le32 status; /* also checksum */
5116 + __le16 length; /* also vlan tag */
5117 + u8 link;
5118 + u8 opcode;
5119 +} __attribute((packed));
5120 +
5121 +struct tx_ring_info {
5122 + struct sk_buff *skb;
5123 + DECLARE_PCI_UNMAP_ADDR(mapaddr);
5124 + u16 idx;
5125 +};
5126 +
5127 +struct ring_info {
5128 + struct sk_buff *skb;
5129 + dma_addr_t mapaddr;
5130 +};
5131 +
5132 +struct sky2_port {
5133 + struct sky2_hw *hw;
5134 + struct net_device *netdev;
5135 + unsigned port;
5136 + u32 msg_enable;
5137 +
5138 + spinlock_t tx_lock ____cacheline_aligned_in_smp;
5139 + struct tx_ring_info *tx_ring;
5140 + struct sky2_tx_le *tx_le;
5141 + u16 tx_cons; /* next le to check */
5142 + u16 tx_prod; /* next le to use */
5143 + u32 tx_addr64;
5144 + u16 tx_pending;
5145 + u16 tx_last_put;
5146 + u16 tx_last_mss;
5147 +
5148 + struct ring_info *rx_ring ____cacheline_aligned_in_smp;
5149 + struct sky2_rx_le *rx_le;
5150 + u32 rx_addr64;
5151 + u16 rx_next; /* next re to check */
5152 + u16 rx_put; /* next le index to use */
5153 + u16 rx_pending;
5154 + u16 rx_last_put;
5155 + u16 rx_bufsize;
5156 +#ifdef SKY2_VLAN_TAG_USED
5157 + u16 rx_tag;
5158 + struct vlan_group *vlgrp;
5159 +#endif
5160 +
5161 + dma_addr_t rx_le_map;
5162 + dma_addr_t tx_le_map;
5163 + u32 advertising; /* ADVERTISED_ bits */
5164 + u16 speed; /* SPEED_1000, SPEED_100, ... */
5165 + u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */
5166 + u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */
5167 + u8 rx_pause;
5168 + u8 tx_pause;
5169 + u8 rx_csum;
5170 + u8 wol;
5171 +
5172 + struct net_device_stats net_stats;
5173 +
5174 + struct work_struct phy_task;
5175 + struct semaphore phy_sema;
5176 +};
5177 +
5178 +struct sky2_hw {
5179 + void __iomem *regs;
5180 + struct pci_dev *pdev;
5181 + u32 intr_mask;
5182 + struct net_device *dev[2];
5183 +
5184 + int pm_cap;
5185 + u8 chip_id;
5186 + u8 chip_rev;
5187 + u8 copper;
5188 + u8 ports;
5189 +
5190 + struct sky2_status_le *st_le;
5191 + u32 st_idx;
5192 + dma_addr_t st_dma;
5193 +};
5194 +
5195 +/* Register accessor for memory mapped device */
5196 +static inline u32 sky2_read32(const struct sky2_hw *hw, unsigned reg)
5197 +{
5198 + return readl(hw->regs + reg);
5199 +}
5200 +
5201 +static inline u16 sky2_read16(const struct sky2_hw *hw, unsigned reg)
5202 +{
5203 + return readw(hw->regs + reg);
5204 +}
5205 +
5206 +static inline u8 sky2_read8(const struct sky2_hw *hw, unsigned reg)
5207 +{
5208 + return readb(hw->regs + reg);
5209 +}
5210 +
5211 +static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val)
5212 +{
5213 + writel(val, hw->regs + reg);
5214 +}
5215 +
5216 +static inline void sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val)
5217 +{
5218 + writew(val, hw->regs + reg);
5219 +}
5220 +
5221 +static inline void sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val)
5222 +{
5223 + writeb(val, hw->regs + reg);
5224 +}
5225 +
5226 +/* Yukon PHY related registers */
5227 +#define SK_GMAC_REG(port,reg) \
5228 + (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
5229 +#define GM_PHY_RETRIES 100
5230 +
5231 +static inline u16 gma_read16(const struct sky2_hw *hw, unsigned port, unsigned reg)
5232 +{
5233 + return sky2_read16(hw, SK_GMAC_REG(port,reg));
5234 +}
5235 +
5236 +static inline u32 gma_read32(struct sky2_hw *hw, unsigned port, unsigned reg)
5237 +{
5238 + unsigned base = SK_GMAC_REG(port, reg);
5239 + return (u32) sky2_read16(hw, base)
5240 + | (u32) sky2_read16(hw, base+4) << 16;
5241 +}
5242 +
5243 +static inline void gma_write16(const struct sky2_hw *hw, unsigned port, int r, u16 v)
5244 +{
5245 + sky2_write16(hw, SK_GMAC_REG(port,r), v);
5246 +}
5247 +
5248 +static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg,
5249 + const u8 *addr)
5250 +{
5251 + gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8));
5252 + gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
5253 + gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
5254 +}
5255 +#endif
5256 --- linux-2.6.15/drivers/net/Makefile 2006-01-03 03:21:10.000000000 +0000
5257 +++ linux-2.6.15-gentoo-r2/drivers/net/Makefile 2006-01-31 11:29:42.000000000 +0000
5258 @@ -59,6 +59,7 @@ spidernet-y += spider_net.o spider_net_e
5259 obj-$(CONFIG_SPIDER_NET) += spidernet.o
5260 obj-$(CONFIG_TC35815) += tc35815.o
5261 obj-$(CONFIG_SKGE) += skge.o
5262 +obj-$(CONFIG_SKY2) += sky2.o
5263 obj-$(CONFIG_SK98LIN) += sk98lin/
5264 obj-$(CONFIG_SKFP) += skfp/
5265 obj-$(CONFIG_VIA_RHINE) += via-rhine.o
5266 --- linux-2.6.15/drivers/net/Kconfig 2006-01-03 03:21:10.000000000 +0000
5267 +++ linux-2.6.15-gentoo-r2/drivers/net/Kconfig 2006-01-31 11:29:42.000000000 +0000
5268 @@ -2008,7 +2008,17 @@ config SKGE
5269
5270 It does not support the link failover and network management
5271 features that "portable" vendor supplied sk98lin driver does.
5272 -
5273 +
5274 +config SKY2
5275 + tristate "SysKonnect Yukon2 support (EXPERIMENTAL)"
5276 + depends on PCI && EXPERIMENTAL
5277 + select CRC32
5278 + ---help---
5279 + This driver support the Marvell Yukon 2 Gigabit Ethernet adapter.
5280 +
5281 + To compile this driver as a module, choose M here: the module
5282 + will be called sky2. This is recommended.
5283 +
5284 config SK98LIN
5285 tristate "Marvell Yukon Chipset / SysKonnect SK-98xx Support"
5286 depends on PCI
5287 --- linux-2.6.15/include/linux/netdevice.h 2006-01-03 03:21:10.000000000 +0000
5288 +++ linux-2.6.15-gentoo-r2/include/linux/netdevice.h 2006-01-31 11:29:42.000000000 +0000
5289 @@ -801,12 +801,16 @@ static inline u32 netif_msg_init(int deb
5290 return (1 << debug_value) - 1;
5291 }
5292
5293 -/* Schedule rx intr now? */
5294 +/* Test if receive needs to be scheduled */
5295 +static inline int __netif_rx_schedule_prep(struct net_device *dev)
5296 +{
5297 + return !test_and_set_bit(__LINK_STATE_RX_SCHED, &dev->state);
5298 +}
5299
5300 +/* Test if receive needs to be scheduled but only if up */
5301 static inline int netif_rx_schedule_prep(struct net_device *dev)
5302 {
5303 - return netif_running(dev) &&
5304 - !test_and_set_bit(__LINK_STATE_RX_SCHED, &dev->state);
5305 + return netif_running(dev) && __netif_rx_schedule_prep(dev);
5306 }
5307
5308 /* Add interface to tail of rx poll list. This assumes that _prep has

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