/[linux-patches]/genpatches-2.6/trunk/2.6.12/4100_skge-0.6.patch
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Contents of /genpatches-2.6/trunk/2.6.12/4100_skge-0.6.patch

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Revision 32 - (show annotations) (download)
Sat Jun 18 16:18:26 2005 UTC (13 years, 5 months ago) by dsd
File size: 219079 byte(s)
2.6.12-pre --> 2.6.12
1 diff -Nru a/drivers/net/Kconfig b/drivers/net/Kconfig
2 --- a/drivers/net/Kconfig 2005-03-15 23:46:53 -08:00
3 +++ b/drivers/net/Kconfig 2005-03-15 23:46:53 -08:00
4 @@ -1953,6 +1953,18 @@
5
6 If in doubt, say Y.
7
8 +config SKGE
9 + tristate "New SysKonnect GigaEthernet support (EXPERIMENTAL)"
10 + depends on PCI && EXPERIMENTAL
11 + select CRC32
12 + ---help---
13 + This driver support the Marvell Yukon or SysKonnect SK-98xx/SK-95xx
14 + and related Gigabit Ethernet adapters. It is a new smaller driver
15 + driver with better performance and more complete ethtool support.
16 +
17 + It does not support the link failover and network management
18 + features that "portable" vendor supplied sk98lin driver does.
19 +
20 config SK98LIN
21 tristate "Marvell Yukon Chipset / SysKonnect SK-98xx Support"
22 depends on PCI
23 diff -Nru a/drivers/net/Makefile b/drivers/net/Makefile
24 --- a/drivers/net/Makefile 2005-03-15 23:46:53 -08:00
25 +++ b/drivers/net/Makefile 2005-03-15 23:46:53 -08:00
26 @@ -52,6 +52,7 @@
27 obj-$(CONFIG_FEALNX) += fealnx.o
28 obj-$(CONFIG_TIGON3) += tg3.o
29 obj-$(CONFIG_TC35815) += tc35815.o
30 +obj-$(CONFIG_SKGE) += skge.o
31 obj-$(CONFIG_SK98LIN) += sk98lin/
32 obj-$(CONFIG_SKFP) += skfp/
33 obj-$(CONFIG_VIA_RHINE) += via-rhine.o
34 diff -Nru a/drivers/net/skge.c b/drivers/net/skge.c
35 --- /dev/null Wed Dec 31 16:00:00 196900
36 +++ b/drivers/net/skge.c 2005-03-15 23:46:53 -08:00
37 @@ -0,0 +1,3385 @@
38 +/*
39 + * New driver for Marvell Yukon chipset and SysKonnect Gigabit
40 + * Ethernet adapters. Based on earlier sk98lin, e100 and
41 + * FreeBSD if_sk drivers.
42 + *
43 + * This driver intentionally does not support all the features
44 + * of the original driver such as link fail-over and link management because
45 + * those should be done at higher levels.
46 + *
47 + * Copyright (C) 2004, Stephen Hemminger <shemminger@osdl.org>
48 + *
49 + * This program is free software; you can redistribute it and/or modify
50 + * it under the terms of the GNU General Public License as published by
51 + * the Free Software Foundation; either version 2 of the License, or
52 + * (at your option) any later version.
53 + *
54 + * This program is distributed in the hope that it will be useful,
55 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
56 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
57 + * GNU General Public License for more details.
58 + *
59 + * You should have received a copy of the GNU General Public License
60 + * along with this program; if not, write to the Free Software
61 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
62 + */
63 +
64 +#include <linux/config.h>
65 +#include <linux/kernel.h>
66 +#include <linux/module.h>
67 +#include <linux/moduleparam.h>
68 +#include <linux/netdevice.h>
69 +#include <linux/etherdevice.h>
70 +#include <linux/ethtool.h>
71 +#include <linux/pci.h>
72 +#include <linux/if_vlan.h>
73 +#include <linux/ip.h>
74 +#include <linux/delay.h>
75 +#include <linux/crc32.h>
76 +#include <asm/irq.h>
77 +
78 +#include "skge.h"
79 +
80 +#define DRV_NAME "skge"
81 +#define DRV_VERSION "0.6"
82 +#define PFX DRV_NAME " "
83 +
84 +#define DEFAULT_TX_RING_SIZE 128
85 +#define DEFAULT_RX_RING_SIZE 512
86 +#define MAX_TX_RING_SIZE 1024
87 +#define MAX_RX_RING_SIZE 4096
88 +#define PHY_RETRIES 1000
89 +#define ETH_JUMBO_MTU 9000
90 +#define TX_WATCHDOG (5 * HZ)
91 +#define NAPI_WEIGHT 64
92 +#define BLINK_HZ (HZ/4)
93 +#define LINK_POLL_HZ (HZ/10)
94 +
95 +MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
96 +MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
97 +MODULE_LICENSE("GPL");
98 +MODULE_VERSION(DRV_VERSION);
99 +
100 +static const u32 default_msg
101 + = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
102 + | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
103 +
104 +static int debug = -1; /* defaults above */
105 +module_param(debug, int, 0);
106 +MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
107 +
108 +static const struct pci_device_id skge_id_table[] = {
109 + { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940,
110 + PCI_ANY_ID, PCI_ANY_ID },
111 + { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B,
112 + PCI_ANY_ID, PCI_ANY_ID },
113 + { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE,
114 + PCI_ANY_ID, PCI_ANY_ID },
115 + { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU,
116 + PCI_ANY_ID, PCI_ANY_ID },
117 + { PCI_VENDOR_ID_SYSKONNECT, 0x9E00, /* SK-9Exx */
118 + PCI_ANY_ID, PCI_ANY_ID },
119 + { PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T,
120 + PCI_ANY_ID, PCI_ANY_ID },
121 + { PCI_VENDOR_ID_MARVELL, 0x4320, /* Gigabit Ethernet Controller */
122 + PCI_ANY_ID, PCI_ANY_ID },
123 + { PCI_VENDOR_ID_MARVELL, 0x5005, /* Marvell (11ab), Belkin */
124 + PCI_ANY_ID, PCI_ANY_ID },
125 + { PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD,
126 + PCI_ANY_ID, PCI_ANY_ID },
127 + { PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1032,
128 + PCI_ANY_ID, PCI_ANY_ID },
129 + { PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064,
130 + PCI_ANY_ID, PCI_ANY_ID },
131 + { 0 }
132 +};
133 +MODULE_DEVICE_TABLE(pci, skge_id_table);
134 +
135 +static int skge_up(struct net_device *dev);
136 +static int skge_down(struct net_device *dev);
137 +static void skge_tx_clean(struct skge_port *skge);
138 +static void skge_xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
139 +static void skge_gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
140 +static void genesis_get_stats(struct skge_port *skge, u64 *data);
141 +static void yukon_get_stats(struct skge_port *skge, u64 *data);
142 +static void yukon_init(struct skge_hw *hw, int port);
143 +static void yukon_reset(struct skge_hw *hw, int port);
144 +static void genesis_mac_init(struct skge_hw *hw, int port);
145 +static void genesis_reset(struct skge_hw *hw, int port);
146 +
147 +static const int txqaddr[] = { Q_XA1, Q_XA2 };
148 +static const int rxqaddr[] = { Q_R1, Q_R2 };
149 +static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
150 +static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
151 +
152 +/* Don't need to look at whole 16K.
153 + * last interesting register is descriptor poll timer.
154 + */
155 +#define SKGE_REGS_LEN (29*128)
156 +
157 +static int skge_get_regs_len(struct net_device *dev)
158 +{
159 + return SKGE_REGS_LEN;
160 +}
161 +
162 +/*
163 + * Returns copy of control register region
164 + * I/O region is divided into banks and certain regions are unreadable
165 + */
166 +static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
167 + void *p)
168 +{
169 + const struct skge_port *skge = netdev_priv(dev);
170 + unsigned long offs;
171 + const void __iomem *io = skge->hw->regs;
172 + static const unsigned long bankmap
173 + = (1<<0) | (1<<2) | (1<<8) | (1<<9)
174 + | (1<<12) | (1<<13) | (1<<14) | (1<<15) | (1<<16)
175 + | (1<<17) | (1<<20) | (1<<21) | (1<<22) | (1<<23)
176 + | (1<<24) | (1<<25) | (1<<26) | (1<<27) | (1<<28);
177 +
178 + regs->version = 1;
179 + for (offs = 0; offs < regs->len; offs += 128) {
180 + u32 len = min_t(u32, 128, regs->len - offs);
181 +
182 + if (bankmap & (1<<(offs/128)))
183 + memcpy_fromio(p + offs, io + offs, len);
184 + else
185 + memset(p + offs, 0, len);
186 + }
187 +}
188 +
189 +/* Wake on Lan only supported on Yukon chps with rev 1 or above */
190 +static int wol_supported(const struct skge_hw *hw)
191 +{
192 + return !((hw->chip_id == CHIP_ID_GENESIS ||
193 + (hw->chip_id == CHIP_ID_YUKON && chip_rev(hw) == 0)));
194 +}
195 +
196 +static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
197 +{
198 + struct skge_port *skge = netdev_priv(dev);
199 +
200 + wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
201 + wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
202 +}
203 +
204 +static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
205 +{
206 + struct skge_port *skge = netdev_priv(dev);
207 + struct skge_hw *hw = skge->hw;
208 +
209 + if(wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
210 + return -EOPNOTSUPP;
211 +
212 + if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
213 + return -EOPNOTSUPP;
214 +
215 + skge->wol = wol->wolopts == WAKE_MAGIC;
216 +
217 + if (skge->wol) {
218 + memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
219 +
220 + skge_write16(hw, WOL_CTRL_STAT,
221 + WOL_CTL_ENA_PME_ON_MAGIC_PKT |
222 + WOL_CTL_ENA_MAGIC_PKT_UNIT);
223 + } else
224 + skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
225 +
226 + return 0;
227 +}
228 +
229 +
230 +static int skge_get_settings(struct net_device *dev,
231 + struct ethtool_cmd *ecmd)
232 +{
233 + struct skge_port *skge = netdev_priv(dev);
234 + struct skge_hw *hw = skge->hw;
235 +
236 + ecmd->transceiver = XCVR_INTERNAL;
237 +
238 + if (iscopper(hw)) {
239 + if (hw->chip_id == CHIP_ID_GENESIS)
240 + ecmd->supported = SUPPORTED_1000baseT_Full
241 + | SUPPORTED_1000baseT_Half
242 + | SUPPORTED_Autoneg | SUPPORTED_TP;
243 + else {
244 + ecmd->supported = SUPPORTED_10baseT_Half
245 + | SUPPORTED_10baseT_Full
246 + | SUPPORTED_100baseT_Half
247 + | SUPPORTED_100baseT_Full
248 + | SUPPORTED_1000baseT_Half
249 + | SUPPORTED_1000baseT_Full
250 + | SUPPORTED_Autoneg| SUPPORTED_TP;
251 +
252 + if (hw->chip_id == CHIP_ID_YUKON)
253 + ecmd->supported &= ~SUPPORTED_1000baseT_Half;
254 +
255 + else if (hw->chip_id == CHIP_ID_YUKON_FE)
256 + ecmd->supported &= ~(SUPPORTED_1000baseT_Half
257 + | SUPPORTED_1000baseT_Full);
258 + }
259 +
260 + ecmd->port = PORT_TP;
261 + ecmd->phy_address = hw->phy_addr;
262 + } else {
263 + ecmd->supported = SUPPORTED_1000baseT_Full
264 + | SUPPORTED_FIBRE
265 + | SUPPORTED_Autoneg;
266 +
267 + ecmd->port = PORT_FIBRE;
268 + }
269 +
270 + ecmd->advertising = skge->advertising;
271 + ecmd->autoneg = skge->autoneg;
272 + ecmd->speed = skge->speed;
273 + ecmd->duplex = skge->duplex;
274 + return 0;
275 +}
276 +
277 +static u32 skge_modes(const struct skge_hw *hw)
278 +{
279 + u32 modes = ADVERTISED_Autoneg
280 + | ADVERTISED_1000baseT_Full | ADVERTISED_1000baseT_Half
281 + | ADVERTISED_100baseT_Full | ADVERTISED_100baseT_Half
282 + | ADVERTISED_10baseT_Full | ADVERTISED_10baseT_Half;
283 +
284 + if (iscopper(hw)) {
285 + modes |= ADVERTISED_TP;
286 + switch(hw->chip_id) {
287 + case CHIP_ID_GENESIS:
288 + modes &= ~(ADVERTISED_100baseT_Full
289 + | ADVERTISED_100baseT_Half
290 + | ADVERTISED_10baseT_Full
291 + | ADVERTISED_10baseT_Half);
292 + break;
293 +
294 + case CHIP_ID_YUKON:
295 + modes &= ~ADVERTISED_1000baseT_Half;
296 + break;
297 +
298 + case CHIP_ID_YUKON_FE:
299 + modes &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
300 + break;
301 + }
302 + } else {
303 + modes |= ADVERTISED_FIBRE;
304 + modes &= ~ADVERTISED_1000baseT_Half;
305 + }
306 + return modes;
307 +}
308 +
309 +static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
310 +{
311 + struct skge_port *skge = netdev_priv(dev);
312 + const struct skge_hw *hw = skge->hw;
313 +
314 + if (ecmd->autoneg == AUTONEG_ENABLE) {
315 + if (ecmd->advertising & skge_modes(hw))
316 + return -EINVAL;
317 + } else {
318 + switch(ecmd->speed) {
319 + case SPEED_1000:
320 + if (hw->chip_id == CHIP_ID_YUKON_FE)
321 + return -EINVAL;
322 + break;
323 + case SPEED_100:
324 + case SPEED_10:
325 + if (iscopper(hw) || hw->chip_id == CHIP_ID_GENESIS)
326 + return -EINVAL;
327 + break;
328 + default:
329 + return -EINVAL;
330 + }
331 + }
332 +
333 + skge->autoneg = ecmd->autoneg;
334 + skge->speed = ecmd->speed;
335 + skge->duplex = ecmd->duplex;
336 + skge->advertising = ecmd->advertising;
337 +
338 + if (netif_running(dev)) {
339 + skge_down(dev);
340 + skge_up(dev);
341 + }
342 + return (0);
343 +}
344 +
345 +static void skge_get_drvinfo(struct net_device *dev,
346 + struct ethtool_drvinfo *info)
347 +{
348 + struct skge_port *skge = netdev_priv(dev);
349 +
350 + strcpy(info->driver, DRV_NAME);
351 + strcpy(info->version, DRV_VERSION);
352 + strcpy(info->fw_version, "N/A");
353 + strcpy(info->bus_info, pci_name(skge->hw->pdev));
354 +}
355 +
356 +static const struct skge_stat {
357 + char name[ETH_GSTRING_LEN];
358 + u16 xmac_offset;
359 + u16 gma_offset;
360 +} skge_stats[] = {
361 + { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
362 + { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
363 +
364 + { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
365 + { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
366 + { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
367 + { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
368 + { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
369 + { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
370 + { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
371 + { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
372 +
373 + { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
374 + { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
375 + { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
376 + { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
377 + { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
378 + { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
379 +
380 + { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
381 + { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
382 + { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
383 + { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
384 + { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
385 +};
386 +
387 +static int skge_get_stats_count(struct net_device *dev)
388 +{
389 + return ARRAY_SIZE(skge_stats);
390 +}
391 +
392 +static void skge_get_ethtool_stats(struct net_device *dev,
393 + struct ethtool_stats *stats, u64 *data)
394 +{
395 + struct skge_port *skge = netdev_priv(dev);
396 +
397 + if (skge->hw->chip_id == CHIP_ID_GENESIS)
398 + genesis_get_stats(skge, data);
399 + else
400 + yukon_get_stats(skge, data);
401 +}
402 +
403 +/* Use hardware MIB variables for critical path statistics and
404 + * transmit feedback not reported at interrupt.
405 + * Other errors are accounted for in interrupt handler.
406 + */
407 +static struct net_device_stats *skge_get_stats(struct net_device *dev)
408 +{
409 + struct skge_port *skge = netdev_priv(dev);
410 + u64 data[ARRAY_SIZE(skge_stats)];
411 +
412 + if (skge->hw->chip_id == CHIP_ID_GENESIS)
413 + genesis_get_stats(skge, data);
414 + else
415 + yukon_get_stats(skge, data);
416 +
417 + skge->net_stats.tx_bytes = data[0];
418 + skge->net_stats.rx_bytes = data[1];
419 + skge->net_stats.tx_packets = data[2] + data[4] + data[6];
420 + skge->net_stats.rx_packets = data[3] + data[5] + data[7];
421 + skge->net_stats.multicast = data[5] + data[7];
422 + skge->net_stats.collisions = data[10];
423 + skge->net_stats.tx_aborted_errors = data[12];
424 +
425 + return &skge->net_stats;
426 +}
427 +
428 +static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
429 +{
430 + int i;
431 +
432 + switch(stringset) {
433 + case ETH_SS_STATS:
434 + for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
435 + memcpy(data + i * ETH_GSTRING_LEN,
436 + skge_stats[i].name, ETH_GSTRING_LEN);
437 + break;
438 + }
439 +}
440 +
441 +static void skge_get_ring_param(struct net_device *dev,
442 + struct ethtool_ringparam *p)
443 +{
444 + struct skge_port *skge = netdev_priv(dev);
445 +
446 + p->rx_max_pending = MAX_RX_RING_SIZE;
447 + p->tx_max_pending = MAX_TX_RING_SIZE;
448 + p->rx_mini_max_pending = 0;
449 + p->rx_jumbo_max_pending = 0;
450 +
451 + p->rx_pending = skge->rx_ring.count;
452 + p->tx_pending = skge->tx_ring.count;
453 + p->rx_mini_pending = 0;
454 + p->rx_jumbo_pending = 0;
455 +}
456 +
457 +static int skge_set_ring_param(struct net_device *dev,
458 + struct ethtool_ringparam *p)
459 +{
460 + struct skge_port *skge = netdev_priv(dev);
461 +
462 + if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
463 + p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
464 + return -EINVAL;
465 +
466 + skge->rx_ring.count = p->rx_pending;
467 + skge->tx_ring.count = p->tx_pending;
468 +
469 + if (netif_running(dev)) {
470 + skge_down(dev);
471 + skge_up(dev);
472 + }
473 +
474 + return 0;
475 +}
476 +
477 +static u32 skge_get_msglevel(struct net_device *netdev)
478 +{
479 + struct skge_port *skge = netdev_priv(netdev);
480 + return skge->msg_enable;
481 +}
482 +
483 +static void skge_set_msglevel(struct net_device *netdev, u32 value)
484 +{
485 + struct skge_port *skge = netdev_priv(netdev);
486 + skge->msg_enable = value;
487 +}
488 +
489 +static int skge_nway_reset(struct net_device *dev)
490 +{
491 + struct skge_port *skge = netdev_priv(dev);
492 + struct skge_hw *hw = skge->hw;
493 + int port = skge->port;
494 +
495 + if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
496 + return -EINVAL;
497 +
498 + spin_lock_bh(&hw->phy_lock);
499 + if (hw->chip_id == CHIP_ID_GENESIS) {
500 + genesis_reset(hw, port);
501 + genesis_mac_init(hw, port);
502 + } else {
503 + yukon_reset(hw, port);
504 + yukon_init(hw, port);
505 + }
506 + spin_unlock_bh(&hw->phy_lock);
507 + return 0;
508 +}
509 +
510 +static int skge_set_sg(struct net_device *dev, u32 data)
511 +{
512 + struct skge_port *skge = netdev_priv(dev);
513 + struct skge_hw *hw = skge->hw;
514 +
515 + if (hw->chip_id == CHIP_ID_GENESIS && data)
516 + return -EOPNOTSUPP;
517 + return ethtool_op_set_sg(dev, data);
518 +}
519 +
520 +static int skge_set_tx_csum(struct net_device *dev, u32 data)
521 +{
522 + struct skge_port *skge = netdev_priv(dev);
523 + struct skge_hw *hw = skge->hw;
524 +
525 + if (hw->chip_id == CHIP_ID_GENESIS && data)
526 + return -EOPNOTSUPP;
527 +
528 + return ethtool_op_set_tx_csum(dev, data);
529 +}
530 +
531 +static u32 skge_get_rx_csum(struct net_device *dev)
532 +{
533 + struct skge_port *skge = netdev_priv(dev);
534 +
535 + return skge->rx_csum;
536 +}
537 +
538 +/* Only Yukon supports checksum offload. */
539 +static int skge_set_rx_csum(struct net_device *dev, u32 data)
540 +{
541 + struct skge_port *skge = netdev_priv(dev);
542 +
543 + if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
544 + return -EOPNOTSUPP;
545 +
546 + skge->rx_csum = data;
547 + return 0;
548 +}
549 +
550 +/* Only Yukon II supports TSO (not implemented yet) */
551 +static int skge_set_tso(struct net_device *dev, u32 data)
552 +{
553 + if (data)
554 + return -EOPNOTSUPP;
555 + return 0;
556 +}
557 +
558 +static void skge_get_pauseparam(struct net_device *dev,
559 + struct ethtool_pauseparam *ecmd)
560 +{
561 + struct skge_port *skge = netdev_priv(dev);
562 +
563 + ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
564 + || (skge->flow_control == FLOW_MODE_SYMMETRIC);
565 + ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
566 + || (skge->flow_control == FLOW_MODE_SYMMETRIC);
567 +
568 + ecmd->autoneg = skge->autoneg;
569 +}
570 +
571 +static int skge_set_pauseparam(struct net_device *dev,
572 + struct ethtool_pauseparam *ecmd)
573 +{
574 + struct skge_port *skge = netdev_priv(dev);
575 +
576 + skge->autoneg = ecmd->autoneg;
577 + if (ecmd->rx_pause && ecmd->tx_pause)
578 + skge->flow_control = FLOW_MODE_SYMMETRIC;
579 + else if(ecmd->rx_pause && !ecmd->tx_pause)
580 + skge->flow_control = FLOW_MODE_REM_SEND;
581 + else if(!ecmd->rx_pause && ecmd->tx_pause)
582 + skge->flow_control = FLOW_MODE_LOC_SEND;
583 + else
584 + skge->flow_control = FLOW_MODE_NONE;
585 +
586 + if (netif_running(dev)) {
587 + skge_down(dev);
588 + skge_up(dev);
589 + }
590 + return 0;
591 +}
592 +
593 +/* Chip internal frequency for clock calculations */
594 +static inline u32 hwkhz(const struct skge_hw *hw)
595 +{
596 + if (hw->chip_id == CHIP_ID_GENESIS)
597 + return 53215; /* or: 53.125 MHz */
598 + else if (hw->chip_id == CHIP_ID_YUKON_EC)
599 + return 125000; /* or: 125.000 MHz */
600 + else
601 + return 78215; /* or: 78.125 MHz */
602 +}
603 +
604 +/* Chip hz to microseconds */
605 +static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
606 +{
607 + return (ticks * 1000) / hwkhz(hw);
608 +}
609 +
610 +/* Microseconds to chip hz */
611 +static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
612 +{
613 + return hwkhz(hw) * usec / 1000;
614 +}
615 +
616 +static int skge_get_coalesce(struct net_device *dev,
617 + struct ethtool_coalesce *ecmd)
618 +{
619 + struct skge_port *skge = netdev_priv(dev);
620 + struct skge_hw *hw = skge->hw;
621 + int port = skge->port;
622 +
623 + ecmd->rx_coalesce_usecs = 0;
624 + ecmd->tx_coalesce_usecs = 0;
625 +
626 + if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
627 + u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
628 + u32 msk = skge_read32(hw, B2_IRQM_MSK);
629 +
630 + if (msk & rxirqmask[port])
631 + ecmd->rx_coalesce_usecs = delay;
632 + if (msk & txirqmask[port])
633 + ecmd->tx_coalesce_usecs = delay;
634 + }
635 +
636 + return 0;
637 +}
638 +
639 +/* Note: interrupt timer is per board, but can turn on/off per port */
640 +static int skge_set_coalesce(struct net_device *dev,
641 + struct ethtool_coalesce *ecmd)
642 +{
643 + struct skge_port *skge = netdev_priv(dev);
644 + struct skge_hw *hw = skge->hw;
645 + int port = skge->port;
646 + u32 msk = skge_read32(hw, B2_IRQM_MSK);
647 + u32 delay = 25;
648 +
649 + if (ecmd->rx_coalesce_usecs == 0)
650 + msk &= ~rxirqmask[port];
651 + else if (ecmd->rx_coalesce_usecs < 25 ||
652 + ecmd->rx_coalesce_usecs > 33333)
653 + return -EINVAL;
654 + else {
655 + msk |= rxirqmask[port];
656 + delay = ecmd->rx_coalesce_usecs;
657 + }
658 +
659 + if (ecmd->tx_coalesce_usecs == 0)
660 + msk &= ~txirqmask[port];
661 + else if (ecmd->tx_coalesce_usecs < 25 ||
662 + ecmd->tx_coalesce_usecs > 33333)
663 + return -EINVAL;
664 + else {
665 + msk |= txirqmask[port];
666 + delay = min(delay, ecmd->rx_coalesce_usecs);
667 + }
668 +
669 + skge_write32(hw, B2_IRQM_MSK, msk);
670 + if (msk == 0)
671 + skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
672 + else {
673 + skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
674 + skge_write32(hw, B2_IRQM_CTRL, TIM_START);
675 + }
676 + return 0;
677 +}
678 +
679 +static void skge_led_on(struct skge_hw *hw, int port)
680 +{
681 + if (hw->chip_id == CHIP_ID_GENESIS) {
682 + skge_write8(hw, SKGEMAC_REG(port, LNK_LED_REG), LINKLED_ON);
683 + skge_write8(hw, B0_LED, LED_STAT_ON);
684 +
685 + skge_write8(hw, SKGEMAC_REG(port, RX_LED_TST), LED_T_ON);
686 + skge_write32(hw, SKGEMAC_REG(port, RX_LED_VAL), 100);
687 + skge_write8(hw, SKGEMAC_REG(port, RX_LED_CTRL), LED_START);
688 +
689 + switch (hw->phy_type) {
690 + case SK_PHY_BCOM:
691 + skge_xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL,
692 + PHY_B_PEC_LED_ON);
693 + break;
694 + case SK_PHY_LONE:
695 + skge_xm_phy_write(hw, port, PHY_LONE_LED_CFG,
696 + 0x0800);
697 + break;
698 + default:
699 + skge_write8(hw, SKGEMAC_REG(port, TX_LED_TST), LED_T_ON);
700 + skge_write32(hw, SKGEMAC_REG(port, TX_LED_VAL), 100);
701 + skge_write8(hw, SKGEMAC_REG(port, TX_LED_CTRL), LED_START);
702 + }
703 + } else {
704 + skge_gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
705 + skge_gm_phy_write(hw, port, PHY_MARV_LED_OVER,
706 + PHY_M_LED_MO_DUP(MO_LED_ON) |
707 + PHY_M_LED_MO_10(MO_LED_ON) |
708 + PHY_M_LED_MO_100(MO_LED_ON) |
709 + PHY_M_LED_MO_1000(MO_LED_ON) |
710 + PHY_M_LED_MO_RX(MO_LED_ON));
711 + }
712 +}
713 +
714 +static void skge_led_off(struct skge_hw *hw, int port)
715 +{
716 + if (hw->chip_id == CHIP_ID_GENESIS) {
717 + skge_write8(hw, SKGEMAC_REG(port, LNK_LED_REG), LINKLED_OFF);
718 + skge_write8(hw, B0_LED, LED_STAT_OFF);
719 +
720 + skge_write32(hw, SKGEMAC_REG(port, RX_LED_VAL), 0);
721 + skge_write8(hw, SKGEMAC_REG(port, RX_LED_CTRL), LED_T_OFF);
722 +
723 + switch (hw->phy_type) {
724 + case SK_PHY_BCOM:
725 + skge_xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL,
726 + PHY_B_PEC_LED_OFF);
727 + break;
728 + case SK_PHY_LONE:
729 + skge_xm_phy_write(hw, port, PHY_LONE_LED_CFG,
730 + PHY_L_LC_LEDT);
731 + break;
732 + default:
733 + skge_write32(hw, SKGEMAC_REG(port, TX_LED_VAL), 0);
734 + skge_write8(hw, SKGEMAC_REG(port, TX_LED_CTRL), LED_T_OFF);
735 + }
736 + } else {
737 + skge_gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
738 + skge_gm_phy_write(hw, port, PHY_MARV_LED_OVER,
739 + PHY_M_LED_MO_DUP(MO_LED_OFF) |
740 + PHY_M_LED_MO_10(MO_LED_OFF) |
741 + PHY_M_LED_MO_100(MO_LED_OFF) |
742 + PHY_M_LED_MO_1000(MO_LED_OFF) |
743 + PHY_M_LED_MO_RX(MO_LED_OFF));
744 + }
745 +}
746 +
747 +static void skge_blink_timer(unsigned long data)
748 +{
749 + struct skge_port *skge = (struct skge_port *) data;
750 + struct skge_hw *hw = skge->hw;
751 + unsigned long flags;
752 +
753 + spin_lock_irqsave(&hw->phy_lock, flags);
754 + if (skge->blink_on)
755 + skge_led_on(hw, skge->port);
756 + else
757 + skge_led_off(hw, skge->port);
758 + spin_unlock_irqrestore(&hw->phy_lock, flags);
759 +
760 + skge->blink_on = !skge->blink_on;
761 + mod_timer(&skge->led_blink, jiffies + BLINK_HZ);
762 +}
763 +
764 +/* blink LED's for finding board */
765 +static int skge_phys_id(struct net_device *dev, u32 data)
766 +{
767 + struct skge_port *skge = netdev_priv(dev);
768 +
769 + if(!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
770 + data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
771 +
772 + /* start blinking */
773 + skge->blink_on = 1;
774 + mod_timer(&skge->led_blink, jiffies+1);
775 +
776 + msleep_interruptible(data * 1000);
777 + del_timer_sync(&skge->led_blink);
778 +
779 + skge_led_off(skge->hw, skge->port);
780 +
781 + return 0;
782 +}
783 +
784 +static struct ethtool_ops skge_ethtool_ops = {
785 + .get_settings = skge_get_settings,
786 + .set_settings = skge_set_settings,
787 + .get_drvinfo = skge_get_drvinfo,
788 + .get_regs_len = skge_get_regs_len,
789 + .get_regs = skge_get_regs,
790 + .get_wol = skge_get_wol,
791 + .set_wol = skge_set_wol,
792 + .get_msglevel = skge_get_msglevel,
793 + .set_msglevel = skge_set_msglevel,
794 + .nway_reset = skge_nway_reset,
795 + .get_link = ethtool_op_get_link,
796 + .get_ringparam = skge_get_ring_param,
797 + .set_ringparam = skge_set_ring_param,
798 + .get_pauseparam = skge_get_pauseparam,
799 + .set_pauseparam = skge_set_pauseparam,
800 + .get_coalesce = skge_get_coalesce,
801 + .set_coalesce = skge_set_coalesce,
802 + .get_tso = ethtool_op_get_tso,
803 + .set_tso = skge_set_tso,
804 + .get_sg = ethtool_op_get_sg,
805 + .set_sg = skge_set_sg,
806 + .get_tx_csum = ethtool_op_get_tx_csum,
807 + .set_tx_csum = skge_set_tx_csum,
808 + .get_rx_csum = skge_get_rx_csum,
809 + .set_rx_csum = skge_set_rx_csum,
810 + .get_strings = skge_get_strings,
811 + .phys_id = skge_phys_id,
812 + .get_stats_count = skge_get_stats_count,
813 + .get_ethtool_stats = skge_get_ethtool_stats,
814 +};
815 +
816 +/*
817 + * Allocate ring elements and chain them together
818 + * One-to-one association of board descriptors with ring elements
819 + */
820 +static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
821 +{
822 + struct skge_tx_desc *d;
823 + struct skge_element *e;
824 + int i;
825 +
826 + ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);
827 + if (!ring->start)
828 + return -ENOMEM;
829 +
830 + for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
831 + e->desc = d;
832 + if (i == ring->count - 1) {
833 + e->next = ring->start;
834 + d->next_offset = base;
835 + } else {
836 + e->next = e + 1;
837 + d->next_offset = base + (i+1) * sizeof(*d);
838 + }
839 + }
840 + ring->to_use = ring->to_clean = ring->start;
841 +
842 + return 0;
843 +}
844 +
845 +/* Setup buffer for receiving */
846 +static inline int skge_rx_alloc(struct skge_port *skge,
847 + struct skge_element *e)
848 +{
849 + unsigned long bufsize = skge->netdev->mtu + ETH_HLEN; /* VLAN? */
850 + struct skge_rx_desc *rd = e->desc;
851 + struct sk_buff *skb;
852 + u64 map;
853 +
854 + skb = dev_alloc_skb(bufsize + NET_IP_ALIGN);
855 + if (unlikely(!skb)) {
856 + printk(KERN_DEBUG PFX "%s: out of memory for receive\n",
857 + skge->netdev->name);
858 + return -ENOMEM;
859 + }
860 +
861 + skb->dev = skge->netdev;
862 + skb_reserve(skb, NET_IP_ALIGN);
863 +
864 + map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
865 + PCI_DMA_FROMDEVICE);
866 +
867 + rd->dma_lo = map;
868 + rd->dma_hi = map >> 32;
869 + e->skb = skb;
870 + rd->csum1_start = ETH_HLEN;
871 + rd->csum2_start = ETH_HLEN;
872 + rd->csum1 = 0;
873 + rd->csum2 = 0;
874 +
875 + wmb();
876 +
877 + rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
878 + pci_unmap_addr_set(e, mapaddr, map);
879 + pci_unmap_len_set(e, maplen, bufsize);
880 + return 0;
881 +}
882 +
883 +/* Free all unused buffers in receive ring, assumes receiver stopped */
884 +static void skge_rx_clean(struct skge_port *skge)
885 +{
886 + struct skge_hw *hw = skge->hw;
887 + struct skge_ring *ring = &skge->rx_ring;
888 + struct skge_element *e;
889 +
890 + for (e = ring->to_clean; e != ring->to_use; e = e->next) {
891 + struct skge_rx_desc *rd = e->desc;
892 + rd->control = 0;
893 +
894 + pci_unmap_single(hw->pdev,
895 + pci_unmap_addr(e, mapaddr),
896 + pci_unmap_len(e, maplen),
897 + PCI_DMA_FROMDEVICE);
898 + dev_kfree_skb(e->skb);
899 + e->skb = NULL;
900 + }
901 + ring->to_clean = e;
902 +}
903 +
904 +/* Allocate buffers for receive ring
905 + * For receive: to_use is refill location
906 + * to_clean is next received frame.
907 + *
908 + * if (to_use == to_clean)
909 + * then ring all frames in ring need buffers
910 + * if (to_use->next == to_clean)
911 + * then ring all frames in ring have buffers
912 + */
913 +static int skge_rx_fill(struct skge_port *skge)
914 +{
915 + struct skge_ring *ring = &skge->rx_ring;
916 + struct skge_element *e;
917 + int ret = 0;
918 +
919 + for (e = ring->to_use; e->next != ring->to_clean; e = e->next) {
920 + if (skge_rx_alloc(skge, e)) {
921 + ret = 1;
922 + break;
923 + }
924 +
925 + }
926 + ring->to_use = e;
927 +
928 + return ret;
929 +}
930 +
931 +static void skge_link_up(struct skge_port *skge)
932 +{
933 + netif_carrier_on(skge->netdev);
934 + if (skge->tx_avail > MAX_SKB_FRAGS + 1)
935 + netif_wake_queue(skge->netdev);
936 +
937 + if (netif_msg_link(skge))
938 + printk(KERN_INFO PFX
939 + "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
940 + skge->netdev->name, skge->speed,
941 + skge->duplex == DUPLEX_FULL ? "full" : "half",
942 + (skge->flow_control == FLOW_MODE_NONE) ? "none" :
943 + (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
944 + (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
945 + (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
946 + "unknown");
947 +}
948 +
949 +static void skge_link_down(struct skge_port *skge)
950 +{
951 + netif_carrier_off(skge->netdev);
952 + netif_stop_queue(skge->netdev);
953 +
954 + if (netif_msg_link(skge))
955 + printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
956 +}
957 +
958 +static u16 skge_xm_phy_read(struct skge_hw *hw, int port, u16 reg)
959 +{
960 + int i;
961 + u16 v;
962 +
963 + skge_xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
964 + v = skge_xm_read16(hw, port, XM_PHY_DATA);
965 + if (hw->phy_type != SK_PHY_XMAC) {
966 + for (i = 0; i < PHY_RETRIES; i++) {
967 + udelay(1);
968 + if (skge_xm_read16(hw, port, XM_MMU_CMD)
969 + & XM_MMU_PHY_RDY)
970 + goto ready;
971 + }
972 +
973 + printk(KERN_WARNING PFX "%s: phy read timed out\n",
974 + hw->dev[port]->name);
975 + return 0;
976 + ready:
977 + v = skge_xm_read16(hw, port, XM_PHY_DATA);
978 + }
979 +
980 + return v;
981 +}
982 +
983 +static void skge_xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
984 +{
985 + int i;
986 +
987 + skge_xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
988 + for (i = 0; i < PHY_RETRIES; i++) {
989 + if (!(skge_xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
990 + goto ready;
991 + cpu_relax();
992 + }
993 + printk(KERN_WARNING PFX "%s: phy write failed to come ready\n",
994 + hw->dev[port]->name);
995 +
996 +
997 + ready:
998 + skge_xm_write16(hw, port, XM_PHY_DATA, val);
999 + for (i = 0; i < PHY_RETRIES; i++) {
1000 + udelay(1);
1001 + if (!(skge_xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1002 + return;
1003 + }
1004 + printk(KERN_WARNING PFX "%s: phy write timed out\n",
1005 + hw->dev[port]->name);
1006 +}
1007 +
1008 +static void genesis_init(struct skge_hw *hw)
1009 +{
1010 + /* set blink source counter */
1011 + skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1012 + skge_write8(hw, B2_BSC_CTRL, BSC_START);
1013 +
1014 + /* configure mac arbiter */
1015 + skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1016 +
1017 + /* configure mac arbiter timeout values */
1018 + skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1019 + skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1020 + skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1021 + skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1022 +
1023 + skge_write8(hw, B3_MA_RCINI_RX1, 0);
1024 + skge_write8(hw, B3_MA_RCINI_RX2, 0);
1025 + skge_write8(hw, B3_MA_RCINI_TX1, 0);
1026 + skge_write8(hw, B3_MA_RCINI_TX2, 0);
1027 +
1028 + /* configure packet arbiter timeout */
1029 + skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1030 + skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1031 + skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1032 + skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1033 + skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1034 +}
1035 +
1036 +static void genesis_reset(struct skge_hw *hw, int port)
1037 +{
1038 + int i;
1039 + u64 zero = 0;
1040 +
1041 + /* reset the statistics module */
1042 + skge_xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1043 + skge_xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
1044 + skge_xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1045 + skge_xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1046 + skge_xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1047 +
1048 + /* disable all PHY IRQs */
1049 + if (hw->phy_type == SK_PHY_BCOM)
1050 + skge_xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1051 +
1052 + skge_xm_outhash(hw, port, XM_HSM, (u8 *) &zero);
1053 + for (i = 0; i < 15; i++)
1054 + skge_xm_outaddr(hw, port, XM_EXM(i), (u8 *) &zero);
1055 + skge_xm_outhash(hw, port, XM_SRC_CHK, (u8 *) &zero);
1056 +}
1057 +
1058 +
1059 +static void genesis_mac_init(struct skge_hw *hw, int port)
1060 +{
1061 + struct skge_port *skge = netdev_priv(hw->dev[port]);
1062 + int i;
1063 + u32 r;
1064 + u16 id1;
1065 + u16 ctrl1, ctrl2, ctrl3, ctrl4, ctrl5;
1066 +
1067 + /* magic workaround patterns for Broadcom */
1068 + static const struct {
1069 + u16 reg;
1070 + u16 val;
1071 + } A1hack[] = {
1072 + { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1073 + { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1074 + { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1075 + { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1076 + }, C0hack[] = {
1077 + { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1078 + { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1079 + };
1080 +
1081 +
1082 + /* initialize Rx, Tx and Link LED */
1083 + skge_write8(hw, SKGEMAC_REG(port, LNK_LED_REG), LINKLED_ON);
1084 + skge_write8(hw, SKGEMAC_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
1085 +
1086 + skge_write8(hw, SKGEMAC_REG(port, RX_LED_CTRL), LED_START);
1087 + skge_write8(hw, SKGEMAC_REG(port, TX_LED_CTRL), LED_START);
1088 +
1089 + /* Unreset the XMAC. */
1090 + skge_write16(hw, SKGEMAC_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1091 +
1092 + /*
1093 + * Perform additional initialization for external PHYs,
1094 + * namely for the 1000baseTX cards that use the XMAC's
1095 + * GMII mode.
1096 + */
1097 + spin_lock_bh(&hw->phy_lock);
1098 + if (hw->phy_type != SK_PHY_XMAC) {
1099 + /* Take PHY out of reset. */
1100 + r = skge_read32(hw, B2_GP_IO);
1101 + if (port == 0)
1102 + r |= GP_DIR_0|GP_IO_0;
1103 + else
1104 + r |= GP_DIR_2|GP_IO_2;
1105 +
1106 + skge_write32(hw, B2_GP_IO, r);
1107 + skge_read32(hw, B2_GP_IO);
1108 +
1109 + /* Enable GMII mode on the XMAC. */
1110 + skge_xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1111 +
1112 + id1 = skge_xm_phy_read(hw, port, PHY_XMAC_ID1);
1113 +
1114 + /* Optimize MDIO transfer by suppressing preamble. */
1115 + skge_xm_write16(hw, port, XM_MMU_CMD,
1116 + skge_xm_read16(hw, port, XM_MMU_CMD)
1117 + | XM_MMU_NO_PRE);
1118 +
1119 + if (id1 == PHY_BCOM_ID1_C0) {
1120 + /*
1121 + * Workaround BCOM Errata for the C0 type.
1122 + * Write magic patterns to reserved registers.
1123 + */
1124 + for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1125 + skge_xm_phy_write(hw, port,
1126 + C0hack[i].reg, C0hack[i].val);
1127 +
1128 + } else if (id1 == PHY_BCOM_ID1_A1) {
1129 + /*
1130 + * Workaround BCOM Errata for the A1 type.
1131 + * Write magic patterns to reserved registers.
1132 + */
1133 + for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1134 + skge_xm_phy_write(hw, port,
1135 + A1hack[i].reg, A1hack[i].val);
1136 + }
1137 +
1138 + /*
1139 + * Workaround BCOM Errata (#10523) for all BCom PHYs.
1140 + * Disable Power Management after reset.
1141 + */
1142 + r = skge_xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1143 + skge_xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r | PHY_B_AC_DIS_PM);
1144 + }
1145 +
1146 + /* Dummy read */
1147 + skge_xm_read16(hw, port, XM_ISRC);
1148 +
1149 + r = skge_xm_read32(hw, port, XM_MODE);
1150 + skge_xm_write32(hw, port, XM_MODE, r|XM_MD_CSA);
1151 +
1152 + /* We don't need the FCS appended to the packet. */
1153 + r = skge_xm_read16(hw, port, XM_RX_CMD);
1154 + skge_xm_write16(hw, port, XM_RX_CMD, r | XM_RX_STRIP_FCS);
1155 +
1156 + /* We want short frames padded to 60 bytes. */
1157 + r = skge_xm_read16(hw, port, XM_TX_CMD);
1158 + skge_xm_write16(hw, port, XM_TX_CMD, r | XM_TX_AUTO_PAD);
1159 +
1160 + /*
1161 + * Enable the reception of all error frames. This is is
1162 + * a necessary evil due to the design of the XMAC. The
1163 + * XMAC's receive FIFO is only 8K in size, however jumbo
1164 + * frames can be up to 9000 bytes in length. When bad
1165 + * frame filtering is enabled, the XMAC's RX FIFO operates
1166 + * in 'store and forward' mode. For this to work, the
1167 + * entire frame has to fit into the FIFO, but that means
1168 + * that jumbo frames larger than 8192 bytes will be
1169 + * truncated. Disabling all bad frame filtering causes
1170 + * the RX FIFO to operate in streaming mode, in which
1171 + * case the XMAC will start transfering frames out of the
1172 + * RX FIFO as soon as the FIFO threshold is reached.
1173 + */
1174 + r = skge_xm_read32(hw, port, XM_MODE);
1175 + skge_xm_write32(hw, port, XM_MODE,
1176 + XM_MD_RX_CRCE|XM_MD_RX_LONG|XM_MD_RX_RUNT|
1177 + XM_MD_RX_ERR|XM_MD_RX_IRLE);
1178 +
1179 + skge_xm_outaddr(hw, port, XM_SA, hw->dev[port]->dev_addr);
1180 + skge_xm_outaddr(hw, port, XM_EXM(0), hw->dev[port]->dev_addr);
1181 +
1182 + /*
1183 + * Bump up the transmit threshold. This helps hold off transmit
1184 + * underruns when we're blasting traffic from both ports at once.
1185 + */
1186 + skge_xm_write16(hw, port, XM_TX_THR, 512);
1187 +
1188 + /* Configure MAC arbiter */
1189 + skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1190 +
1191 + /* configure timeout values */
1192 + skge_write8(hw, B3_MA_TOINI_RX1, 72);
1193 + skge_write8(hw, B3_MA_TOINI_RX2, 72);
1194 + skge_write8(hw, B3_MA_TOINI_TX1, 72);
1195 + skge_write8(hw, B3_MA_TOINI_TX2, 72);
1196 +
1197 + skge_write8(hw, B3_MA_RCINI_RX1, 0);
1198 + skge_write8(hw, B3_MA_RCINI_RX2, 0);
1199 + skge_write8(hw, B3_MA_RCINI_TX1, 0);
1200 + skge_write8(hw, B3_MA_RCINI_TX2, 0);
1201 +
1202 + /* Configure Rx MAC FIFO */
1203 + skge_write8(hw, SKGEMAC_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1204 + skge_write16(hw, SKGEMAC_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1205 + skge_write8(hw, SKGEMAC_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1206 +
1207 + /* Configure Tx MAC FIFO */
1208 + skge_write8(hw, SKGEMAC_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1209 + skge_write16(hw, SKGEMAC_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1210 + skge_write8(hw, SKGEMAC_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1211 +
1212 + if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1213 + /* Enable frame flushing if jumbo frames used */
1214 + skge_write16(hw, SKGEMAC_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1215 + } else {
1216 + /* enable timeout timers if normal frames */
1217 + skge_write16(hw, B3_PA_CTRL,
1218 + port == 0 ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1219 + }
1220 +
1221 +
1222 + r = skge_xm_read16(hw, port, XM_RX_CMD);
1223 + if (hw->dev[port]->mtu > ETH_DATA_LEN)
1224 + skge_xm_write16(hw, port, XM_RX_CMD, r | XM_RX_BIG_PK_OK);
1225 + else
1226 + skge_xm_write16(hw, port, XM_RX_CMD, r & ~(XM_RX_BIG_PK_OK));
1227 +
1228 + switch (hw->phy_type) {
1229 + case SK_PHY_XMAC:
1230 + if (skge->autoneg == AUTONEG_ENABLE) {
1231 + ctrl1 = PHY_X_AN_FD | PHY_X_AN_HD;
1232 +
1233 + switch (skge->flow_control) {
1234 + case FLOW_MODE_NONE:
1235 + ctrl1 |= PHY_X_P_NO_PAUSE;
1236 + break;
1237 + case FLOW_MODE_LOC_SEND:
1238 + ctrl1 |= PHY_X_P_ASYM_MD;
1239 + break;
1240 + case FLOW_MODE_SYMMETRIC:
1241 + ctrl1 |= PHY_X_P_SYM_MD;
1242 + break;
1243 + case FLOW_MODE_REM_SEND:
1244 + ctrl1 |= PHY_X_P_BOTH_MD;
1245 + break;
1246 + }
1247 +
1248 + skge_xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl1);
1249 + ctrl2 = PHY_CT_ANE | PHY_CT_RE_CFG;
1250 + } else {
1251 + ctrl2 = 0;
1252 + if (skge->duplex == DUPLEX_FULL)
1253 + ctrl2 |= PHY_CT_DUP_MD;
1254 + }
1255 +
1256 + skge_xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl2);
1257 + break;
1258 +
1259 + case SK_PHY_BCOM:
1260 + ctrl1 = PHY_CT_SP1000;
1261 + ctrl2 = 0;
1262 + ctrl3 = PHY_SEL_TYPE;
1263 + ctrl4 = PHY_B_PEC_EN_LTR;
1264 + ctrl5 = PHY_B_AC_TX_TST;
1265 +
1266 + if (skge->autoneg == AUTONEG_ENABLE) {
1267 + /*
1268 + * Workaround BCOM Errata #1 for the C5 type.
1269 + * 1000Base-T Link Acquisition Failure in Slave Mode
1270 + * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1271 + */
1272 + ctrl2 |= PHY_B_1000C_RD;
1273 + if (skge->advertising & ADVERTISED_1000baseT_Half)
1274 + ctrl2 |= PHY_B_1000C_AHD;
1275 + if (skge->advertising & ADVERTISED_1000baseT_Full)
1276 + ctrl2 |= PHY_B_1000C_AFD;
1277 +
1278 + /* Set Flow-control capabilities */
1279 + switch (skge->flow_control) {
1280 + case FLOW_MODE_NONE:
1281 + ctrl3 |= PHY_B_P_NO_PAUSE;
1282 + break;
1283 + case FLOW_MODE_LOC_SEND:
1284 + ctrl3 |= PHY_B_P_ASYM_MD;
1285 + break;
1286 + case FLOW_MODE_SYMMETRIC:
1287 + ctrl3 |= PHY_B_P_SYM_MD;
1288 + break;
1289 + case FLOW_MODE_REM_SEND:
1290 + ctrl3 |= PHY_B_P_BOTH_MD;
1291 + break;
1292 + }
1293 +
1294 + /* Restart Auto-negotiation */
1295 + ctrl1 |= PHY_CT_ANE | PHY_CT_RE_CFG;
1296 + } else {
1297 + if (skge->duplex == DUPLEX_FULL)
1298 + ctrl1 |= PHY_CT_DUP_MD;
1299 +
1300 + ctrl2 |= PHY_B_1000C_MSE; /* set it to Slave */
1301 + }
1302 +
1303 + skge_xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, ctrl2);
1304 + skge_xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV, ctrl3);
1305 +
1306 + if (skge->netdev->mtu > ETH_DATA_LEN) {
1307 + ctrl4 |= PHY_B_PEC_HIGH_LA;
1308 + ctrl5 |= PHY_B_AC_LONG_PACK;
1309 +
1310 + skge_xm_phy_write(hw, port,PHY_BCOM_AUX_CTRL, ctrl5);
1311 + }
1312 +
1313 + skge_xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ctrl4);
1314 + skge_xm_phy_write(hw, port, PHY_BCOM_CTRL, ctrl1);
1315 + break;
1316 + }
1317 + spin_unlock_bh(&hw->phy_lock);
1318 +
1319 + /* Clear MIB counters */
1320 + skge_xm_write16(hw, port, XM_STAT_CMD,
1321 + XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1322 + /* Clear two times according to Errata #3 */
1323 + skge_xm_write16(hw, port, XM_STAT_CMD,
1324 + XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1325 +
1326 + /* Start polling for link status */
1327 + mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
1328 +}
1329 +
1330 +static void genesis_stop(struct skge_port *skge)
1331 +{
1332 + struct skge_hw *hw = skge->hw;
1333 + int port = skge->port;
1334 +
1335 + /* Clear Tx packet arbiter timeout IRQ */
1336 + skge_write16(hw, B3_PA_CTRL,
1337 + port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1338 +
1339 + /*
1340 + * If the transfer stucks at the MAC the STOP command will not
1341 + * terminate if we don't flush the XMAC's transmit FIFO !
1342 + */
1343 + skge_xm_write32(hw, port, XM_MODE,
1344 + skge_xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1345 +
1346 +
1347 + /* Reset the MAC */
1348 + skge_write16(hw, SKGEMAC_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1349 +
1350 + /* For external PHYs there must be special handling */
1351 + if (hw->phy_type != SK_PHY_XMAC) {
1352 + u32 reg = skge_read32(hw, B2_GP_IO);
1353 +
1354 + if (port == 0) {
1355 + reg |= GP_DIR_0;
1356 + reg &= ~GP_IO_0;
1357 + } else {
1358 + reg |= GP_DIR_2;
1359 + reg &= ~GP_IO_2;
1360 + }
1361 + skge_write32(hw, B2_GP_IO, reg);
1362 + skge_read32(hw, B2_GP_IO);
1363 + }
1364 +
1365 + skge_xm_write16(hw, port, XM_MMU_CMD,
1366 + skge_xm_read16(hw, port, XM_MMU_CMD)
1367 + & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1368 +
1369 + skge_xm_read16(hw, port, XM_MMU_CMD);
1370 +}
1371 +
1372 +
1373 +static void genesis_get_stats(struct skge_port *skge, u64 *data)
1374 +{
1375 + struct skge_hw *hw = skge->hw;
1376 + int port = skge->port;
1377 + int i;
1378 + unsigned long timeout = jiffies + HZ;
1379 +
1380 + skge_xm_write16(hw, port,
1381 + XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1382 +
1383 + /* wait for update to complete */
1384 + while (skge_xm_read16(hw, port, XM_STAT_CMD)
1385 + & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1386 + if (time_after(jiffies, timeout))
1387 + break;
1388 + udelay(10);
1389 + }
1390 +
1391 + /* special case for 64 bit octet counter */
1392 + data[0] = (u64) skge_xm_read32(hw, port, XM_TXO_OK_HI) << 32
1393 + | skge_xm_read32(hw, port, XM_TXO_OK_LO);
1394 + data[1] = (u64) skge_xm_read32(hw, port, XM_RXO_OK_HI) << 32
1395 + | skge_xm_read32(hw, port, XM_RXO_OK_LO);
1396 +
1397 + for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1398 + data[i] = skge_xm_read32(hw, port, skge_stats[i].xmac_offset);
1399 +}
1400 +
1401 +static void genesis_mac_intr(struct skge_hw *hw, int port)
1402 +{
1403 + struct skge_port *skge = netdev_priv(hw->dev[port]);
1404 + u16 status = skge_xm_read16(hw, port, XM_ISRC);
1405 +
1406 + pr_debug("genesis_intr status %x\n", status);
1407 + if (hw->phy_type == SK_PHY_XMAC) {
1408 + /* LInk down, start polling for state change */
1409 + if (status & XM_IS_INP_ASS) {
1410 + skge_xm_write16(hw, port, XM_IMSK,
1411 + skge_xm_read16(hw, port, XM_IMSK) | XM_IS_INP_ASS);
1412 + mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
1413 + }
1414 + else if (status & XM_IS_AND)
1415 + mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
1416 + }
1417 +
1418 + if (status & XM_IS_TXF_UR) {
1419 + skge_xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1420 + ++skge->net_stats.tx_fifo_errors;
1421 + }
1422 + if (status & XM_IS_RXF_OV) {
1423 + skge_xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1424 + ++skge->net_stats.rx_fifo_errors;
1425 + }
1426 +}
1427 +
1428 +static void skge_gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1429 +{
1430 + int i;
1431 +
1432 + skge_gma_write16(hw, port, GM_SMI_DATA, val);
1433 + skge_gma_write16(hw, port, GM_SMI_CTRL,
1434 + GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1435 + for (i = 0; i < PHY_RETRIES; i++) {
1436 + udelay(1);
1437 +
1438 + if (!(skge_gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1439 + break;
1440 + }
1441 +}
1442 +
1443 +static u16 skge_gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1444 +{
1445 + int i;
1446 +
1447 + skge_gma_write16(hw, port, GM_SMI_CTRL,
1448 + GM_SMI_CT_PHY_AD(hw->phy_addr)
1449 + | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1450 +
1451 + for (i = 0; i < PHY_RETRIES; i++) {
1452 + udelay(1);
1453 + if (skge_gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1454 + goto ready;
1455 + }
1456 +
1457 + printk(KERN_WARNING PFX "%s: phy read timeout\n",
1458 + hw->dev[port]->name);
1459 + return 0;
1460 + ready:
1461 + return skge_gma_read16(hw, port, GM_SMI_DATA);
1462 +}
1463 +
1464 +static void genesis_link_down(struct skge_port *skge)
1465 +{
1466 + struct skge_hw *hw = skge->hw;
1467 + int port = skge->port;
1468 +
1469 + pr_debug("genesis_link_down\n");
1470 +
1471 + skge_xm_write16(hw, port, XM_MMU_CMD,
1472 + skge_xm_read16(hw, port, XM_MMU_CMD)
1473 + & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1474 +
1475 + /* dummy read to ensure writing */
1476 + (void) skge_xm_read16(hw, port, XM_MMU_CMD);
1477 +
1478 + skge_link_down(skge);
1479 +}
1480 +
1481 +static void genesis_link_up(struct skge_port *skge)
1482 +{
1483 + struct skge_hw *hw = skge->hw;
1484 + int port = skge->port;
1485 + u16 cmd;
1486 + u32 mode, msk;
1487 +
1488 + pr_debug("genesis_link_up\n");
1489 + cmd = skge_xm_read16(hw, port, XM_MMU_CMD);
1490 +
1491 + /*
1492 + * enabling pause frame reception is required for 1000BT
1493 + * because the XMAC is not reset if the link is going down
1494 + */
1495 + if (skge->flow_control == FLOW_MODE_NONE ||
1496 + skge->flow_control == FLOW_MODE_LOC_SEND)
1497 + cmd |= XM_MMU_IGN_PF;
1498 + else
1499 + /* Enable Pause Frame Reception */
1500 + cmd &= ~XM_MMU_IGN_PF;
1501 +
1502 + skge_xm_write16(hw, port, XM_MMU_CMD, cmd);
1503 +
1504 + mode = skge_xm_read32(hw, port, XM_MODE);
1505 + if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1506 + skge->flow_control == FLOW_MODE_LOC_SEND) {
1507 + /*
1508 + * Configure Pause Frame Generation
1509 + * Use internal and external Pause Frame Generation.
1510 + * Sending pause frames is edge triggered.
1511 + * Send a Pause frame with the maximum pause time if
1512 + * internal oder external FIFO full condition occurs.
1513 + * Send a zero pause time frame to re-start transmission.
1514 + */
1515 + /* XM_PAUSE_DA = '010000C28001' (default) */
1516 + /* XM_MAC_PTIME = 0xffff (maximum) */
1517 + /* remember this value is defined in big endian (!) */
1518 + skge_xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1519 +
1520 + mode |= XM_PAUSE_MODE;
1521 + skge_write16(hw, SKGEMAC_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1522 + } else {
1523 + /*
1524 + * disable pause frame generation is required for 1000BT
1525 + * because the XMAC is not reset if the link is going down
1526 + */
1527 + /* Disable Pause Mode in Mode Register */
1528 + mode &= ~XM_PAUSE_MODE;
1529 +
1530 + skge_write16(hw, SKGEMAC_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1531 + }
1532 +
1533 + skge_xm_write32(hw, port, XM_MODE, mode);
1534 +
1535 + msk = XM_DEF_MSK;
1536 + if (hw->phy_type != SK_PHY_XMAC)
1537 + msk |= XM_IS_INP_ASS; /* disable GP0 interrupt bit */
1538 +
1539 + skge_xm_write16(hw, port, XM_IMSK, msk);
1540 + skge_xm_read16(hw, port, XM_ISRC);
1541 +
1542 + /* get MMU Command Reg. */
1543 + cmd = skge_xm_read16(hw, port, XM_MMU_CMD);
1544 + if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1545 + cmd |= XM_MMU_GMII_FD;
1546 +
1547 + if (hw->phy_type == SK_PHY_BCOM) {
1548 + /*
1549 + * Workaround BCOM Errata (#10523) for all BCom Phys
1550 + * Enable Power Management after link up
1551 + */
1552 + skge_xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1553 + skge_xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1554 + & ~PHY_B_AC_DIS_PM);
1555 + skge_xm_phy_write(hw, port, PHY_BCOM_INT_MASK,
1556 + PHY_B_DEF_MSK);
1557 + }
1558 +
1559 + /* enable Rx/Tx */
1560 + skge_xm_write16(hw, port, XM_MMU_CMD,
1561 + cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1562 + skge_link_up(skge);
1563 +}
1564 +
1565 +
1566 +static void genesis_bcom_intr(struct skge_port *skge)
1567 +{
1568 + struct skge_hw *hw = skge->hw;
1569 + int port = skge->port;
1570 + u16 stat = skge_xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1571 +
1572 + pr_debug("genesis_bcom intr stat=%x\n", stat);
1573 +
1574 + /* Workaround BCom Errata:
1575 + * enable and disable loopback mode if "NO HCD" occurs.
1576 + */
1577 + if (stat & PHY_B_IS_NO_HDCL) {
1578 + u16 ctrl = skge_xm_phy_read(hw, port, PHY_BCOM_CTRL);
1579 + skge_xm_phy_write(hw, port, PHY_BCOM_CTRL,
1580 + ctrl | PHY_CT_LOOP);
1581 + skge_xm_phy_write(hw, port, PHY_BCOM_CTRL,
1582 + ctrl & ~PHY_CT_LOOP);
1583 + }
1584 +
1585 + stat = skge_xm_phy_read(hw, port, PHY_BCOM_STAT);
1586 + if (stat & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) {
1587 + u16 aux = skge_xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1588 + if ( !(aux & PHY_B_AS_LS) && netif_carrier_ok(skge->netdev))
1589 + genesis_link_down(skge);
1590 +
1591 + else if (stat & PHY_B_IS_LST_CHANGE) {
1592 + if (aux & PHY_B_AS_AN_C) {
1593 + switch (aux & PHY_B_AS_AN_RES_MSK) {
1594 + case PHY_B_RES_1000FD:
1595 + skge->duplex = DUPLEX_FULL;
1596 + break;
1597 + case PHY_B_RES_1000HD:
1598 + skge->duplex = DUPLEX_HALF;
1599 + break;
1600 + }
1601 +
1602 + switch (aux & PHY_B_AS_PAUSE_MSK) {
1603 + case PHY_B_AS_PAUSE_MSK:
1604 + skge->flow_control = FLOW_MODE_SYMMETRIC;
1605 + break;
1606 + case PHY_B_AS_PRR:
1607 + skge->flow_control = FLOW_MODE_REM_SEND;
1608 + break;
1609 + case PHY_B_AS_PRT:
1610 + skge->flow_control = FLOW_MODE_LOC_SEND;
1611 + break;
1612 + default:
1613 + skge->flow_control = FLOW_MODE_NONE;
1614 + }
1615 + skge->speed = SPEED_1000;
1616 + }
1617 + genesis_link_up(skge);
1618 + }
1619 + else
1620 + mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
1621 + }
1622 +}
1623 +
1624 +/* Perodic poll of phy status to check for link transistion */
1625 +static void skge_link_timer(unsigned long __arg)
1626 +{
1627 + struct skge_port *skge = (struct skge_port *) __arg;
1628 + struct skge_hw *hw = skge->hw;
1629 + int port = skge->port;
1630 +
1631 + if (hw->chip_id != CHIP_ID_GENESIS || !netif_running(skge->netdev))
1632 + return;
1633 +
1634 + spin_lock_bh(&hw->phy_lock);
1635 + if (hw->phy_type == SK_PHY_BCOM)
1636 + genesis_bcom_intr(skge);
1637 + else {
1638 + int i;
1639 + for (i = 0; i < 3; i++)
1640 + if (skge_xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS)
1641 + break;
1642 +
1643 + if (i == 3)
1644 + mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
1645 + else
1646 + genesis_link_up(skge);
1647 + }
1648 + spin_unlock_bh(&hw->phy_lock);
1649 +}
1650 +
1651 +/* Marvell Phy Initailization */
1652 +static void yukon_init(struct skge_hw *hw, int port)
1653 +{
1654 + struct skge_port *skge = netdev_priv(hw->dev[port]);
1655 + u16 ctrl, ct1000, adv;
1656 + u16 ledctrl, ledover;
1657 +
1658 + pr_debug("yukon_init\n");
1659 + if (skge->autoneg == AUTONEG_ENABLE) {
1660 + u16 ectrl = skge_gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1661 +
1662 + ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1663 + PHY_M_EC_MAC_S_MSK);
1664 + ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1665 +
1666 + /* on PHY 88E1111 there is a change for downshift control */
1667 + if (hw->chip_id == CHIP_ID_YUKON_EC)
1668 + ectrl |= PHY_M_EC_M_DSC_2(0) | PHY_M_EC_DOWN_S_ENA;
1669 + else
1670 + ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1671 +
1672 + skge_gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1673 + }
1674 +
1675 + ctrl = skge_gm_phy_read(hw, port, PHY_MARV_CTRL);
1676 + if (skge->autoneg == AUTONEG_DISABLE)
1677 + ctrl &= ~PHY_CT_ANE;
1678 +
1679 + ctrl |= PHY_CT_RESET;
1680 + skge_gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1681 +
1682 + ctrl = 0;
1683 + ct1000 = 0;
1684 + adv = PHY_SEL_TYPE;
1685 +
1686 + if (skge->autoneg == AUTONEG_ENABLE) {
1687 + if (iscopper(hw)) {
1688 + if (skge->advertising & ADVERTISED_1000baseT_Full)
1689 + ct1000 |= PHY_M_1000C_AFD;
1690 + if (skge->advertising & ADVERTISED_1000baseT_Half)
1691 + ct1000 |= PHY_M_1000C_AHD;
1692 + if (skge->advertising & ADVERTISED_100baseT_Full)
1693 + adv |= PHY_M_AN_100_FD;
1694 + if (skge->advertising & ADVERTISED_100baseT_Half)
1695 + adv |= PHY_M_AN_100_HD;
1696 + if (skge->advertising & ADVERTISED_10baseT_Full)
1697 + adv |= PHY_M_AN_10_FD;
1698 + if (skge->advertising & ADVERTISED_10baseT_Half)
1699 + adv |= PHY_M_AN_10_HD;
1700 +
1701 + /* Set Flow-control capabilities */
1702 + switch (skge->flow_control) {
1703 + case FLOW_MODE_NONE:
1704 + adv |= PHY_B_P_NO_PAUSE;
1705 + break;
1706 + case FLOW_MODE_LOC_SEND:
1707 + adv |= PHY_B_P_ASYM_MD;
1708 + break;
1709 + case FLOW_MODE_SYMMETRIC:
1710 + adv |= PHY_B_P_SYM_MD;
1711 + break;
1712 + case FLOW_MODE_REM_SEND:
1713 + adv |= PHY_B_P_BOTH_MD;
1714 + break;
1715 + }
1716 + } else { /* special defines for FIBER (88E1011S only) */
1717 + adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1718 +
1719 + /* Set Flow-control capabilities */
1720 + switch (skge->flow_control) {
1721 + case FLOW_MODE_NONE:
1722 + adv |= PHY_M_P_NO_PAUSE_X;
1723 + break;
1724 + case FLOW_MODE_LOC_SEND:
1725 + adv |= PHY_M_P_ASYM_MD_X;
1726 + break;
1727 + case FLOW_MODE_SYMMETRIC:
1728 + adv |= PHY_M_P_SYM_MD_X;
1729 + break;
1730 + case FLOW_MODE_REM_SEND:
1731 + adv |= PHY_M_P_BOTH_MD_X;
1732 + break;
1733 + }
1734 + }
1735 + /* Restart Auto-negotiation */
1736 + ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1737 + } else {
1738 + /* forced speed/duplex settings */
1739 + ct1000 = PHY_M_1000C_MSE;
1740 +
1741 + if (skge->duplex == DUPLEX_FULL)
1742 + ctrl |= PHY_CT_DUP_MD;
1743 +
1744 + switch (skge->speed) {
1745 + case SPEED_1000:
1746 + ctrl |= PHY_CT_SP1000;
1747 + break;
1748 + case SPEED_100:
1749 + ctrl |= PHY_CT_SP100;
1750 + break;
1751 + }
1752 +
1753 + ctrl |= PHY_CT_RESET;
1754 + }
1755 +
1756 + if (hw->chip_id != CHIP_ID_YUKON_FE)
1757 + skge_gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1758 +
1759 + skge_gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1760 + skge_gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1761 +
1762 + /* Setup Phy LED's */
1763 + ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
1764 + ledover = 0;
1765 +
1766 + if (hw->chip_id == CHIP_ID_YUKON_FE) {
1767 + /* on 88E3082 these bits are at 11..9 (shifted left) */
1768 + ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
1769 +
1770 + skge_gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR,
1771 + ((skge_gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR)
1772 +
1773 + & ~PHY_M_FELP_LED1_MSK)
1774 + | PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL)));
1775 + } else {
1776 + /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
1777 + ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
1778 +
1779 + /* turn off the Rx LED (LED_RX) */
1780 + ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
1781 + }
1782 +
1783 + /* disable blink mode (LED_DUPLEX) on collisions */
1784 + ctrl |= PHY_M_LEDC_DP_CTRL;
1785 + skge_gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
1786 +
1787 + if (skge->autoneg == AUTONEG_DISABLE || skge->speed == SPEED_100) {
1788 + /* turn on 100 Mbps LED (LED_LINK100) */
1789 + ledover |= PHY_M_LED_MO_100(MO_LED_ON);
1790 + }
1791 +
1792 + if (ledover)
1793 + skge_gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
1794 +
1795 + /* Enable phy interrupt on autonegotiation complete (or link up) */
1796 + if (skge->autoneg == AUTONEG_ENABLE)
1797 + skge_gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
1798 + else
1799 + skge_gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1800 +}
1801 +
1802 +static void yukon_reset(struct skge_hw *hw, int port)
1803 +{
1804 + skge_gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1805 + skge_gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1806 + skge_gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1807 + skge_gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1808 + skge_gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1809 +
1810 + skge_gma_write16(hw, port, GM_RX_CTRL,
1811 + skge_gma_read16(hw, port, GM_RX_CTRL)
1812 + | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1813 +}
1814 +
1815 +static void yukon_mac_init(struct skge_hw *hw, int port)
1816 +{
1817 + struct skge_port *skge = netdev_priv(hw->dev[port]);
1818 + int i;
1819 + u32 reg;
1820 + const u8 *addr = hw->dev[port]->dev_addr;
1821 +
1822 + /* WA code for COMA mode -- set PHY reset */
1823 + if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1824 + chip_rev(hw) == CHIP_REV_YU_LITE_A3)
1825 + skge_write32(hw, B2_GP_IO,
1826 + (skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9));
1827 +
1828 + /* hard reset */
1829 + skge_write32(hw, SKGEMAC_REG(port, GPHY_CTRL), GPC_RST_SET);
1830 + skge_write32(hw, SKGEMAC_REG(port, GMAC_CTRL), GMC_RST_SET);
1831 +
1832 + /* WA code for COMA mode -- clear PHY reset */
1833 + if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1834 + chip_rev(hw) == CHIP_REV_YU_LITE_A3)
1835 + skge_write32(hw, B2_GP_IO,
1836 + (skge_read32(hw, B2_GP_IO) | GP_DIR_9)
1837 + & ~GP_IO_9);
1838 +
1839 + /* Set hardware config mode */
1840 + reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1841 + GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1842 + reg |= iscopper(hw) ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1843 +
1844 + /* Clear GMC reset */
1845 + skge_write32(hw, SKGEMAC_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1846 + skge_write32(hw, SKGEMAC_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1847 + skge_write32(hw, SKGEMAC_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
1848 + if (skge->autoneg == AUTONEG_DISABLE) {
1849 + reg = GM_GPCR_AU_ALL_DIS;
1850 + skge_gma_write16(hw, port, GM_GP_CTRL,
1851 + skge_gma_read16(hw, port, GM_GP_CTRL) | reg);
1852 +
1853 + switch (skge->speed) {
1854 + case SPEED_1000:
1855 + reg |= GM_GPCR_SPEED_1000;
1856 + /* fallthru */
1857 + case SPEED_100:
1858 + reg |= GM_GPCR_SPEED_100;
1859 + }
1860 +
1861 + if (skge->duplex == DUPLEX_FULL)
1862 + reg |= GM_GPCR_DUP_FULL;
1863 + } else
1864 + reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1865 + switch (skge->flow_control) {
1866 + case FLOW_MODE_NONE:
1867 + skge_write32(hw, SKGEMAC_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1868 + reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1869 + break;
1870 + case FLOW_MODE_LOC_SEND:
1871 + /* disable Rx flow-control */
1872 + reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1873 + }
1874 +
1875 + skge_gma_write16(hw, port, GM_GP_CTRL, reg);
1876 + skge_read16(hw, GMAC_IRQ_SRC);
1877 +
1878 + spin_lock_bh(&hw->phy_lock);
1879 + yukon_init(hw, port);
1880 + spin_unlock_bh(&hw->phy_lock);
1881 +
1882 + /* MIB clear */
1883 + reg = skge_gma_read16(hw, port, GM_PHY_ADDR);
1884 + skge_gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
1885 +
1886 + for (i = 0; i < GM_MIB_CNT_SIZE; i++)
1887 + skge_gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1888 + skge_gma_write16(hw, port, GM_PHY_ADDR, reg);
1889 +
1890 + /* transmit control */
1891 + skge_gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
1892 +
1893 + /* receive control reg: unicast + multicast + no FCS */
1894 + skge_gma_write16(hw, port, GM_RX_CTRL,
1895 + GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1896 +
1897 + /* transmit flow control */
1898 + skge_gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
1899 +
1900 + /* transmit parameter */
1901 + skge_gma_write16(hw, port, GM_TX_PARAM,
1902 + TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1903 + TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1904 + TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1905 +
1906 + /* serial mode register */
1907 + reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1908 + if (hw->dev[port]->mtu > 1500)
1909 + reg |= GM_SMOD_JUMBO_ENA;
1910 +
1911 + skge_gma_write16(hw, port, GM_SERIAL_MODE, reg);
1912 +
1913 + /* physical address: used for pause frames */
1914 + skge_gm_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
1915 + /* virtual address for data */
1916 + skge_gm_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
1917 +
1918 + /* enable interrupt mask for counter overflows */
1919 + skge_gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1920 + skge_gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1921 + skge_gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
1922 +
1923 + /* Initialize Mac Fifo */
1924 +
1925 + /* Configure Rx MAC FIFO */
1926 + skge_write16(hw, SKGEMAC_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
1927 + reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1928 + if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1929 + chip_rev(hw) == CHIP_REV_YU_LITE_A3)
1930 + reg &= ~GMF_RX_F_FL_ON;
1931 + skge_write8(hw, SKGEMAC_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1932 + skge_write16(hw, SKGEMAC_REG(port, RX_GMF_CTRL_T), reg);
1933 + skge_write16(hw, SKGEMAC_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
1934 +
1935 + /* Configure Tx MAC FIFO */
1936 + skge_write8(hw, SKGEMAC_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1937 + skge_write16(hw, SKGEMAC_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1938 +}
1939 +
1940 +static void yukon_stop(struct skge_port *skge)
1941 +{
1942 + struct skge_hw *hw = skge->hw;
1943 + int port = skge->port;
1944 +
1945 + if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1946 + chip_rev(hw) == CHIP_REV_YU_LITE_A3) {
1947 + skge_write32(hw, B2_GP_IO,
1948 + skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9);
1949 + }
1950 +
1951 + skge_gma_write16(hw, port, GM_GP_CTRL,
1952 + skge_gma_read16(hw, port, GM_GP_CTRL)
1953 + & ~(GM_GPCR_RX_ENA|GM_GPCR_RX_ENA));
1954 + skge_gma_read16(hw, port, GM_GP_CTRL);
1955 +
1956 + /* set GPHY Control reset */
1957 + skge_gma_write32(hw, port, GPHY_CTRL, GPC_RST_SET);
1958 + skge_gma_write32(hw, port, GMAC_CTRL, GMC_RST_SET);
1959 +}
1960 +
1961 +static void yukon_get_stats(struct skge_port *skge, u64 *data)
1962 +{
1963 + struct skge_hw *hw = skge->hw;
1964 + int port = skge->port;
1965 + int i;
1966 +
1967 + data[0] = (u64) skge_gma_read32(hw, port, GM_TXO_OK_HI) << 32
1968 + | skge_gma_read32(hw, port, GM_TXO_OK_LO);
1969 + data[1] = (u64) skge_gma_read32(hw, port, GM_RXO_OK_HI) << 32
1970 + | skge_gma_read32(hw, port, GM_RXO_OK_LO);
1971 +
1972 + for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1973 + data[i] = skge_gma_read32(hw, port,
1974 + skge_stats[i].gma_offset);
1975 +}
1976 +
1977 +static void yukon_mac_intr(struct skge_hw *hw, int port)
1978 +{
1979 + struct skge_port *skge = netdev_priv(hw->dev[port]);
1980 + u8 status = skge_read8(hw, SKGEMAC_REG(port, GMAC_IRQ_SRC));
1981 +
1982 + pr_debug("yukon_intr status %x\n", status);
1983 + if (status & GM_IS_RX_FF_OR) {
1984 + ++skge->net_stats.rx_fifo_errors;
1985 + skge_gma_write8(hw, port, RX_GMF_CTRL_T, GMF_CLI_RX_FO);
1986 + }
1987 + if (status & GM_IS_TX_FF_UR) {
1988 + ++skge->net_stats.tx_fifo_errors;
1989 + skge_gma_write8(hw, port, TX_GMF_CTRL_T, GMF_CLI_TX_FU);
1990 + }
1991 +
1992 +}
1993 +
1994 +static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1995 +{
1996 + if (hw->chip_id == CHIP_ID_YUKON_FE)
1997 + return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1998 +
1999 + switch(aux & PHY_M_PS_SPEED_MSK) {
2000 + case PHY_M_PS_SPEED_1000:
2001 + return SPEED_1000;
2002 + case PHY_M_PS_SPEED_100:
2003 + return SPEED_100;
2004 + default:
2005 + return SPEED_10;
2006 + }
2007 +}
2008 +
2009 +static void yukon_link_up(struct skge_port *skge)
2010 +{
2011 + struct skge_hw *hw = skge->hw;
2012 + int port = skge->port;
2013 + u16 reg;
2014 +
2015 + pr_debug("yukon_link_up\n");
2016 +
2017 + /* Enable Transmit FIFO Underrun */
2018 + skge_write8(hw, GMAC_IRQ_MSK, GMAC_DEF_MSK);
2019 +
2020 + reg = skge_gma_read16(hw, port, GM_GP_CTRL);
2021 + if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2022 + reg |= GM_GPCR_DUP_FULL;
2023 +
2024 + /* enable Rx/Tx */
2025 + reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2026 + skge_gma_write16(hw, port, GM_GP_CTRL, reg);
2027 +
2028 + skge_gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2029 + skge_link_up(skge);
2030 +}
2031 +
2032 +static void yukon_link_down(struct skge_port *skge)
2033 +{
2034 + struct skge_hw *hw = skge->hw;
2035 + int port = skge->port;
2036 +
2037 + pr_debug("yukon_link_down\n");
2038 + skge_gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2039 + skge_gm_phy_write(hw, port, GM_GP_CTRL,
2040 + skge_gm_phy_read(hw, port, GM_GP_CTRL)
2041 + & ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA));
2042 +
2043 + if (hw->chip_id != CHIP_ID_YUKON_FE &&
2044 + skge->flow_control == FLOW_MODE_REM_SEND) {
2045 + /* restore Asymmetric Pause bit */
2046 + skge_gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
2047 + skge_gm_phy_read(hw, port,
2048 + PHY_MARV_AUNE_ADV)
2049 + | PHY_M_AN_ASP);
2050 +
2051 + }
2052 +
2053 + yukon_reset(hw, port);
2054 + skge_link_down(skge);
2055 +
2056 + yukon_init(hw, port);
2057 +}
2058 +
2059 +static void yukon_phy_intr(struct skge_port *skge)
2060 +{
2061 + struct skge_hw *hw = skge->hw;
2062 + int port = skge->port;
2063 + const char *reason = NULL;
2064 + u16 istatus, phystat;
2065 +
2066 + istatus = skge_gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2067 + phystat = skge_gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2068 + pr_debug("yukon phy intr istat=%x phy_stat=%x\n", istatus, phystat);
2069 +
2070 + if (istatus & PHY_M_IS_AN_COMPL) {
2071 + if (skge_gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2072 + & PHY_M_AN_RF) {
2073 + reason = "remote fault";
2074 + goto failed;
2075 + }
2076 +
2077 + if (!(hw->chip_id == CHIP_ID_YUKON_FE || hw->chip_id == CHIP_ID_YUKON_EC)
2078 + && (skge_gm_phy_read(hw, port, PHY_MARV_1000T_STAT)
2079 + & PHY_B_1000S_MSF)) {
2080 + reason = "master/slave fault";
2081 + goto failed;
2082 + }
2083 +
2084 + if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2085 + reason = "speed/duplex";
2086 + goto failed;
2087 + }
2088 +
2089 + skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2090 + ? DUPLEX_FULL : DUPLEX_HALF;
2091 + skge->speed = yukon_speed(hw, phystat);
2092 +
2093 + /* Tx & Rx Pause Enabled bits are at 9..8 */
2094 + if (hw->chip_id == CHIP_ID_YUKON_XL)
2095 + phystat >>= 6;
2096 +
2097 + /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2098 + switch (phystat & PHY_M_PS_PAUSE_MSK) {
2099 + case PHY_M_PS_PAUSE_MSK:
2100 + skge->flow_control = FLOW_MODE_SYMMETRIC;
2101 + break;
2102 + case PHY_M_PS_RX_P_EN:
2103 + skge->flow_control = FLOW_MODE_REM_SEND;
2104 + break;
2105 + case PHY_M_PS_TX_P_EN:
2106 + skge->flow_control = FLOW_MODE_LOC_SEND;
2107 + break;
2108 + default:
2109 + skge->flow_control = FLOW_MODE_NONE;
2110 + }
2111 +
2112 + if (skge->flow_control == FLOW_MODE_NONE ||
2113 + (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2114 + skge_write8(hw, SKGEMAC_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2115 + else
2116 + skge_write8(hw, SKGEMAC_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2117 + yukon_link_up(skge);
2118 + return;
2119 + }
2120 +
2121 + if (istatus & PHY_M_IS_LSP_CHANGE)
2122 + skge->speed = yukon_speed(hw, phystat);
2123 +
2124 + if (istatus & PHY_M_IS_DUP_CHANGE)
2125 + skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2126 + if (istatus & PHY_M_IS_LST_CHANGE) {
2127 + if (phystat & PHY_M_PS_LINK_UP)
2128 + yukon_link_up(skge);
2129 + else
2130 + yukon_link_down(skge);
2131 + }
2132 + return;
2133 + failed:
2134 + printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2135 + skge->netdev->name, reason);
2136 +
2137 + /* XXX restart autonegotiation? */
2138 +}
2139 +
2140 +static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2141 +{
2142 + u32 end;
2143 +
2144 + start /= 8;
2145 + len /= 8;
2146 + end = start + len - 1;
2147 +
2148 + skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2149 + skge_write32(hw, RB_ADDR(q, RB_START), start);
2150 + skge_write32(hw, RB_ADDR(q, RB_WP), start);
2151 + skge_write32(hw, RB_ADDR(q, RB_RP), start);
2152 + skge_write32(hw, RB_ADDR(q, RB_END), end);
2153 +
2154 + if (q == Q_R1 || q == Q_R2) {
2155 + /* Set thresholds on receive queue's */
2156 + skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2157 + start + (2*len)/3);
2158 + skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2159 + start + (len/3));
2160 + } else {
2161 + /* Enable store & forward on Tx queue's because
2162 + * Tx FIFO is only 4K on Genesis and 1K on Yukon
2163 + */
2164 + skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2165 + }
2166 +
2167 + skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2168 +}
2169 +
2170 +/* Setup Bus Memory Interface */
2171 +static void skge_qset(struct skge_port *skge, u16 q,
2172 + const struct skge_element *e)
2173 +{
2174 + struct skge_hw *hw = skge->hw;
2175 + u32 watermark = 0x600;
2176 + u64 base = skge->dma + (e->desc - skge->mem);
2177 +
2178 + /* optimization to reduce window on 32bit/33mhz */
2179 + if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2180 + watermark /= 2;
2181 +
2182 + skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2183 + skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2184 + skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2185 + skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2186 +}
2187 +
2188 +static int skge_up(struct net_device *dev)
2189 +{
2190 + struct skge_port *skge = netdev_priv(dev);
2191 + struct skge_hw *hw = skge->hw;
2192 + int port = skge->port;
2193 + u32 chunk, ram_addr;
2194 + size_t rx_size, tx_size;
2195 + int err;
2196 +
2197 + if (netif_msg_ifup(skge))
2198 + printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2199 +
2200 + rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2201 + tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2202 + skge->mem_size = tx_size + rx_size;
2203 + skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2204 + if (!skge->mem)
2205 + return -ENOMEM;
2206 +
2207 + memset(skge->mem, 0, skge->mem_size);
2208 +
2209 + if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2210 + goto free_pci_mem;
2211 +
2212 + if (skge_rx_fill(skge))
2213 + goto free_rx_ring;
2214 +
2215 + if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2216 + skge->dma + rx_size)))
2217 + goto free_rx_ring;
2218 +
2219 + skge->tx_avail = skge->tx_ring.count - 1;
2220 +
2221 + /* Initialze MAC */
2222 + if (hw->chip_id == CHIP_ID_GENESIS)
2223 + genesis_mac_init(hw, port);
2224 + else
2225 + yukon_mac_init(hw, port);
2226 +
2227 + /* Configure RAMbuffers */
2228 + chunk = hw->ram_size / (isdualport(hw) ? 4 : 2);
2229 + ram_addr = hw->ram_offset + 2 * chunk * port;
2230 +
2231 + skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2232 + skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2233 +
2234 + BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2235 + skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2236 + skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2237 +
2238 + /* Start receiver BMU */
2239 + wmb();
2240 + skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2241 +
2242 + pr_debug("skge_up completed\n");
2243 + return 0;
2244 +
2245 + free_rx_ring:
2246 + skge_rx_clean(skge);
2247 + kfree(skge->rx_ring.start);
2248 + free_pci_mem:
2249 + pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2250 +
2251 + return err;
2252 +}
2253 +
2254 +static int skge_down(struct net_device *dev)
2255 +{
2256 + struct skge_port *skge = netdev_priv(dev);
2257 + struct skge_hw *hw = skge->hw;
2258 + int port = skge->port;
2259 +
2260 + if (netif_msg_ifdown(skge))
2261 + printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2262 +
2263 + netif_stop_queue(dev);
2264 +
2265 + del_timer_sync(&skge->led_blink);
2266 + del_timer_sync(&skge->link_check);
2267 +
2268 + /* Stop transmitter */
2269 + skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2270 + skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2271 + RB_RST_SET|RB_DIS_OP_MD);
2272 +
2273 + if (hw->chip_id == CHIP_ID_GENESIS)
2274 + genesis_stop(skge);
2275 + else
2276 + yukon_stop(skge);
2277 +
2278 + /* Disable Force Sync bit and Enable Alloc bit */
2279 + skge_write8(hw, SKGEMAC_REG(port, TXA_CTRL),
2280 + TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2281 +
2282 + /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2283 + skge_write32(hw, SKGEMAC_REG(port, TXA_ITI_INI), 0L);
2284 + skge_write32(hw, SKGEMAC_REG(port, TXA_LIM_INI), 0L);
2285 +
2286 + /* Reset PCI FIFO */
2287 + skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2288 + skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2289 +
2290 + /* Reset the RAM Buffer async Tx queue */
2291 + skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2292 + /* stop receiver */
2293 + skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2294 + skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2295 + RB_RST_SET|RB_DIS_OP_MD);
2296 + skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2297 +
2298 + if (hw->chip_id == CHIP_ID_GENESIS) {
2299 + skge_write8(hw, SKGEMAC_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2300 + skge_write8(hw, SKGEMAC_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2301 + skge_write8(hw, SKGEMAC_REG(port, TX_LED_CTRL), LED_STOP);
2302 + skge_write8(hw, SKGEMAC_REG(port, RX_LED_CTRL), LED_STOP);
2303 + } else {
2304 + skge_write8(hw, SKGEMAC_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2305 + skge_write8(hw, SKGEMAC_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2306 + }
2307 +
2308 + /* turn off led's */
2309 + skge_write16(hw, B0_LED, LED_STAT_OFF);
2310 +
2311 + skge_tx_clean(skge);
2312 + skge_rx_clean(skge);
2313 +
2314 + kfree(skge->rx_ring.start);
2315 + kfree(skge->tx_ring.start);
2316 + pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2317 + return 0;
2318 +}
2319 +
2320 +static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2321 +{
2322 + struct skge_port *skge = netdev_priv(dev);
2323 + struct skge_hw *hw = skge->hw;
2324 + struct skge_ring *ring = &skge->tx_ring;
2325 + struct skge_element *e;
2326 + struct skge_tx_desc *td;
2327 + int i;
2328 + u32 control, len;
2329 + u64 map;
2330 + unsigned long flags;
2331 +
2332 + skb = skb_padto(skb, ETH_ZLEN);
2333 + if (!skb)
2334 + return NETDEV_TX_OK;
2335 +
2336 + local_irq_save(flags);
2337 + if (!spin_trylock(&skge->tx_lock)) {
2338 + /* Collision - tell upper layer to requeue */
2339 + local_irq_restore(flags);
2340 + return NETDEV_TX_LOCKED;
2341 + }
2342 +
2343 + if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
2344 + netif_stop_queue(dev);
2345 + spin_unlock_irqrestore(&skge->tx_lock, flags);
2346 +
2347 + printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2348 + dev->name);
2349 + return NETDEV_TX_BUSY;
2350 + }
2351 +
2352 + e = ring->to_use;
2353 + td = e->desc;
2354 + e->skb = skb;
2355 + len = skb_headlen(skb);
2356 + map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2357 + pci_unmap_addr_set(e, mapaddr, map);
2358 + pci_unmap_len_set(e, maplen, len);
2359 +
2360 + td->dma_lo = map;
2361 + td->dma_hi = map >> 32;
2362 +
2363 + if (skb->ip_summed == CHECKSUM_HW) {
2364 + const struct iphdr *ip
2365 + = (const struct iphdr *) (skb->data + ETH_HLEN);
2366 + int offset = skb->h.raw - skb->data;
2367 +
2368 + /* This seems backwards, but it is what the sk98lin
2369 + * does. Looks like hardware is wrong?
2370 + */
2371 + if (ip->protocol == IPPROTO_UDP
2372 + && chip_rev(hw) == 0 && hw->chip_id == CHIP_ID_YUKON)
2373 + control = BMU_TCP_CHECK;
2374 + else
2375 + control = BMU_UDP_CHECK;
2376 +
2377 + td->csum_offs = 0;
2378 + td->csum_start = offset;
2379 + td->csum_write = offset + skb->csum;
2380 + } else
2381 + control = BMU_CHECK;
2382 +
2383 + if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2384 + control |= BMU_EOF| BMU_IRQ_EOF;
2385 + else {
2386 + struct skge_tx_desc *tf = td;
2387 +
2388 + control |= BMU_STFWD;
2389 + for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2390 + skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2391 +
2392 + map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2393 + frag->size, PCI_DMA_TODEVICE);
2394 +
2395 + e = e->next;
2396 + e->skb = NULL;
2397 + tf = e->desc;
2398 + tf->dma_lo = map;
2399 + tf->dma_hi = (u64) map >> 32;
2400 + pci_unmap_addr_set(e, mapaddr, map);
2401 + pci_unmap_len_set(e, maplen, frag->size);
2402 +
2403 + tf->control = BMU_OWN | BMU_SW | control | frag->size;
2404 + }
2405 + tf->control |= BMU_EOF | BMU_IRQ_EOF;
2406 + }
2407 + /* Make sure all the descriptors written */
2408 + wmb();
2409 + td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2410 + wmb();
2411 +
2412 + skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2413 +
2414 + if (netif_msg_tx_queued(skge))
2415 + printk(KERN_DEBUG "%s: tx queued, slot %d, len %d\n",
2416 + dev->name, e - ring->start, skb->len);
2417 +
2418 + ring->to_use = e->next;
2419 + skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2420 + if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2421 + pr_debug("%s: transmit queue full\n", dev->name);
2422 + netif_stop_queue(dev);
2423 + }
2424 +
2425 + dev->trans_start = jiffies;
2426 + spin_unlock_irqrestore(&skge->tx_lock, flags);
2427 +
2428 + return NETDEV_TX_OK;
2429 +}
2430 +
2431 +static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2432 +{
2433 + if (e->skb) {
2434 + pci_unmap_single(hw->pdev,
2435 + pci_unmap_addr(e, mapaddr),
2436 + pci_unmap_len(e, maplen),
2437 + PCI_DMA_TODEVICE);
2438 + dev_kfree_skb_any(e->skb);
2439 + e->skb = NULL;
2440 + } else {
2441 + pci_unmap_page(hw->pdev,
2442 + pci_unmap_addr(e, mapaddr),
2443 + pci_unmap_len(e, maplen),
2444 + PCI_DMA_TODEVICE);
2445 + }
2446 +}
2447 +
2448 +static void skge_tx_clean(struct skge_port *skge)
2449 +{
2450 + struct skge_ring *ring = &skge->tx_ring;
2451 + struct skge_element *e;
2452 + unsigned long flags;
2453 +
2454 + spin_lock_irqsave(&skge->tx_lock, flags);
2455 + for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2456 + ++skge->tx_avail;
2457 + skge_tx_free(skge->hw, e);
2458 + }
2459 + ring->to_clean = e;
2460 + spin_unlock_irqrestore(&skge->tx_lock, flags);
2461 +}
2462 +
2463 +static void skge_tx_timeout(struct net_device *dev)
2464 +{
2465 + struct skge_port *skge = netdev_priv(dev);
2466 +
2467 + if (netif_msg_timer(skge))
2468 + printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2469 +
2470 + skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2471 + skge_tx_clean(skge);
2472 +}
2473 +
2474 +static int skge_change_mtu(struct net_device *dev, int new_mtu)
2475 +{
2476 + int err = 0;
2477 +
2478 + if(new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2479 + return -EINVAL;
2480 +
2481 + dev->mtu = new_mtu;
2482 +
2483 + if (netif_running(dev)) {
2484 + skge_down(dev);
2485 + skge_up(dev);
2486 + }
2487 +
2488 + return err;
2489 +}
2490 +
2491 +static void genesis_set_multicast(struct net_device *dev)
2492 +{
2493 + struct skge_port *skge = netdev_priv(dev);
2494 + struct skge_hw *hw = skge->hw;
2495 + int port = skge->port;
2496 + int i, count = dev->mc_count;
2497 + struct dev_mc_list *list = dev->mc_list;
2498 + u32 mode;
2499 + u8 filter[8];
2500 +
2501 + mode = skge_xm_read32(hw, port, XM_MODE);
2502 + mode |= XM_MD_ENA_HASH;
2503 + if (dev->flags & IFF_PROMISC)
2504 + mode |= XM_MD_ENA_PROM;
2505 + else
2506 + mode &= ~XM_MD_ENA_PROM;
2507 +
2508 + if (dev->flags & IFF_ALLMULTI)
2509 + memset(filter, 0xff, sizeof(filter));
2510 + else {
2511 + memset(filter, 0, sizeof(filter));
2512 + for(i = 0; list && i < count; i++, list = list->next) {
2513 + u32 crc = crc32_le(~0, list->dmi_addr, ETH_ALEN);
2514 + u8 bit = 63 - (crc & 63);
2515 +
2516 + filter[bit/8] |= 1 << (bit%8);
2517 + }
2518 + }
2519 +
2520 + skge_xm_outhash(hw, port, XM_HSM, filter);
2521 +
2522 + skge_xm_write32(hw, port, XM_MODE, mode);
2523 +}
2524 +
2525 +static void yukon_set_multicast(struct net_device *dev)
2526 +{
2527 + struct skge_port *skge = netdev_priv(dev);
2528 + struct skge_hw *hw = skge->hw;
2529 + int port = skge->port;
2530 + struct dev_mc_list *list = dev->mc_list;
2531 + u16 reg;
2532 + u8 filter[8];
2533 +
2534 + memset(filter, 0, sizeof(filter));
2535 +
2536 + reg = skge_gma_read16(hw, port, GM_RX_CTRL);
2537 + reg |= GM_RXCR_UCF_ENA;
2538 +
2539 + if (dev->flags & IFF_PROMISC) /* promiscious */
2540 + reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2541 + else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2542 + memset(filter, 0xff, sizeof(filter));
2543 + else if (dev->mc_count == 0) /* no multicast */
2544 + reg &= ~GM_RXCR_MCF_ENA;
2545 + else {
2546 + int i;
2547 + reg |= GM_RXCR_MCF_ENA;
2548 +
2549 + for(i = 0; list && i < dev->mc_count; i++, list = list->next) {
2550 + u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2551 + filter[bit/8] |= 1 << (bit%8);
2552 + }
2553 + }
2554 +
2555 +
2556 + skge_gma_write16(hw, port, GM_MC_ADDR_H1,
2557 + (u16)filter[0] | ((u16)filter[1] << 8));
2558 + skge_gma_write16(hw, port, GM_MC_ADDR_H2,
2559 + (u16)filter[2] | ((u16)filter[3] << 8));
2560 + skge_gma_write16(hw, port, GM_MC_ADDR_H3,
2561 + (u16)filter[4] | ((u16)filter[5] << 8));
2562 + skge_gma_write16(hw, port, GM_MC_ADDR_H4,
2563 + (u16)filter[6] | ((u16)filter[7] << 8));
2564 +
2565 + skge_gma_write16(hw, port, GM_RX_CTRL, reg);
2566 +}
2567 +
2568 +static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2569 +{
2570 + if (hw->chip_id == CHIP_ID_GENESIS)
2571 + return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2572 + else
2573 + return (status & GMR_FS_ANY_ERR) ||
2574 + (status & GMR_FS_RX_OK) == 0;
2575 +}
2576 +
2577 +static void skge_rx_error(struct skge_port *skge, int slot,
2578 + u32 control, u32 status)
2579 +{
2580 + if (netif_msg_rx_err(skge))
2581 + printk(KERN_DEBUG PFX "%s: rx err, slot %d control 0x%x status 0x%x\n",
2582 + skge->netdev->name, slot, control, status);
2583 +
2584 + if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)
2585 + || (control & BMU_BBC) > skge->netdev->mtu + VLAN_ETH_HLEN)
2586 + skge->net_stats.rx_length_errors++;
2587 + else {
2588 + if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2589 + if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2590 + skge->net_stats.rx_length_errors++;
2591 + if (status & XMR_FS_FRA_ERR)
2592 + skge->net_stats.rx_frame_errors++;
2593 + if (status & XMR_FS_FCS_ERR)
2594 + skge->net_stats.rx_crc_errors++;
2595 + } else {
2596 + if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2597 + skge->net_stats.rx_length_errors++;
2598 + if (status & GMR_FS_FRAGMENT)
2599 + skge->net_stats.rx_frame_errors++;
2600 + if (status & GMR_FS_CRC_ERR)
2601 + skge->net_stats.rx_crc_errors++;
2602 + }
2603 + }
2604 +}
2605 +
2606 +static int skge_poll(struct net_device *dev, int *budget)
2607 +{
2608 + struct skge_port *skge = netdev_priv(dev);
2609 + struct skge_hw *hw = skge->hw;
2610 + struct skge_ring *ring = &skge->rx_ring;
2611 + struct skge_element *e;
2612 + unsigned int to_do = min(dev->quota, *budget);
2613 + unsigned int work_done = 0;
2614 + int done;
2615 + static const u32 irqmask[] = { IS_PORT_1, IS_PORT_2 };
2616 +
2617 + for (e = ring->to_clean; e != ring->to_use && work_done < to_do;
2618 + e = e->next) {
2619 + struct skge_rx_desc *rd = e->desc;
2620 + struct sk_buff *skb = e->skb;
2621 + u32 control, len, status;
2622 +
2623 + rmb();
2624 + control = rd->control;
2625 + if (control & BMU_OWN)
2626 + break;
2627 +
2628 + len = control & BMU_BBC;
2629 + e->skb = NULL;
2630 +
2631 + pci_unmap_single(hw->pdev,
2632 + pci_unmap_addr(e, mapaddr),
2633 + pci_unmap_len(e, maplen),
2634 + PCI_DMA_FROMDEVICE);
2635 +
2636 + status = rd->status;
2637 + if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)
2638 + || len > dev->mtu + VLAN_ETH_HLEN
2639 + || bad_phy_status(hw, status)) {
2640 + skge_rx_error(skge, e - ring->start, control, status);
2641 + dev_kfree_skb(skb);
2642 + continue;
2643 + }
2644 +
2645 + if (netif_msg_rx_status(skge))
2646 + printk(KERN_DEBUG PFX "%s: rx slot %d status 0x%x len %d\n",
2647 + dev->name, e - ring->start, rd->status, len);
2648 +
2649 + skb_put(skb, len);
2650 + skb->protocol = eth_type_trans(skb, dev);
2651 +
2652 + if (skge->rx_csum) {
2653 + skb->csum = le16_to_cpu(rd->csum2);
2654 + skb->ip_summed = CHECKSUM_HW;
2655 + }
2656 +
2657 + dev->last_rx = jiffies;
2658 + netif_receive_skb(skb);
2659 +
2660 + ++work_done;
2661 + }
2662 + ring->to_clean = e;
2663 +
2664 + *budget -= work_done;
2665 + dev->quota -= work_done;
2666 + done = work_done < to_do;
2667 +
2668 + if (skge_rx_fill(skge))
2669 + done = 0;
2670 +
2671 + /* restart receiver */
2672 + wmb();
2673 + skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR),
2674 + CSR_START | CSR_IRQ_CL_F);
2675 +
2676 + if (done) {
2677 + local_irq_disable();
2678 + hw->intr_mask |= irqmask[skge->port];
2679 + /* Order is important since data can get interrupted */
2680 + skge_write32(hw, B0_IMSK, hw->intr_mask);
2681 + __netif_rx_complete(dev);
2682 + local_irq_enable();
2683 + }
2684 +
2685 + return !done;
2686 +}
2687 +
2688 +static inline void skge_tx_intr(struct net_device *dev)
2689 +{
2690 + struct skge_port *skge = netdev_priv(dev);
2691 + struct skge_hw *hw = skge->hw;
2692 + struct skge_ring *ring = &skge->tx_ring;
2693 + struct skge_element *e;
2694 +
2695 + spin_lock(&skge->tx_lock);
2696 + for(e = ring->to_clean; e != ring->to_use; e = e->next) {
2697 + struct skge_tx_desc *td = e->desc;
2698 + u32 control;
2699 +
2700 + rmb();
2701 + control = td->control;
2702 + if (control & BMU_OWN)
2703 + break;
2704 +
2705 + if (unlikely(netif_msg_tx_done(skge)))
2706 + printk(KERN_DEBUG PFX "%s: tx done slot %d status 0x%x\n",
2707 + dev->name, e - ring->start, td->status);
2708 +
2709 + skge_tx_free(hw, e);
2710 + e->skb = NULL;
2711 + ++skge->tx_avail;
2712 + }
2713 + ring->to_clean = e;
2714 + skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2715 +
2716 + if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2717 + netif_wake_queue(dev);
2718 +
2719 + spin_unlock(&skge->tx_lock);
2720 +}
2721 +
2722 +static void skge_mac_parity(struct skge_hw *hw, int port)
2723 +{
2724 + printk(KERN_ERR PFX "%s: mac data parity error\n",
2725 + hw->dev[port] ? hw->dev[port]->name
2726 + : (port == 0 ? "(port A)": "(port B"));
2727 +
2728 + if (hw->chip_id == CHIP_ID_GENESIS)
2729 + skge_write16(hw, SKGEMAC_REG(port, TX_MFF_CTRL1),
2730 + MFF_CLR_PERR);
2731 + else
2732 + /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
2733 + skge_write8(hw, SKGEMAC_REG(port, TX_GMF_CTRL_T),
2734 + (hw->chip_id == CHIP_ID_YUKON && chip_rev(hw) == 0)
2735 + ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2736 +}
2737 +
2738 +static void skge_pci_clear(struct skge_hw *hw)
2739 +{
2740 + u16 status;
2741 +
2742 + status = skge_read16(hw, SKGEPCI_REG(PCI_STATUS));
2743 + skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2744 + skge_write16(hw, SKGEPCI_REG(PCI_STATUS),
2745 + status | PCI_STATUS_ERROR_BITS);
2746 + skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2747 +}
2748 +
2749 +static void skge_mac_intr(struct skge_hw *hw, int port)
2750 +{
2751 + if (hw->chip_id == CHIP_ID_GENESIS)
2752 + genesis_mac_intr(hw, port);
2753 + else
2754 + yukon_mac_intr(hw, port);
2755 +}
2756 +
2757 +/* Handle device specific framing and timeout interrupts */
2758 +static void skge_error_irq(struct skge_hw *hw)
2759 +{
2760 + u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2761 +
2762 + if (hw->chip_id == CHIP_ID_GENESIS) {
2763 + /* clear xmac errors */
2764 + if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
2765 + skge_write16(hw, SKGEMAC_REG(0, RX_MFF_CTRL1), MFF_CLR_INSTAT);
2766 + if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
2767 + skge_write16(hw, SKGEMAC_REG(0, RX_MFF_CTRL2), MFF_CLR_INSTAT);
2768 + } else {
2769 + /* Timestamp (unused) overflow */
2770 + if (hwstatus & IS_IRQ_TIST_OV)
2771 + skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2772 +
2773 + if (hwstatus & IS_IRQ_SENSOR) {
2774 + /* no sensors on 32-bit Yukon */
2775 + if (!(skge_read16(hw, B0_CTST) & CS_BUS_SLOT_SZ)) {
2776 + printk(KERN_ERR PFX "ignoring bogus sensor interrups\n");
2777 + skge_write32(hw, B0_HWE_IMSK,
2778 + IS_ERR_MSK & ~IS_IRQ_SENSOR);
2779 + } else
2780 + printk(KERN_WARNING PFX "sensor interrupt\n");
2781 + }
2782 +
2783 +
2784 + }
2785 +
2786 + if (hwstatus & IS_RAM_RD_PAR) {
2787 + printk(KERN_ERR PFX "Ram read data parity error\n");
2788 + skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2789 + }
2790 +
2791 + if (hwstatus & IS_RAM_WR_PAR) {
2792 + printk(KERN_ERR PFX "Ram write data parity error\n");
2793 + skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2794 + }
2795 +
2796 + if (hwstatus & IS_M1_PAR_ERR)
2797 + skge_mac_parity(hw, 0);
2798 +
2799 + if (hwstatus & IS_M2_PAR_ERR)
2800 + skge_mac_parity(hw, 1);
2801 +
2802 + if (hwstatus & IS_R1_PAR_ERR)
2803 + skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2804 +
2805 + if (hwstatus & IS_R2_PAR_ERR)
2806 + skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2807 +
2808 + if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2809 + printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
2810 + hwstatus);
2811 +
2812 + skge_pci_clear(hw);
2813 +
2814 + hwstatus = skge_read32(hw, B0_HWE_ISRC);
2815 + if (hwstatus & IS_IRQ_STAT) {
2816 + printk(KERN_WARNING PFX "IRQ status %x: still set ignoring hardware errors\n",
2817 + hwstatus);
2818 + hw->intr_mask &= ~IS_HW_ERR;
2819 + }
2820 + }
2821 +}
2822 +
2823 +/*
2824 + * Interrrupt from PHY are handled in tasklet (soft irq)
2825 + * because accessing phy registers requires spin wait which might
2826 + * cause excess interrupt latency.
2827 + */
2828 +static void skge_extirq(unsigned long data)
2829 +{
2830 + struct skge_hw *hw = (struct skge_hw *) data;
2831 + int port;
2832 +
2833 + spin_lock(&hw->phy_lock);
2834 + for (port = 0; port < 2; port++) {
2835 + struct net_device *dev = hw->dev[port];
2836 +
2837 + if (dev && netif_running(dev)) {
2838 + struct skge_port *skge = netdev_priv(dev);
2839 +
2840 + if (hw->chip_id != CHIP_ID_GENESIS)
2841 + yukon_phy_intr(skge);
2842 + else if (hw->phy_type == SK_PHY_BCOM)
2843 + genesis_bcom_intr(skge);
2844 + }
2845 + }
2846 + spin_unlock(&hw->phy_lock);
2847 +
2848 + local_irq_disable();
2849 + hw->intr_mask |= IS_EXT_REG;
2850 + skge_write32(hw, B0_IMSK, hw->intr_mask);
2851 + local_irq_enable();
2852 +}
2853 +
2854 +static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2855 +{
2856 + struct skge_hw *hw = dev_id;
2857 + u32 status = skge_read32(hw, B0_SP_ISRC);
2858 +
2859 + if (status == 0 || status == ~0) /* hotplug or shared irq */
2860 + return IRQ_NONE;
2861 +
2862 + status &= hw->intr_mask;
2863 +
2864 + if ((status & IS_R1_F) && netif_rx_schedule_prep(hw->dev[0])) {
2865 + status &= ~IS_R1_F;
2866 + hw->intr_mask &= ~IS_R1_F;
2867 + skge_write32(hw, B0_IMSK, hw->intr_mask);
2868 + __netif_rx_schedule(hw->dev[0]);
2869 + }
2870 +
2871 + if ((status & IS_R2_F) && netif_rx_schedule_prep(hw->dev[1])) {
2872 + status &= ~IS_R2_F;
2873 + hw->intr_mask &= ~IS_R2_F;
2874 + skge_write32(hw, B0_IMSK, hw->intr_mask);
2875 + __netif_rx_schedule(hw->dev[1]);
2876 + }
2877 +
2878 + if (status & IS_XA1_F)
2879 + skge_tx_intr(hw->dev[0]);
2880 +
2881 + if (status & IS_XA2_F)
2882 + skge_tx_intr(hw->dev[1]);
2883 +
2884 + if (status & IS_MAC1)
2885 + skge_mac_intr(hw, 0);
2886 +
2887 + if (status & IS_MAC2)
2888 + skge_mac_intr(hw, 1);
2889 +
2890 + if (status & IS_HW_ERR)
2891 + skge_error_irq(hw);
2892 +
2893 + if (status & IS_EXT_REG) {
2894 + hw->intr_mask &= ~IS_EXT_REG;
2895 + tasklet_schedule(&hw->ext_tasklet);
2896 + }
2897 +
2898 + if (status)
2899 + skge_write32(hw, B0_IMSK, hw->intr_mask);
2900 +
2901 + return IRQ_HANDLED;
2902 +}
2903 +
2904 +#ifdef CONFIG_NET_POLL_CONTROLLER
2905 +static void skge_netpoll(struct net_device *dev)
2906 +{
2907 + struct skge_port *skge = netdev_priv(dev);
2908 +
2909 + disable_irq(dev->irq);
2910 + skge_intr(dev->irq, skge->hw, NULL);
2911 + enable_irq(dev->irq);
2912 +}
2913 +#endif
2914 +
2915 +static int skge_set_mac_address(struct net_device *dev, void *p)
2916 +{
2917 + struct skge_port *skge = netdev_priv(dev);
2918 + struct sockaddr *addr = p;
2919 + int err = 0;
2920 +
2921 + if (!is_valid_ether_addr(addr->sa_data))
2922 + return -EADDRNOTAVAIL;
2923 +
2924 + skge_down(dev);
2925 + memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2926 + memcpy_toio(skge->hw->regs + B2_MAC_1 + skge->port*8,
2927 + dev->dev_addr, ETH_ALEN);
2928 + memcpy_toio(skge->hw->regs + B2_MAC_2 + skge->port*8,
2929 + dev->dev_addr, ETH_ALEN);
2930 + if (dev->flags & IFF_UP)
2931 + err = skge_up(dev);
2932 + return err;
2933 +}
2934 +
2935 +static const struct {
2936 + u8 id;
2937 + const char *name;
2938 +} skge_chips[] = {
2939 + { CHIP_ID_GENESIS, "Genesis" },
2940 + { CHIP_ID_YUKON, "Yukon" },
2941 + { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2942 + { CHIP_ID_YUKON_LP, "Yukon-LP"},
2943 + { CHIP_ID_YUKON_XL, "Yukon-2 XL"},
2944 + { CHIP_ID_YUKON_EC, "YUKON-2 EC"},
2945 + { CHIP_ID_YUKON_FE, "YUKON-2 FE"},
2946 +};
2947 +
2948 +static const char *skge_board_name(const struct skge_hw *hw)
2949 +{
2950 + int i;
2951 + static char buf[16];
2952 +
2953 + for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2954 + if (skge_chips[i].id == hw->chip_id)
2955 + return skge_chips[i].name;
2956 +
2957 + snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2958 + return buf;
2959 +}
2960 +
2961 +
2962 +/*
2963 + * Setup the board data structure, but don't bring up
2964 + * the port(s)
2965 + */
2966 +static int skge_reset(struct skge_hw *hw)
2967 +{
2968 + u16 ctst;
2969 + u8 t8;
2970 + int i, ports;
2971 +
2972 + ctst = skge_read16(hw, B0_CTST);
2973 +
2974 + /* do a SW reset */
2975 + skge_write8(hw, B0_CTST, CS_RST_SET);
2976 + skge_write8(hw, B0_CTST, CS_RST_CLR);
2977 +
2978 + /* clear PCI errors, if any */
2979 + skge_pci_clear(hw);
2980 +
2981 + skge_write8(hw, B0_CTST, CS_MRST_CLR);
2982 +
2983 + /* restore CLK_RUN bits (for Yukon-Lite) */
2984 + skge_write16(hw, B0_CTST,
2985 + ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
2986 +
2987 + hw->chip_id = skge_read8(hw, B2_CHIP_ID);
2988 + hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
2989 + hw->pmd_type = skge_read8(hw, B2_PMD_TYP);
2990 +
2991 + switch(hw->chip_id) {
2992 + case CHIP_ID_GENESIS:
2993 + switch (hw->phy_type) {
2994 + case SK_PHY_XMAC:
2995 + hw->phy_addr = PHY_ADDR_XMAC;
2996 + break;
2997 + case SK_PHY_BCOM:
2998 + hw->phy_addr = PHY_ADDR_BCOM;
2999 + break;
3000 + default:
3001 + printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
3002 + pci_name(hw->pdev), hw->phy_type);
3003 + return -EOPNOTSUPP;
3004 + }
3005 + break;
3006 +
3007 + case CHIP_ID_YUKON:
3008 + case CHIP_ID_YUKON_LITE:
3009 + case CHIP_ID_YUKON_LP:
3010 + if (hw->phy_type < SK_PHY_MARV_COPPER && hw->pmd_type != 'S')
3011 + hw->phy_type = SK_PHY_MARV_COPPER;
3012 +
3013 + hw->phy_addr = PHY_ADDR_MARV;
3014 + if (!iscopper(hw))
3015 + hw->phy_type = SK_PHY_MARV_FIBER;
3016 +
3017 + break;
3018 +
3019 + default:
3020 + printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
3021 + pci_name(hw->pdev), hw->chip_id);
3022 + return -EOPNOTSUPP;
3023 + }
3024 +
3025 + hw->mac_cfg = skge_read8(hw, B2_MAC_CFG);
3026 + ports = isdualport(hw) ? 2 : 1;
3027 +
3028 + /* read the adapters RAM size */
3029 + t8 = skge_read8(hw, B2_E_0);
3030 + if (hw->chip_id == CHIP_ID_GENESIS) {
3031 + if (t8 == 3) {
3032 + /* special case: 4 x 64k x 36, offset = 0x80000 */
3033 + hw->ram_size = 0x100000;
3034 + hw->ram_offset = 0x80000;
3035 + } else
3036 + hw->ram_size = t8 * 512;
3037 + }
3038 + else if (t8 == 0)
3039 + hw->ram_size = 0x20000;
3040 + else
3041 + hw->ram_size = t8 * 4096;
3042 +
3043 + if (hw->chip_id == CHIP_ID_GENESIS)
3044 + genesis_init(hw);
3045 + else {
3046 + /* switch power to VCC (WA for VAUX problem) */
3047 + skge_write8(hw, B0_POWER_CTRL,
3048 + PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3049 + for (i = 0; i < ports; i++) {
3050 + skge_write16(hw, SKGEMAC_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3051 + skge_write16(hw, SKGEMAC_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3052 + }
3053 + }
3054 +
3055 + /* turn off hardware timer (unused) */
3056 + skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3057 + skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3058 + skge_write8(hw, B0_LED, LED_STAT_ON);
3059 +
3060 + /* enable the Tx Arbiters */
3061 + for (i = 0; i < ports; i++)
3062 + skge_write8(hw, SKGEMAC_REG(i, TXA_CTRL), TXA_ENA_ARB);
3063 +
3064 + /* Initialize ram interface */
3065 + skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3066 +
3067 + skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3068 + skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3069 + skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3070 + skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3071 + skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3072 + skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3073 + skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3074 + skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3075 + skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3076 + skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3077 + skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3078 + skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3079 +
3080 + skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3081 +
3082 + /* Set interrupt moderation for Transmit only
3083 + * Receive interrupts avoided by NAPI
3084 + */
3085 + skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3086 + skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3087 + skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3088 +
3089 + hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1;
3090 + if (isdualport(hw))
3091 + hw->intr_mask |= IS_PORT_2;
3092 + skge_write32(hw, B0_IMSK, hw->intr_mask);
3093 +
3094 + if (hw->chip_id != CHIP_ID_GENESIS)
3095 + skge_write8(hw, GMAC_IRQ_MSK, 0);
3096 +
3097 + spin_lock_bh(&hw->phy_lock);
3098 + for (i = 0; i < ports; i++) {
3099 + if (hw->chip_id == CHIP_ID_GENESIS)
3100 + genesis_reset(hw, i);
3101 + else
3102 + yukon_reset(hw, i);
3103 + }
3104 + spin_unlock_bh(&hw->phy_lock);
3105 +
3106 + return 0;
3107 +}
3108 +
3109 +/* Initialize network device */
3110 +static struct net_device *skge_devinit(struct skge_hw *hw, int port)
3111 +{
3112 + struct skge_port *skge;
3113 + struct net_device *dev = alloc_etherdev(sizeof(*skge));
3114 +
3115 + if (!dev) {
3116 + printk(KERN_ERR "skge etherdev alloc failed");
3117 + return NULL;
3118 + }
3119 +
3120 + SET_MODULE_OWNER(dev);
3121 + SET_NETDEV_DEV(dev, &hw->pdev->dev);
3122 + dev->open = skge_up;
3123 + dev->stop = skge_down;
3124 + dev->hard_start_xmit = skge_xmit_frame;
3125 + dev->get_stats = skge_get_stats;
3126 + if (hw->chip_id == CHIP_ID_GENESIS)
3127 + dev->set_multicast_list = genesis_set_multicast;
3128 + else
3129 + dev->set_multicast_list = yukon_set_multicast;
3130 +
3131 + dev->set_mac_address = skge_set_mac_address;
3132 + dev->change_mtu = skge_change_mtu;
3133 + SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3134 + dev->tx_timeout = skge_tx_timeout;
3135 + dev->watchdog_timeo = TX_WATCHDOG;
3136 + dev->poll = skge_poll;
3137 + dev->weight = NAPI_WEIGHT;
3138 +#ifdef CONFIG_NET_POLL_CONTROLLER
3139 + dev->poll_controller = skge_netpoll;
3140 +#endif
3141 + dev->irq = hw->pdev->irq;
3142 + dev->features = NETIF_F_LLTX;
3143 +
3144 + skge = netdev_priv(dev);
3145 + skge->netdev = dev;
3146 + skge->hw = hw;
3147 + skge->msg_enable = netif_msg_init(debug, default_msg);
3148 + skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3149 + skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3150 +
3151 + /* Auto speed and flow control */
3152 + skge->autoneg = AUTONEG_ENABLE;
3153 + skge->flow_control = FLOW_MODE_SYMMETRIC;
3154 + skge->duplex = -1;
3155 + skge->speed = -1;
3156 + skge->advertising = skge_modes(hw);
3157 +
3158 + hw->dev[port] = dev;
3159 +
3160 + skge->port = port;
3161 +
3162 + spin_lock_init(&skge->tx_lock);
3163 +
3164 + init_timer(&skge->link_check);
3165 + skge->link_check.function = skge_link_timer;
3166 + skge->link_check.data = (unsigned long) skge;
3167 +
3168 + init_timer(&skge->led_blink);
3169 + skge->led_blink.function = skge_blink_timer;
3170 + skge->led_blink.data = (unsigned long) skge;
3171 +
3172 + if (hw->chip_id != CHIP_ID_GENESIS) {
3173 + dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3174 + skge->rx_csum = 1;
3175 + }
3176 +
3177 + /* read the mac address */
3178 + memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3179 +
3180 + /* device is off until link detection */
3181 + netif_carrier_off(dev);
3182 + netif_stop_queue(dev);
3183 +
3184 + return dev;
3185 +}
3186 +
3187 +static void __devinit skge_show_addr(struct net_device *dev)
3188 +{
3189 + const struct skge_port *skge = netdev_priv(dev);
3190 +
3191 + if (netif_msg_probe(skge))
3192 + printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3193 + dev->name,
3194 + dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3195 + dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3196 +}
3197 +
3198 +static int __devinit skge_probe(struct pci_dev *pdev,
3199 + const struct pci_device_id *ent)
3200 +{
3201 + struct net_device *dev, *dev1;
3202 + struct skge_hw *hw;
3203 + int err, using_dac = 0;
3204 +
3205 + if ((err = pci_enable_device(pdev))) {
3206 + printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3207 + pci_name(pdev));
3208 + goto err_out;
3209 + }
3210 +
3211 + if ((err = pci_request_regions(pdev, DRV_NAME))) {
3212 + printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3213 + pci_name(pdev));
3214 + goto err_out_disable_pdev;
3215 + }
3216 +
3217 + pci_set_master(pdev);
3218 +
3219 + if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)))
3220 + using_dac = 1;
3221 + else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3222 + printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3223 + pci_name(pdev));
3224 + goto err_out_free_regions;
3225 + }
3226 +
3227 +#ifdef __BIG_ENDIAN
3228 + /* byte swap decriptors in hardware */
3229 + {
3230 + u32 reg;
3231 +
3232 + pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3233 + reg |= PCI_REV_DESC;
3234 + pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3235 + }
3236 +#endif
3237 +
3238 + err = -ENOMEM;
3239 + hw = kmalloc(sizeof(*hw), GFP_KERNEL);
3240 + if (!hw) {
3241 + printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3242 + pci_name(pdev));
3243 + goto err_out_free_regions;
3244 + }
3245 +
3246 + memset(hw, 0, sizeof(*hw));
3247 + hw->pdev = pdev;
3248 + spin_lock_init(&hw->phy_lock);
3249 + tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3250 +
3251 + hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3252 + if (!hw->regs) {
3253 + printk(KERN_ERR PFX "%s: cannot map device registers\n",
3254 + pci_name(pdev));
3255 + goto err_out_free_hw;
3256 + }
3257 +
3258 + if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
3259 + printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3260 + pci_name(pdev), pdev->irq);
3261 + goto err_out_iounmap;
3262 + }
3263 + pci_set_drvdata(pdev, hw);
3264 +
3265 + err = skge_reset(hw);
3266 + if (err)
3267 + goto err_out_free_irq;
3268 +
3269 + printk(KERN_INFO PFX "addr 0x%lx irq %d chip %s rev %d\n",
3270 + pci_resource_start(pdev, 0), pdev->irq,
3271 + skge_board_name(hw), chip_rev(hw));
3272 +
3273 + if ((dev = skge_devinit(hw, 0)) == NULL)
3274 + goto err_out_led_off;
3275 +
3276 + if (using_dac)
3277 + dev->features |= NETIF_F_HIGHDMA;
3278 +
3279 + if ((err = register_netdev(dev))) {
3280 + printk(KERN_ERR PFX "%s: cannot register net device\n",
3281 + pci_name(pdev));
3282 + goto err_out_free_netdev;
3283 + }
3284 +
3285 + skge_show_addr(dev);
3286 +
3287 + if (isdualport(hw) && (dev1 = skge_devinit(hw, 1))) {
3288 + if (using_dac)
3289 + dev1->features |= NETIF_F_HIGHDMA;
3290 +
3291 + if (register_netdev(dev1) == 0)
3292 + skge_show_addr(dev1);
3293 + else {
3294 + /* Failure to register second port need not be fatal */
3295 + printk(KERN_WARNING PFX "register of second port failed\n");
3296 + hw->dev[1] = NULL;
3297 + free_netdev(dev1);
3298 + }
3299 + }
3300 +
3301 + return 0;
3302 +
3303 +err_out_free_netdev:
3304 + free_netdev(dev);
3305 +err_out_led_off:
3306 + skge_write16(hw, B0_LED, LED_STAT_OFF);
3307 +err_out_free_irq:
3308 + free_irq(pdev->irq, hw);
3309 +err_out_iounmap:
3310 + iounmap(hw->regs);
3311 +err_out_free_hw:
3312 + kfree(hw);
3313 +err_out_free_regions:
3314 + pci_release_regions(pdev);
3315 +err_out_disable_pdev:
3316 + pci_disable_device(pdev);
3317 + pci_set_drvdata(pdev, NULL);
3318 +err_out:
3319 + return err;
3320 +}
3321 +
3322 +static void __devexit skge_remove(struct pci_dev *pdev)
3323 +{
3324 + struct skge_hw *hw = pci_get_drvdata(pdev);
3325 + struct net_device *dev0, *dev1;
3326 +
3327 + if(!hw)
3328 + return;
3329 +
3330 + if ((dev1 = hw->dev[1]))
3331 + unregister_netdev(dev1);
3332 + dev0 = hw->dev[0];
3333 + unregister_netdev(dev0);
3334 +
3335 + tasklet_kill(&hw->ext_tasklet);
3336 +
3337 + free_irq(pdev->irq, hw);
3338 + pci_release_regions(pdev);
3339 + pci_disable_device(pdev);
3340 + if (dev1)
3341 + free_netdev(dev1);
3342 + free_netdev(dev0);
3343 + skge_write16(hw, B0_LED, LED_STAT_OFF);
3344 + iounmap(hw->regs);
3345 + kfree(hw);
3346 + pci_set_drvdata(pdev, NULL);
3347 +}
3348 +
3349 +#ifdef CONFIG_PM
3350 +static int skge_suspend(struct pci_dev *pdev, u32 state)
3351 +{
3352 + struct skge_hw *hw = pci_get_drvdata(pdev);
3353 + int i, wol = 0;
3354 +
3355 + for(i = 0; i < 2; i++) {
3356 + struct net_device *dev = hw->dev[i];
3357 +
3358 + if (dev) {
3359 + struct skge_port *skge = netdev_priv(dev);
3360 + if (netif_running(dev)) {
3361 + netif_carrier_off(dev);
3362 + skge_down(dev);
3363 + }
3364 + netif_device_detach(dev);
3365 + wol |= skge->wol;
3366 + }
3367 + }
3368 +
3369 + pci_save_state(pdev);
3370 + pci_enable_wake(pdev, state, wol);
3371 + pci_disable_device(pdev);
3372 + pci_set_power_state(pdev, pci_choose_state(pdev, state));
3373 +
3374 + return 0;
3375 +}
3376 +
3377 +static int skge_resume(struct pci_dev *pdev)
3378 +{
3379 + struct skge_hw *hw = pci_get_drvdata(pdev);
3380 + int i;
3381 +
3382 + pci_set_power_state(pdev, PCI_D0);
3383 + pci_restore_state(pdev);
3384 + pci_enable_wake(pdev, PCI_D0, 0);
3385 +
3386 + skge_reset(hw);
3387 +
3388 + for(i = 0; i < 2; i++) {
3389 + struct net_device *dev = hw->dev[i];
3390 + if (dev) {
3391 + netif_device_attach(dev);
3392 + if(netif_running(dev))
3393 + skge_up(dev);
3394 + }
3395 + }
3396 + return 0;
3397 +}
3398 +#endif
3399 +
3400 +static struct pci_driver skge_driver = {
3401 + .name = DRV_NAME,
3402 + .id_table = skge_id_table,
3403 + .probe = skge_probe,
3404 + .remove = __devexit_p(skge_remove),
3405 +#ifdef CONFIG_PM
3406 + .suspend = skge_suspend,
3407 + .resume = skge_resume,
3408 +#endif
3409 +};
3410 +
3411 +static int __init skge_init_module(void)
3412 +{
3413 + return pci_module_init(&skge_driver);
3414 +}
3415 +
3416 +static void __exit skge_cleanup_module(void)
3417 +{
3418 + pci_unregister_driver(&skge_driver);
3419 +}
3420 +
3421 +module_init(skge_init_module);
3422 +module_exit(skge_cleanup_module);
3423 diff -Nru a/drivers/net/skge.h b/drivers/net/skge.h
3424 --- /dev/null Wed Dec 31 16:00:00 196900
3425 +++ b/drivers/net/skge.h 2005-03-15 23:46:53 -08:00
3426 @@ -0,0 +1,3005 @@
3427 +/*
3428 + * Definitions for the new Marvell Yukon / SysKonenct driver.
3429 + */
3430 +#ifndef _SKGE_H
3431 +#define _SKGE_H
3432 +
3433 +/* PCI config registers */
3434 +#define PCI_DEV_REG1 0x40
3435 +#define PCI_DEV_REG2 0x44
3436 +#ifndef PCI_VPD
3437 +#define PCI_VPD 0x50
3438 +#endif
3439 +
3440 +/* PCI_OUR_REG_2 32 bit Our Register 2 */
3441 +enum {
3442 + PCI_VPD_WR_THR = 0xff<<24, /* Bit 31..24: VPD Write Threshold */
3443 + PCI_DEV_SEL = 0x7f<<17, /* Bit 23..17: EEPROM Device Select */
3444 + PCI_VPD_ROM_SZ = 7 <<14, /* Bit 16..14: VPD ROM Size */
3445 + /* Bit 13..12: reserved */
3446 + PCI_EN_DUMMY_RD = 1<<3, /* Enable Dummy Read */
3447 + PCI_REV_DESC = 1<<2, /* Reverse Desc. Bytes */
3448 + PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */
3449 +};
3450 +
3451 +/* PCI_VPD_ADR_REG 16 bit VPD Address Register */
3452 +enum {
3453 + PCI_VPD_FLAG = 1<<15, /* starts VPD rd/wr cycle */
3454 + PCI_VPD_ADR_MSK =0x7fffL, /* Bit 14.. 0: VPD Address Mask */
3455 + VPD_RES_ID = 0x82,
3456 + VPD_RES_READ = 0x90,
3457 + VPD_RES_WRITE = 0x81,
3458 + VPD_RES_END = 0x78,
3459 +};
3460 +
3461 +
3462 +#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
3463 + PCI_STATUS_SIG_SYSTEM_ERROR | \
3464 + PCI_STATUS_REC_MASTER_ABORT | \
3465 + PCI_STATUS_REC_TARGET_ABORT | \
3466 + PCI_STATUS_PARITY)
3467 +
3468 +
3469 +enum csr_regs {
3470 + B0_RAP = 0x0000,
3471 + B0_CTST = 0x0004,
3472 + B0_LED = 0x0006,
3473 + B0_POWER_CTRL = 0x0007,
3474 + B0_ISRC = 0x0008,
3475 + B0_IMSK = 0x000c,
3476 + B0_HWE_ISRC = 0x0010,
3477 + B0_HWE_IMSK = 0x0014,
3478 + B0_SP_ISRC = 0x0018,
3479 + B0_XM1_IMSK = 0x0020,
3480 + B0_XM1_ISRC = 0x0028,
3481 + B0_XM1_PHY_ADDR = 0x0030,
3482 + B0_XM1_PHY_DATA = 0x0034,
3483 + B0_XM2_IMSK = 0x0040,
3484 + B0_XM2_ISRC = 0x0048,
3485 + B0_XM2_PHY_ADDR = 0x0050,
3486 + B0_XM2_PHY_DATA = 0x0054,
3487 + B0_R1_CSR = 0x0060,
3488 + B0_R2_CSR = 0x0064,
3489 + B0_XS1_CSR = 0x0068,
3490 + B0_XA1_CSR = 0x006c,
3491 + B0_XS2_CSR = 0x0070,
3492 + B0_XA2_CSR = 0x0074,
3493 +
3494 + B2_MAC_1 = 0x0100,
3495 + B2_MAC_2 = 0x0108,
3496 + B2_MAC_3 = 0x0110,
3497 + B2_CONN_TYP = 0x0118,
3498 + B2_PMD_TYP = 0x0119,
3499 + B2_MAC_CFG = 0x011a,
3500 + B2_CHIP_ID = 0x011b,
3501 + B2_E_0 = 0x011c,
3502 + B2_E_1 = 0x011d,
3503 + B2_E_2 = 0x011e,
3504 + B2_E_3 = 0x011f,
3505 + B2_FAR = 0x0120,
3506 + B2_FDP = 0x0124,
3507 + B2_LD_CTRL = 0x0128,
3508 + B2_LD_TEST = 0x0129,
3509 + B2_TI_INI = 0x0130,
3510 + B2_TI_VAL = 0x0134,
3511 + B2_TI_CTRL = 0x0138,
3512 + B2_TI_TEST = 0x0139,
3513 + B2_IRQM_INI = 0x0140,
3514 + B2_IRQM_VAL = 0x0144,
3515 + B2_IRQM_CTRL = 0x0148,
3516 + B2_IRQM_TEST = 0x0149,
3517 + B2_IRQM_MSK = 0x014c,
3518 + B2_IRQM_HWE_MSK = 0x0150,
3519 + B2_TST_CTRL1 = 0x0158,
3520 + B2_TST_CTRL2 = 0x0159,
3521 + B2_GP_IO = 0x015c,
3522 + B2_I2C_CTRL = 0x0160,
3523 + B2_I2C_DATA = 0x0164,
3524 + B2_I2C_IRQ = 0x0168,
3525 + B2_I2C_SW = 0x016c,
3526 + B2_BSC_INI = 0x0170,
3527 + B2_BSC_VAL = 0x0174,
3528 + B2_BSC_CTRL = 0x0178,
3529 + B2_BSC_STAT = 0x0179,
3530 + B2_BSC_TST = 0x017a,
3531 +
3532 + B3_RAM_ADDR = 0x0180,
3533 + B3_RAM_DATA_LO = 0x0184,
3534 + B3_RAM_DATA_HI = 0x0188,
3535 + B3_RI_WTO_R1 = 0x0190,
3536 + B3_RI_WTO_XA1 = 0x0191,
3537 + B3_RI_WTO_XS1 = 0x0192,
3538 + B3_RI_RTO_R1 = 0x0193,
3539 + B3_RI_RTO_XA1 = 0x0194,
3540 + B3_RI_RTO_XS1 = 0x0195,
3541 + B3_RI_WTO_R2 = 0x0196,
3542 + B3_RI_WTO_XA2 = 0x0197,
3543 + B3_RI_WTO_XS2 = 0x0198,
3544 + B3_RI_RTO_R2 = 0x0199,
3545 + B3_RI_RTO_XA2 = 0x019a,
3546 + B3_RI_RTO_XS2 = 0x019b,
3547 + B3_RI_TO_VAL = 0x019c,
3548 + B3_RI_CTRL = 0x01a0,
3549 + B3_RI_TEST = 0x01a2,
3550 + B3_MA_TOINI_RX1 = 0x01b0,
3551 + B3_MA_TOINI_RX2 = 0x01b1,
3552 + B3_MA_TOINI_TX1 = 0x01b2,
3553 + B3_MA_TOINI_TX2 = 0x01b3,
3554 + B3_MA_TOVAL_RX1 = 0x01b4,
3555 + B3_MA_TOVAL_RX2 = 0x01b5,
3556 + B3_MA_TOVAL_TX1 = 0x01b6,
3557 + B3_MA_TOVAL_TX2 = 0x01b7,
3558 + B3_MA_TO_CTRL = 0x01b8,
3559 + B3_MA_TO_TEST = 0x01ba,
3560 + B3_MA_RCINI_RX1 = 0x01c0,
3561 + B3_MA_RCINI_RX2 = 0x01c1,
3562 + B3_MA_RCINI_TX1 = 0x01c2,
3563 + B3_MA_RCINI_TX2 = 0x01c3,
3564 + B3_MA_RCVAL_RX1 = 0x01c4,
3565 + B3_MA_RCVAL_RX2 = 0x01c5,
3566 + B3_MA_RCVAL_TX1 = 0x01c6,
3567 + B3_MA_RCVAL_TX2 = 0x01c7,
3568 + B3_MA_RC_CTRL = 0x01c8,
3569 + B3_MA_RC_TEST = 0x01ca,
3570 + B3_PA_TOINI_RX1 = 0x01d0,
3571 + B3_PA_TOINI_RX2 = 0x01d4,
3572 + B3_PA_TOINI_TX1 = 0x01d8,
3573 + B3_PA_TOINI_TX2 = 0x01dc,
3574 + B3_PA_TOVAL_RX1 = 0x01e0,
3575 + B3_PA_TOVAL_RX2 = 0x01e4,
3576 + B3_PA_TOVAL_TX1 = 0x01e8,
3577 + B3_PA_TOVAL_TX2 = 0x01ec,
3578 + B3_PA_CTRL = 0x01f0,
3579 + B3_PA_TEST = 0x01f2,
3580 +};
3581 +
3582 +/* B0_CTST 16 bit Control/Status register */
3583 +enum {
3584 + CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
3585 + CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
3586 + CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
3587 + CS_VAUX_AVAIL = 1<<10,/* VAUX available (YUKON only) */
3588 + CS_BUS_CLOCK = 1<<9, /* Bus Clock 0/1 = 33/66 MHz */
3589 + CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
3590 + CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
3591 + CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
3592 + CS_STOP_DONE = 1<<5, /* Stop Master is finished */
3593 + CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
3594 + CS_MRST_CLR = 1<<3, /* Clear Master reset */
3595 + CS_MRST_SET = 1<<2, /* Set Master reset */
3596 + CS_RST_CLR = 1<<1, /* Clear Software reset */
3597 + CS_RST_SET = 1, /* Set Software reset */
3598 +
3599 +/* B0_LED 8 Bit LED register */
3600 +/* Bit 7.. 2: reserved */
3601 + LED_STAT_ON = 1<<1, /* Status LED on */
3602 + LED_STAT_OFF = 1, /* Status LED off */
3603 +
3604 +/* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
3605 + PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
3606 + PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
3607 + PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
3608 + PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
3609 + PC_VAUX_ON = 1<<3, /* Switch VAUX On */
3610 + PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
3611 + PC_VCC_ON = 1<<1, /* Switch VCC On */
3612 + PC_VCC_OFF = 1<<0, /* Switch VCC Off */
3613 +};
3614 +
3615 +/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
3616 +enum {
3617 + IS_ALL_MSK = 0xbffffffful, /* All Interrupt bits */
3618 + IS_HW_ERR = 1<<31, /* Interrupt HW Error */
3619 + /* Bit 30: reserved */
3620 + IS_PA_TO_RX1 = 1<<29, /* Packet Arb Timeout Rx1 */
3621 + IS_PA_TO_RX2 = 1<<28, /* Packet Arb Timeout Rx2 */
3622 + IS_PA_TO_TX1 = 1<<27, /* Packet Arb Timeout Tx1 */
3623 + IS_PA_TO_TX2 = 1<<26, /* Packet Arb Timeout Tx2 */
3624 + IS_I2C_READY = 1<<25, /* IRQ on end of I2C Tx */
3625 + IS_IRQ_SW = 1<<24, /* SW forced IRQ */
3626 + IS_EXT_REG = 1<<23, /* IRQ from LM80 or PHY (GENESIS only) */
3627 + /* IRQ from PHY (YUKON only) */
3628 + IS_TIMINT = 1<<22, /* IRQ from Timer */
3629 + IS_MAC1 = 1<<21, /* IRQ from MAC 1 */
3630 + IS_LNK_SYNC_M1 = 1<<20, /* Link Sync Cnt wrap MAC 1 */
3631 + IS_MAC2 = 1<<19, /* IRQ from MAC 2 */
3632 + IS_LNK_SYNC_M2 = 1<<18, /* Link Sync Cnt wrap MAC 2 */
3633 +/* Receive Queue 1 */
3634 + IS_R1_B = 1<<17, /* Q_R1 End of Buffer */
3635 + IS_R1_F = 1<<16, /* Q_R1 End of Frame */
3636 + IS_R1_C = 1<<15, /* Q_R1 Encoding Error */
3637 +/* Receive Queue 2 */
3638 + IS_R2_B = 1<<14, /* Q_R2 End of Buffer */
3639 + IS_R2_F = 1<<13, /* Q_R2 End of Frame */
3640 + IS_R2_C = 1<<12, /* Q_R2 Encoding Error */
3641 +/* Synchronous Transmit Queue 1 */
3642 + IS_XS1_B = 1<<11, /* Q_XS1 End of Buffer */
3643 + IS_XS1_F = 1<<10, /* Q_XS1 End of Frame */
3644 + IS_XS1_C = 1<<9, /* Q_XS1 Encoding Error */
3645 +/* Asynchronous Transmit Queue 1 */
3646 + IS_XA1_B = 1<<8, /* Q_XA1 End of Buffer */
3647 + IS_XA1_F = 1<<7, /* Q_XA1 End of Frame */
3648 + IS_XA1_C = 1<<6, /* Q_XA1 Encoding Error */
3649 +/* Synchronous Transmit Queue 2 */
3650 + IS_XS2_B = 1<<5, /* Q_XS2 End of Buffer */
3651 + IS_XS2_F = 1<<4, /* Q_XS2 End of Frame */
3652 + IS_XS2_C = 1<<3, /* Q_XS2 Encoding Error */
3653 +/* Asynchronous Transmit Queue 2 */
3654 + IS_XA2_B = 1<<2, /* Q_XA2 End of Buffer */
3655 + IS_XA2_F = 1<<1, /* Q_XA2 End of Frame */
3656 + IS_XA2_C = 1<<0, /* Q_XA2 Encoding Error */
3657 +
3658 + IS_PORT_1 = IS_XA1_F| IS_R1_F| IS_MAC1,
3659 + IS_PORT_2 = IS_XA2_F| IS_R2_F| IS_MAC2,
3660 +};
3661 +
3662 +
3663 +/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
3664 +enum {
3665 + IS_ERR_MSK = 0x00003fff,/* All Error bits */
3666 +
3667 + IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
3668 + IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
3669 + IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
3670 + IS_IRQ_STAT = 1<<10, /* IRQ status exception */
3671 + IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
3672 + IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
3673 + IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
3674 + IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
3675 + IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
3676 + IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
3677 + IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
3678 + IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
3679 + IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
3680 + IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
3681 +};
3682 +
3683 +/* B2_TST_CTRL1 8 bit Test Control Register 1 */
3684 +enum {
3685 + TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
3686 + TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
3687 + TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
3688 + TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
3689 + TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
3690 + TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
3691 + TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
3692 + TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
3693 +};
3694 +
3695 +/* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
3696 +enum {
3697 + CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
3698 + /* Bit 3.. 2: reserved */
3699 + CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
3700 + CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
3701 +};
3702 +
3703 +/* B2_CHIP_ID 8 bit Chip Identification Number */
3704 +enum {
3705 + CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */
3706 + CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */
3707 + CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
3708 + CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
3709 + CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
3710 + CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
3711 + CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
3712 +
3713 + CHIP_REV_YU_LITE_A1 = 3, /* Chip Rev. for YUKON-Lite A1,A2 */
3714 + CHIP_REV_YU_LITE_A3 = 7, /* Chip Rev. for YUKON-Lite A3 */
3715 +};
3716 +
3717 +/* B2_LD_TEST 8 bit EPROM loader test register */
3718 +enum {
3719 + LD_T_ON = 1<<3, /* Loader Test mode on */
3720 + LD_T_OFF = 1<<2, /* Loader Test mode off */
3721 + LD_T_STEP = 1<<1, /* Decrement FPROM addr. Counter */
3722 + LD_START = 1<<0, /* Start loading FPROM */
3723 +};
3724 +
3725 +/* B2_TI_CTRL 8 bit Timer control */
3726 +/* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
3727 +enum {
3728 + TIM_START = 1<<2, /* Start Timer */
3729 + TIM_STOP = 1<<1, /* Stop Timer */
3730 + TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
3731 +};
3732 +
3733 +/* B2_TI_TEST 8 Bit Timer Test */
3734 +/* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
3735 +/* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
3736 +enum {
3737 + TIM_T_ON = 1<<2, /* Test mode on */
3738 + TIM_T_OFF = 1<<1, /* Test mode off */
3739 + TIM_T_STEP = 1<<0, /* Test step */
3740 +};
3741 +
3742 +/* B28_DPT_INI 32 bit Descriptor Poll Timer Init Val */
3743 +/* B28_DPT_VAL 32 bit Descriptor Poll Timer Curr Val */
3744 +/* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
3745 +enum {
3746 + DPT_MSK = 0x00ffffffL, /* Bit 23.. 0: Desc Poll Timer Bits */
3747 +
3748 + DPT_START = 1<<1, /* Start Descriptor Poll Timer */
3749 + DPT_STOP = 1<<0, /* Stop Descriptor Poll Timer */
3750 +};
3751 +
3752 +/* B2_GP_IO 32 bit General Purpose I/O Register */
3753 +enum {
3754 + GP_DIR_9 = 1<<25, /* IO_9 direct, 0=In/1=Out */
3755 + GP_DIR_8 = 1<<24, /* IO_8 direct, 0=In/1=Out */
3756 + GP_DIR_7 = 1<<23, /* IO_7 direct, 0=In/1=Out */
3757 + GP_DIR_6 = 1<<22, /* IO_6 direct, 0=In/1=Out */
3758 + GP_DIR_5 = 1<<21, /* IO_5 direct, 0=In/1=Out */
3759 + GP_DIR_4 = 1<<20, /* IO_4 direct, 0=In/1=Out */
3760 + GP_DIR_3 = 1<<19, /* IO_3 direct, 0=In/1=Out */
3761 + GP_DIR_2 = 1<<18, /* IO_2 direct, 0=In/1=Out */
3762 + GP_DIR_1 = 1<<17, /* IO_1 direct, 0=In/1=Out */
3763 + GP_DIR_0 = 1<<16, /* IO_0 direct, 0=In/1=Out */
3764 +
3765 + GP_IO_9 = 1<<9, /* IO_9 pin */
3766 + GP_IO_8 = 1<<8, /* IO_8 pin */
3767 + GP_IO_7 = 1<<7, /* IO_7 pin */
3768 + GP_IO_6 = 1<<6, /* IO_6 pin */
3769 + GP_IO_5 = 1<<5, /* IO_5 pin */
3770 + GP_IO_4 = 1<<4, /* IO_4 pin */
3771 + GP_IO_3 = 1<<3, /* IO_3 pin */
3772 + GP_IO_2 = 1<<2, /* IO_2 pin */
3773 + GP_IO_1 = 1<<1, /* IO_1 pin */
3774 + GP_IO_0 = 1<<0, /* IO_0 pin */
3775 +};
3776 +
3777 +/* Rx/Tx Path related Arbiter Test Registers */
3778 +/* B3_MA_TO_TEST 16 bit MAC Arbiter Timeout Test Reg */
3779 +/* B3_MA_RC_TEST 16 bit MAC Arbiter Recovery Test Reg */
3780 +/* B3_PA_TEST 16 bit Packet Arbiter Test Register */
3781 +/* Bit 15, 11, 7, and 3 are reserved in B3_PA_TEST */
3782 +enum {
3783 + TX2_T_EV = 1<<15,/* TX2 Timeout/Recv Event occured */
3784 + TX2_T_ON = 1<<14,/* TX2 Timeout/Recv Timer Test On */
3785 + TX2_T_OFF = 1<<13,/* TX2 Timeout/Recv Timer Tst Off */
3786 + TX2_T_STEP = 1<<12,/* TX2 Timeout/Recv Timer Step */
3787 + TX1_T_EV = 1<<11,/* TX1 Timeout/Recv Event occured */
3788 + TX1_T_ON = 1<<10,/* TX1 Timeout/Recv Timer Test On */
3789 + TX1_T_OFF = 1<<9, /* TX1 Timeout/Recv Timer Tst Off */
3790 + TX1_T_STEP = 1<<8, /* TX1 Timeout/Recv Timer Step */
3791 + RX2_T_EV = 1<<7, /* RX2 Timeout/Recv Event occured */
3792 + RX2_T_ON = 1<<6, /* RX2 Timeout/Recv Timer Test On */
3793 + RX2_T_OFF = 1<<5, /* RX2 Timeout/Recv Timer Tst Off */
3794 + RX2_T_STEP = 1<<4, /* RX2 Timeout/Recv Timer Step */
3795 + RX1_T_EV = 1<<3, /* RX1 Timeout/Recv Event occured */
3796 + RX1_T_ON = 1<<2, /* RX1 Timeout/Recv Timer Test On */
3797 + RX1_T_OFF = 1<<1, /* RX1 Timeout/Recv Timer Tst Off */
3798 + RX1_T_STEP = 1<<0, /* RX1 Timeout/Recv Timer Step */
3799 +};
3800 +
3801 +/* Descriptor Bit Definition */
3802 +/* TxCtrl Transmit Buffer Control Field */
3803 +/* RxCtrl Receive Buffer Control Field */
3804 +enum {
3805 + BMU_OWN = 1<<31, /* OWN bit: 0=host/1=BMU */
3806 + BMU_STF = 1<<30, /* Start of Frame */
3807 + BMU_EOF = 1<<29, /* End of Frame */
3808 + BMU_IRQ_EOB = 1<<28, /* Req "End of Buffer" IRQ */
3809 + BMU_IRQ_EOF = 1<<27, /* Req "End of Frame" IRQ */
3810 + /* TxCtrl specific bits */
3811 + BMU_STFWD = 1<<26, /* (Tx) Store & Forward Frame */
3812 + BMU_NO_FCS = 1<<25, /* (Tx) Disable MAC FCS (CRC) generation */
3813 + BMU_SW = 1<<24, /* (Tx) 1 bit res. for SW use */
3814 + /* RxCtrl specific bits */
3815 + BMU_DEV_0 = 1<<26, /* (Rx) Transfer data to Dev0 */
3816 + BMU_STAT_VAL = 1<<25, /* (Rx) Rx Status Valid */
3817 + BMU_TIST_VAL = 1<<24, /* (Rx) Rx TimeStamp Valid */
3818 + /* Bit 23..16: BMU Check Opcodes */
3819 + BMU_CHECK = 0x55<<16, /* Default BMU check */
3820 + BMU_TCP_CHECK = 0x56<<16, /* Descr with TCP ext */
3821 + BMU_UDP_CHECK = 0x57<<16, /* Descr with UDP ext (YUKON only) */
3822 + BMU_BBC = 0xffffL, /* Bit 15.. 0: Buffer Byte Counter */
3823 +};
3824 +
3825 +/* B2_BSC_CTRL 8 bit Blink Source Counter Control */
3826 +enum {
3827 + BSC_START = 1<<1, /* Start Blink Source Counter */
3828 + BSC_STOP = 1<<0, /* Stop Blink Source Counter */
3829 +};
3830 +
3831 +/* B2_BSC_STAT 8 bit Blink Source Counter Status */
3832 +enum {
3833 + BSC_SRC = 1<<0, /* Blink Source, 0=Off / 1=On */
3834 +};
3835 +
3836 +/* B2_BSC_TST 16 bit Blink Source Counter Test Reg */
3837 +enum {
3838 + BSC_T_ON = 1<<2, /* Test mode on */
3839 + BSC_T_OFF = 1<<1, /* Test mode off */
3840 + BSC_T_STEP = 1<<0, /* Test step */
3841 +};
3842 +
3843 +/* B3_RAM_ADDR 32 bit RAM Address, to read or write */
3844 + /* Bit 31..19: reserved */
3845 +#define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
3846 +/* RAM Interface Registers */
3847 +
3848 +/* B3_RI_CTRL 16 bit RAM Iface Control Register */
3849 +enum {
3850 + RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
3851 + RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
3852 +
3853 + RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
3854 + RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
3855 +};
3856 +
3857 +/* B3_RI_TEST 8 bit RAM Iface Test Register */
3858 +enum {
3859 + RI_T_EV = 1<<3, /* Timeout Event occured */
3860 + RI_T_ON = 1<<2, /* Timeout Timer Test On */
3861 + RI_T_OFF = 1<<1, /* Timeout Timer Test Off */
3862 + RI_T_STEP = 1<<0, /* Timeout Timer Step */
3863 +};
3864 +
3865 +/* MAC Arbiter Registers */
3866 +/* B3_MA_TO_CTRL 16 bit MAC Arbiter Timeout Ctrl Reg */
3867 +enum {
3868 + MA_FOE_ON = 1<<3, /* XMAC Fast Output Enable ON */
3869 + MA_FOE_OFF = 1<<2, /* XMAC Fast Output Enable OFF */
3870 + MA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
3871 + MA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
3872 +
3873 +};
3874 +
3875 +/* Timeout values */
3876 +#define SK_MAC_TO_53 72 /* MAC arbiter timeout */
3877 +#define SK_PKT_TO_53 0x2000 /* Packet arbiter timeout */
3878 +#define SK_PKT_TO_MAX 0xffff /* Maximum value */
3879 +#define SK_RI_TO_53 36 /* RAM interface timeout */
3880 +
3881 +
3882 +/* B3_MA_RC_CTRL 16 bit MAC Arbiter Recovery Ctrl Reg */
3883 +enum {
3884 + MA_ENA_REC_TX2 = 1<<7, /* Enable Recovery Timer TX2 */
3885 + MA_DIS_REC_TX2 = 1<<6, /* Disable Recovery Timer TX2 */
3886 + MA_ENA_REC_TX1 = 1<<5, /* Enable Recovery Timer TX1 */
3887 + MA_DIS_REC_TX1 = 1<<4, /* Disable Recovery Timer TX1 */
3888 + MA_ENA_REC_RX2 = 1<<3, /* Enable Recovery Timer RX2 */
3889 + MA_DIS_REC_RX2 = 1<<2, /* Disable Recovery Timer RX2 */
3890 + MA_ENA_REC_RX1 = 1<<1, /* Enable Recovery Timer RX1 */
3891 + MA_DIS_REC_RX1 = 1<<0, /* Disable Recovery Timer RX1 */
3892 +};
3893 +
3894 +/* Packet Arbiter Registers */
3895 +/* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */
3896 +enum {
3897 + PA_CLR_TO_TX2 = 1<<13, /* Clear IRQ Packet Timeout TX2 */
3898 + PA_CLR_TO_TX1 = 1<<12, /* Clear IRQ Packet Timeout TX1 */
3899 + PA_CLR_TO_RX2 = 1<<11, /* Clear IRQ Packet Timeout RX2 */
3900 + PA_CLR_TO_RX1 = 1<<10, /* Clear IRQ Packet Timeout RX1 */
3901 + PA_ENA_TO_TX2 = 1<<9, /* Enable Timeout Timer TX2 */
3902 + PA_DIS_TO_TX2 = 1<<8, /* Disable Timeout Timer TX2 */
3903 + PA_ENA_TO_TX1 = 1<<7, /* Enable Timeout Timer TX1 */
3904 + PA_DIS_TO_TX1 = 1<<6, /* Disable Timeout Timer TX1 */
3905 + PA_ENA_TO_RX2 = 1<<5, /* Enable Timeout Timer RX2 */
3906 + PA_DIS_TO_RX2 = 1<<4, /* Disable Timeout Timer RX2 */
3907 + PA_ENA_TO_RX1 = 1<<3, /* Enable Timeout Timer RX1 */
3908 + PA_DIS_TO_RX1 = 1<<2, /* Disable Timeout Timer RX1 */
3909 + PA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
3910 + PA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
3911 +};
3912 +
3913 +#define PA_ENA_TO_ALL (PA_ENA_TO_RX1 | PA_ENA_TO_RX2 |\
3914 + PA_ENA_TO_TX1 | PA_ENA_TO_TX2)
3915 +
3916 +
3917 +/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */
3918 +/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
3919 +/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
3920 +/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
3921 +/* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
3922 +
3923 +#define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
3924 +
3925 +/* TXA_CTRL 8 bit Tx Arbiter Control Register */
3926 +enum {
3927 + TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
3928 + TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
3929 + TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
3930 + TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
3931 + TXA_START_RC = 1<<3, /* Start sync Rate Control */
3932 + TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
3933 + TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
3934 + TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
3935 +};
3936 +
3937 +/*
3938 + * Bank 4 - 5
3939 + */
3940 +/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */
3941 +enum {
3942 + TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
3943 + TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
3944 + TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
3945 + TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
3946 + TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
3947 + TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
3948 + TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
3949 +};
3950 +
3951 +
3952 +enum {
3953 + B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
3954 + B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
3955 + B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
3956 + B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
3957 + B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
3958 + B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
3959 + B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
3960 + B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
3961 + B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
3962 +};
3963 +
3964 +/* Queue Register Offsets, use Q_ADDR() to access */
3965 +enum {
3966 + B8_Q_REGS = 0x0400, /* base of Queue registers */
3967 + Q_D = 0x00, /* 8*32 bit Current Descriptor */
3968 + Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */
3969 + Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */
3970 + Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
3971 + Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
3972 + Q_BC = 0x30, /* 32 bit Current Byte Counter */
3973 + Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
3974 + Q_F = 0x38, /* 32 bit Flag Register */
3975 + Q_T1 = 0x3c, /* 32 bit Test Register 1 */
3976 + Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */
3977 + Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */
3978 + Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */
3979 + Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */
3980 + Q_T2 = 0x40, /* 32 bit Test Register 2 */
3981 + Q_T3 = 0x44, /* 32 bit Test Register 3 */
3982 +
3983 +/* Yukon-2 */
3984 + Q_DONE = 0x24, /* 16 bit Done Index (Yukon-2 only) */
3985 + Q_WM = 0x40, /* 16 bit FIFO Watermark */
3986 + Q_AL = 0x42, /* 8 bit FIFO Alignment */
3987 + Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */
3988 + Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */
3989 + Q_RP = 0x48, /* 8 bit FIFO Read Pointer */
3990 + Q_RL = 0x4a, /* 8 bit FIFO Read Level */
3991 + Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */
3992 + Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */
3993 + Q_WL = 0x4e, /* 8 bit FIFO Write Level */
3994 + Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */
3995 +};
3996 +#define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
3997 +
3998 +/* RAM Buffer Register Offsets */
3999 +enum {
4000 +
4001 + RB_START = 0x00,/* 32 bit RAM Buffer Start Address */
4002 + RB_END = 0x04,/* 32 bit RAM Buffer End Address */
4003 + RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
4004 + RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
4005 + RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
4006 + RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
4007 + RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */
4008 + RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
4009 + /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
4010 + RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
4011 + RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
4012 + RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
4013 + RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
4014 + RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
4015 +};
4016 +
4017 +/* Receive and Transmit Queues */
4018 +enum {
4019 + Q_R1 = 0x0000, /* Receive Queue 1 */
4020 + Q_R2 = 0x0080, /* Receive Queue 2 */
4021 + Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
4022 + Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
4023 + Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
4024 + Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
4025 +};
4026 +
4027 +/* Different MAC Types */
4028 +enum {
4029 + SK_MAC_XMAC = 0, /* Xaqti XMAC II */
4030 + SK_MAC_GMAC = 1, /* Marvell GMAC */
4031 +};
4032 +
4033 +/* Different PHY Types */
4034 +enum {
4035 + SK_PHY_XMAC = 0,/* integrated in XMAC II */
4036 + SK_PHY_BCOM = 1,/* Broadcom BCM5400 */
4037 + SK_PHY_LONE = 2,/* Level One LXT1000 [not supported]*/
4038 + SK_PHY_NAT = 3,/* National DP83891 [not supported] */
4039 + SK_PHY_MARV_COPPER= 4,/* Marvell 88E1011S */
4040 + SK_PHY_MARV_FIBER = 5,/* Marvell 88E1011S working on fiber */
4041 +};
4042 +
4043 +/* PHY addresses (bits 12..8 of PHY address reg) */
4044 +enum {
4045 + PHY_ADDR_XMAC = 0<<8,
4046 + PHY_ADDR_BCOM = 1<<8,
4047 + PHY_ADDR_LONE = 3<<8,
4048 + PHY_ADDR_NAT = 0<<8,
4049 +/* GPHY address (bits 15..11 of SMI control reg) */
4050 + PHY_ADDR_MARV = 0,
4051 +};
4052 +
4053 +#define RB_ADDR(offs, queue) (B16_RAM_REGS + (queue) + (offs))
4054 +
4055 +/* Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only) */
4056 +enum {
4057 + RX_MFF_EA = 0x0c00,/* 32 bit Receive MAC FIFO End Address */
4058 + RX_MFF_WP = 0x0c04,/* 32 bit Receive MAC FIFO Write Pointer */
4059 +
4060 + RX_MFF_RP = 0x0c0c,/* 32 bit Receive MAC FIFO Read Pointer */
4061 + RX_MFF_PC = 0x0c10,/* 32 bit Receive MAC FIFO Packet Cnt */
4062 + RX_MFF_LEV = 0x0c14,/* 32 bit Receive MAC FIFO Level */
4063 + RX_MFF_CTRL1 = 0x0c18,/* 16 bit Receive MAC FIFO Control Reg 1*/
4064 + RX_MFF_STAT_TO = 0x0c1a,/* 8 bit Receive MAC Status Timeout */
4065 + RX_MFF_TIST_TO = 0x0c1b,/* 8 bit Receive MAC Time Stamp Timeout */
4066 + RX_MFF_CTRL2 = 0x0c1c,/* 8 bit Receive MAC FIFO Control Reg 2*/
4067 + RX_MFF_TST1 = 0x0c1d,/* 8 bit Receive MAC FIFO Test Reg 1 */
4068 + RX_MFF_TST2 = 0x0c1e,/* 8 bit Receive MAC FIFO Test Reg 2 */
4069 +
4070 + RX_LED_INI = 0x0c20,/* 32 bit Receive LED Cnt Init Value */
4071 + RX_LED_VAL = 0x0c24,/* 32 bit Receive LED Cnt Current Value */
4072 + RX_LED_CTRL = 0x0c28,/* 8 bit Receive LED Cnt Control Reg */
4073 + RX_LED_TST = 0x0c29,/* 8 bit Receive LED Cnt Test Register */
4074 +
4075 + LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
4076 + LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
4077 + LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
4078 + LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
4079 + LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
4080 +};
4081 +
4082 +/* Receive and Transmit MAC FIFO Registers (GENESIS only) */
4083 +/* RX_MFF_CTRL1 16 bit Receive MAC FIFO Control Reg 1 */
4084 +enum {
4085 + MFF_ENA_RDY_PAT = 1<<13, /* Enable Ready Patch */
4086 + MFF_DIS_RDY_PAT = 1<<12, /* Disable Ready Patch */
4087 + MFF_ENA_TIM_PAT = 1<<11, /* Enable Timing Patch */
4088 + MFF_DIS_TIM_PAT = 1<<10, /* Disable Timing Patch */
4089 + MFF_ENA_ALM_FUL = 1<<9, /* Enable AlmostFull Sign */
4090 + MFF_DIS_ALM_FUL = 1<<8, /* Disable AlmostFull Sign */
4091 + MFF_ENA_PAUSE = 1<<7, /* Enable Pause Signaling */
4092 + MFF_DIS_PAUSE = 1<<6, /* Disable Pause Signaling */
4093 + MFF_ENA_FLUSH = 1<<5, /* Enable Frame Flushing */
4094 + MFF_DIS_FLUSH = 1<<4, /* Disable Frame Flushing */
4095 + MFF_ENA_TIST = 1<<3, /* Enable Time Stamp Gener */
4096 + MFF_DIS_TIST = 1<<2, /* Disable Time Stamp Gener */
4097 + MFF_CLR_INTIST = 1<<1, /* Clear IRQ No Time Stamp */
4098 + MFF_CLR_INSTAT = 1<<0, /* Clear IRQ No Status */
4099 +#define MFF_RX_CTRL_DEF MFF_ENA_TIM_PAT
4100 +};
4101 +
4102 +/* TX_MFF_CTRL1 16 bit Transmit MAC FIFO Control Reg 1 */
4103 +enum {
4104 + MFF_CLR_PERR = 1<<15, /* Clear Parity Error IRQ */
4105 + /* Bit 14: reserved */
4106 + MFF_ENA_PKT_REC = 1<<13, /* Enable Packet Recovery */
4107 + MFF_DIS_PKT_REC = 1<<12, /* Disable Packet Recovery */
4108 +
4109 + MFF_ENA_W4E = 1<<7, /* Enable Wait for Empty */
4110 + MFF_DIS_W4E = 1<<6, /* Disable Wait for Empty */
4111 +
4112 + MFF_ENA_LOOPB = 1<<3, /* Enable Loopback */
4113 + MFF_DIS_LOOPB = 1<<2, /* Disable Loopback */
4114 + MFF_CLR_MAC_RST = 1<<1, /* Clear XMAC Reset */
4115 + MFF_SET_MAC_RST = 1<<0, /* Set XMAC Reset */
4116 +};
4117 +
4118 +#define MFF_TX_CTRL_DEF (MFF_ENA_PKT_REC | MFF_ENA_TIM_PAT | MFF_ENA_FLUSH)
4119 +
4120 +/* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */
4121 +/* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */
4122 +enum {
4123 + MFF_WSP_T_ON = 1<<6, /* Tx: Write Shadow Ptr TestOn */
4124 + MFF_WSP_T_OFF = 1<<5, /* Tx: Write Shadow Ptr TstOff */
4125 + MFF_WSP_INC = 1<<4, /* Tx: Write Shadow Ptr Increment */
4126 + MFF_PC_DEC = 1<<3, /* Packet Counter Decrement */
4127 + MFF_PC_T_ON = 1<<2, /* Packet Counter Test On */
4128 + MFF_PC_T_OFF = 1<<1, /* Packet Counter Test Off */
4129 + MFF_PC_INC = 1<<0, /* Packet Counter Increment */
4130 +};
4131 +
4132 +/* RX_MFF_TST1 8 bit Receive MAC FIFO Test Register 1 */
4133 +/* TX_MFF_TST1 8 bit Transmit MAC FIFO Test Register 1 */
4134 +enum {
4135 + MFF_WP_T_ON = 1<<6, /* Write Pointer Test On */
4136 + MFF_WP_T_OFF = 1<<5, /* Write Pointer Test Off */
4137 + MFF_WP_INC = 1<<4, /* Write Pointer Increm */
4138 +
4139 + MFF_RP_T_ON = 1<<2, /* Read Pointer Test On */
4140 + MFF_RP_T_OFF = 1<<1, /* Read Pointer Test Off */
4141 + MFF_RP_DEC = 1<<0, /* Read Pointer Decrement */
4142 +};
4143 +
4144 +/* RX_MFF_CTRL2 8 bit Receive MAC FIFO Control Reg 2 */
4145 +/* TX_MFF_CTRL2 8 bit Transmit MAC FIFO Control Reg 2 */
4146 +enum {
4147 + MFF_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
4148 + MFF_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
4149 + MFF_RST_CLR = 1<<1, /* Clear MAC FIFO Reset */
4150 + MFF_RST_SET = 1<<0, /* Set MAC FIFO Reset */
4151 +};
4152 +
4153 +
4154 +/* Link LED Counter Registers (GENESIS only) */
4155 +
4156 +/* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */
4157 +/* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */
4158 +/* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */
4159 +enum {
4160 + LED_START = 1<<2, /* Start Timer */
4161 + LED_STOP = 1<<1, /* Stop Timer */
4162 + LED_STATE = 1<<0, /* Rx/Tx: LED State, 1=LED on */
4163 +};
4164 +
4165 +/* RX_LED_TST 8 bit Receive LED Cnt Test Register */
4166 +/* TX_LED_TST 8 bit Transmit LED Cnt Test Register */
4167 +/* LNK_SYNC_TST 8 bit Link Sync Cnt Test Register */
4168 +enum {
4169 + LED_T_ON = 1<<2, /* LED Counter Test mode On */
4170 + LED_T_OFF = 1<<1, /* LED Counter Test mode Off */
4171 + LED_T_STEP = 1<<0, /* LED Counter Step */
4172 +};
4173 +
4174 +/* LNK_LED_REG 8 bit Link LED Register */
4175 +enum {
4176 + LED_BLK_ON = 1<<5, /* Link LED Blinking On */
4177 + LED_BLK_OFF = 1<<4, /* Link LED Blinking Off */
4178 + LED_SYNC_ON = 1<<3, /* Use Sync Wire to switch LED */
4179 + LED_SYNC_OFF = 1<<2, /* Disable Sync Wire Input */
4180 + LED_ON = 1<<1, /* switch LED on */
4181 + LED_OFF = 1<<0, /* switch LED off */
4182 +};
4183 +
4184 +/* Receive GMAC FIFO (YUKON and Yukon-2) */
4185 +enum {
4186 + RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
4187 + RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
4188 + RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
4189 + RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
4190 + RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
4191 + RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
4192 +
4193 + RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
4194 + RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
4195 +
4196 + RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
4197 +
4198 + RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
4199 +
4200 + RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
4201 +};
4202 +
4203 +
4204 +/* TXA_TEST 8 bit Tx Arbiter Test Register */
4205 +enum {
4206 + TXA_INT_T_ON = 1<<5, /* Tx Arb Interval Timer Test On */
4207 + TXA_INT_T_OFF = 1<<4, /* Tx Arb Interval Timer Test Off */
4208 + TXA_INT_T_STEP = 1<<3, /* Tx Arb Interval Timer Step */
4209 + TXA_LIM_T_ON = 1<<2, /* Tx Arb Limit Timer Test On */
4210 + TXA_LIM_T_OFF = 1<<1, /* Tx Arb Limit Timer Test Off */
4211 + TXA_LIM_T_STEP = 1<<0, /* Tx Arb Limit Timer Step */
4212 +};
4213 +
4214 +/* TXA_STAT 8 bit Tx Arbiter Status Register */
4215 +enum {
4216 + TXA_PRIO_XS = 1<<0, /* sync queue has prio to send */
4217 +};
4218 +
4219 +
4220 +/* Q_BC 32 bit Current Byte Counter */
4221 +
4222 +/* BMU Control Status Registers */
4223 +/* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
4224 +/* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
4225 +/* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
4226 +/* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
4227 +/* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
4228 +/* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
4229 +/* Q_CSR 32 bit BMU Control/Status Register */
4230 +
4231 +enum {
4232 + CSR_SV_IDLE = 1<<24, /* BMU SM Idle */
4233 +
4234 + CSR_DESC_CLR = 1<<21, /* Clear Reset for Descr */
4235 + CSR_DESC_SET = 1<<20, /* Set Reset for Descr */
4236 + CSR_FIFO_CLR = 1<<19, /* Clear Reset for FIFO */
4237 + CSR_FIFO_SET = 1<<18, /* Set Reset for FIFO */
4238 + CSR_HPI_RUN = 1<<17, /* Release HPI SM */
4239 + CSR_HPI_RST = 1<<16, /* Reset HPI SM to Idle */
4240 + CSR_SV_RUN = 1<<15, /* Release Supervisor SM */
4241 + CSR_SV_RST = 1<<14, /* Reset Supervisor SM */
4242 + CSR_DREAD_RUN = 1<<13, /* Release Descr Read SM */
4243 + CSR_DREAD_RST = 1<<12, /* Reset Descr Read SM */
4244 + CSR_DWRITE_RUN = 1<<11, /* Release Descr Write SM */
4245 + CSR_DWRITE_RST = 1<<10, /* Reset Descr Write SM */
4246 + CSR_TRANS_RUN = 1<<9, /* Release Transfer SM */
4247 + CSR_TRANS_RST = 1<<8, /* Reset Transfer SM */
4248 + CSR_ENA_POL = 1<<7, /* Enable Descr Polling */
4249 + CSR_DIS_POL = 1<<6, /* Disable Descr Polling */
4250 + CSR_STOP = 1<<5, /* Stop Rx/Tx Queue */
4251 + CSR_START = 1<<4, /* Start Rx/Tx Queue */
4252 + CSR_IRQ_CL_P = 1<<3, /* (Rx) Clear Parity IRQ */
4253 + CSR_IRQ_CL_B = 1<<2, /* Clear EOB IRQ */
4254 + CSR_IRQ_CL_F = 1<<1, /* Clear EOF IRQ */
4255 + CSR_IRQ_CL_C = 1<<0, /* Clear ERR IRQ */
4256 +};
4257 +
4258 +#define CSR_SET_RESET (CSR_DESC_SET | CSR_FIFO_SET | CSR_HPI_RST |\
4259 + CSR_SV_RST | CSR_DREAD_RST | CSR_DWRITE_RST |\
4260 + CSR_TRANS_RST)
4261 +#define CSR_CLR_RESET (CSR_DESC_CLR | CSR_FIFO_CLR | CSR_HPI_RUN |\
4262 + CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\
4263 + CSR_TRANS_RUN)
4264 +
4265 +/* Q_F 32 bit Flag Register */
4266 +enum {
4267 + F_ALM_FULL = 1<<27, /* Rx FIFO: almost full */
4268 + F_EMPTY = 1<<27, /* Tx FIFO: empty flag */
4269 + F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */
4270 + F_WM_REACHED = 1<<25, /* Watermark reached */
4271 +
4272 + F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */
4273 + F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */
4274 +};
4275 +
4276 +/* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
4277 +/* RB_START 32 bit RAM Buffer Start Address */
4278 +/* RB_END 32 bit RAM Buffer End Address */
4279 +/* RB_WP 32 bit RAM Buffer Write Pointer */
4280 +/* RB_RP 32 bit RAM Buffer Read Pointer */
4281 +/* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
4282 +/* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
4283 +/* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
4284 +/* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
4285 +/* RB_PC 32 bit RAM Buffer Packet Counter */
4286 +/* RB_LEV 32 bit RAM Buffer Level Register */
4287 +
4288 +#define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
4289 +/* RB_TST2 8 bit RAM Buffer Test Register 2 */
4290 +/* RB_TST1 8 bit RAM Buffer Test Register 1 */
4291 +
4292 +/* RB_CTRL 8 bit RAM Buffer Control Register */
4293 +enum {
4294 + RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
4295 + RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
4296 + RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
4297 + RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
4298 + RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
4299 + RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
4300 +};
4301 +
4302 +/* Transmit MAC FIFO and Transmit LED Registers (GENESIS only), */
4303 +enum {
4304 + TX_MFF_EA = 0x0d00,/* 32 bit Transmit MAC FIFO End Address */
4305 + TX_MFF_WP = 0x0d04,/* 32 bit Transmit MAC FIFO WR Pointer */
4306 + TX_MFF_WSP = 0x0d08,/* 32 bit Transmit MAC FIFO WR Shadow Ptr */
4307 + TX_MFF_RP = 0x0d0c,/* 32 bit Transmit MAC FIFO RD Pointer */
4308 + TX_MFF_PC = 0x0d10,/* 32 bit Transmit MAC FIFO Packet Cnt */
4309 + TX_MFF_LEV = 0x0d14,/* 32 bit Transmit MAC FIFO Level */
4310 + TX_MFF_CTRL1 = 0x0d18,/* 16 bit Transmit MAC FIFO Ctrl Reg 1 */
4311 + TX_MFF_WAF = 0x0d1a,/* 8 bit Transmit MAC Wait after flush */
4312 +
4313 + TX_MFF_CTRL2 = 0x0d1c,/* 8 bit Transmit MAC FIFO Ctrl Reg 2 */
4314 + TX_MFF_TST1 = 0x0d1d,/* 8 bit Transmit MAC FIFO Test Reg 1 */
4315 + TX_MFF_TST2 = 0x0d1e,/* 8 bit Transmit MAC FIFO Test Reg 2 */
4316 +
4317 + TX_LED_INI = 0x0d20,/* 32 bit Transmit LED Cnt Init Value */
4318 + TX_LED_VAL = 0x0d24,/* 32 bit Transmit LED Cnt Current Val */
4319 + TX_LED_CTRL = 0x0d28,/* 8 bit Transmit LED Cnt Control Reg */
4320 + TX_LED_TST = 0x0d29,/* 8 bit Transmit LED Cnt Test Reg */
4321 +};
4322 +
4323 +/* Counter and Timer constants, for a host clock of 62.5 MHz */
4324 +#define SK_XMIT_DUR 0x002faf08UL /* 50 ms */
4325 +#define SK_BLK_DUR 0x01dcd650UL /* 500 ms */
4326 +
4327 +#define SK_DPOLL_DEF 0x00ee6b28UL /* 250 ms at 62.5 MHz */
4328 +
4329 +#define SK_DPOLL_MAX 0x00ffffffUL /* 268 ms at 62.5 MHz */
4330 + /* 215 ms at 78.12 MHz */
4331 +
4332 +#define SK_FACT_62 100 /* is given in percent */
4333 +#define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */
4334 +#define SK_FACT_78 125 /* on YUKON: 78.12 MHz */
4335 +
4336 +
4337 +/* Transmit GMAC FIFO (YUKON only) */
4338 +enum {
4339 + TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
4340 + TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
4341 + TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
4342 +
4343 + TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
4344 + TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
4345 + TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
4346 +
4347 + TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
4348 + TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
4349 + TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
4350 +
4351 + /* Descriptor Poll Timer Registers */
4352 + B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
4353 + B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
4354 + B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
4355 +
4356 + B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
4357 +
4358 + /* Time Stamp Timer Registers (YUKON only) */
4359 + GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
4360 + GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
4361 + GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
4362 +};
4363 +
4364 +/* Status BMU Registers (Yukon-2 only)*/
4365 +enum {
4366 + STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */
4367 + STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */
4368 + /* 0x0e85 - 0x0e86: reserved */
4369 + STAT_LIST_ADDR_LO = 0x0e88,/* 32 bit Status List Start Addr (low) */
4370 + STAT_LIST_ADDR_HI = 0x0e8c,/* 32 bit Status List Start Addr (high) */
4371 + STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */
4372 + STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */
4373 + STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */
4374 + STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */
4375 + STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */
4376 + STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */
4377 +
4378 +/* FIFO Control/Status Registers (Yukon-2 only)*/
4379 + STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */
4380 + STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */
4381 + STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */
4382 + STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */
4383 + STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */
4384 + STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */
4385 + STAT_FIFO_ISR_WM = 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */
4386 +
4387 +/* Level and ISR Timer Registers (Yukon-2 only)*/
4388 + STAT_LEV_TIMER_INI = 0x0eb0,/* 32 bit Level Timer Init. Value Reg */
4389 + STAT_LEV_TIMER_CNT = 0x0eb4,/* 32 bit Level Timer Counter Reg */
4390 + STAT_LEV_TIMER_CTRL = 0x0eb8,/* 8 bit Level Timer Control Reg */
4391 + STAT_LEV_TIMER_TEST = 0x0eb9,/* 8 bit Level Timer Test Reg */
4392 + STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */
4393 + STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */
4394 + STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */
4395 + STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */
4396 + STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */
4397 + STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */
4398 + STAT_ISR_TIMER_CTRL = 0x0ed8,/* 8 bit ISR Timer Control Reg */
4399 + STAT_ISR_TIMER_TEST = 0x0ed9,/* 8 bit ISR Timer Test Reg */
4400 +
4401 + ST_LAST_IDX_MASK = 0x007f,/* Last Index Mask */
4402 + ST_TXRP_IDX_MASK = 0x0fff,/* Tx Report Index Mask */
4403 + ST_TXTH_IDX_MASK = 0x0fff,/* Tx Threshold Index Mask */
4404 + ST_WM_IDX_MASK = 0x3f,/* FIFO Watermark Index Mask */
4405 +};
4406 +
4407 +enum {
4408 + LINKLED_OFF = 0x01,
4409 + LINKLED_ON = 0x02,
4410 + LINKLED_LINKSYNC_OFF = 0x04,
4411 + LINKLED_LINKSYNC_ON = 0x08,
4412 + LINKLED_BLINK_OFF = 0x10,
4413 + LINKLED_BLINK_ON = 0x20,
4414 +};
4415 +
4416 +/* GMAC and GPHY Control Registers (YUKON only) */
4417 +enum {
4418 + GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
4419 + GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
4420 + GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
4421 + GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
4422 + GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
4423 +
4424 +/* Wake-up Frame Pattern Match Control Registers (YUKON only) */
4425 +
4426 + WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
4427 +
4428 + WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
4429 + WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
4430 + WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
4431 + WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
4432 + WOL_PATT_PME = 0x0f2a,/* 8 bit WOL PME Match Enable (Yukon-2) */
4433 + WOL_PATT_ASFM = 0x0f2b,/* 8 bit WOL ASF Match Enable (Yukon-2) */
4434 + WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
4435 +
4436 +/* WOL Pattern Length Registers (YUKON only) */
4437 +
4438 + WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
4439 + WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
4440 +
4441 +/* WOL Pattern Counter Registers (YUKON only) */
4442 +
4443 + WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
4444 + WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
4445 +};
4446 +
4447 +enum {
4448 + WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
4449 + WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
4450 +};
4451 +
4452 +enum {
4453 + BASE_XMAC_1 = 0x2000,/* XMAC 1 registers */
4454 + BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
4455 + BASE_XMAC_2 = 0x3000,/* XMAC 2 registers */
4456 + BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
4457 +};
4458 +
4459 +/*
4460 + * Receive Frame Status Encoding
4461 + */
4462 +enum {
4463 + XMR_FS_LEN = 0x3fff<<18, /* Bit 31..18: Rx Frame Length */
4464 + XMR_FS_2L_VLAN = 1<<17, /* Bit 17: tagged wh 2Lev VLAN ID*/
4465 + XMR_FS_1_VLAN = 1<<16, /* Bit 16: tagged wh 1ev VLAN ID*/
4466 + XMR_FS_BC = 1<<15, /* Bit 15: Broadcast Frame */
4467 + XMR_FS_MC = 1<<14, /* Bit 14: Multicast Frame */
4468 + XMR_FS_UC = 1<<13, /* Bit 13: Unicast Frame */
4469 +
4470 + XMR_FS_BURST = 1<<11, /* Bit 11: Burst Mode */
4471 + XMR_FS_CEX_ERR = 1<<10, /* Bit 10: Carrier Ext. Error */
4472 + XMR_FS_802_3 = 1<<9, /* Bit 9: 802.3 Frame */
4473 + XMR_FS_COL_ERR = 1<<8, /* Bit 8: Collision Error */
4474 + XMR_FS_CAR_ERR = 1<<7, /* Bit 7: Carrier Event Error */
4475 + XMR_FS_LEN_ERR = 1<<6, /* Bit 6: In-Range Length Error */
4476 + XMR_FS_FRA_ERR = 1<<5, /* Bit 5: Framing Error */
4477 + XMR_FS_RUNT = 1<<4, /* Bit 4: Runt Frame */
4478 + XMR_FS_LNG_ERR = 1<<3, /* Bit 3: Giant (Jumbo) Frame */
4479 + XMR_FS_FCS_ERR = 1<<2, /* Bit 2: Frame Check Sequ Err */
4480 + XMR_FS_ERR = 1<<1, /* Bit 1: Frame Error */
4481 + XMR_FS_MCTRL = 1<<0, /* Bit 0: MAC Control Packet */
4482 +
4483 +/*
4484 + * XMR_FS_ERR will be set if
4485 + * XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT,
4486 + * XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR_FS_CEX_ERR
4487 + * is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR will issue
4488 + * XMR_FS_ERR unless the corresponding bit in the Receive Command
4489 + * Register is set.
4490 + */
4491 +};
4492 +
4493 +/*
4494 +,* XMAC-PHY Registers, indirect addressed over the XMAC
4495 + */
4496 +enum {
4497 + PHY_XMAC_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
4498 + PHY_XMAC_STAT = 0x01,/* 16 bit r/w PHY Status Register */
4499 + PHY_XMAC_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
4500 + PHY_XMAC_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
4501 + PHY_XMAC_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
4502 + PHY_XMAC_AUNE_LP = 0x05,/* 16 bit r/o Link Partner Abi Reg */
4503 + PHY_XMAC_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
4504 + PHY_XMAC_NEPG = 0x07,/* 16 bit r/w Next Page Register */
4505 + PHY_XMAC_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
4506 +
4507 + PHY_XMAC_EXT_STAT = 0x0f,/* 16 bit r/o Ext Status Register */
4508 + PHY_XMAC_RES_ABI = 0x10,/* 16 bit r/o PHY Resolved Ability */
4509 +};
4510 +/*
4511 + * Broadcom-PHY Registers, indirect addressed over XMAC
4512 + */
4513 +enum {
4514 + PHY_BCOM_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
4515 + PHY_BCOM_STAT = 0x01,/* 16 bit r/o PHY Status Register */
4516 + PHY_BCOM_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
4517 + PHY_BCOM_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
4518 + PHY_BCOM_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
4519 + PHY_BCOM_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
4520 + PHY_BCOM_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
4521 + PHY_BCOM_NEPG = 0x07,/* 16 bit r/w Next Page Register */
4522 + PHY_BCOM_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
4523 + /* Broadcom-specific registers */
4524 + PHY_BCOM_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
4525 + PHY_BCOM_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
4526 + PHY_BCOM_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
4527 + PHY_BCOM_P_EXT_CTRL = 0x10,/* 16 bit r/w PHY Extended Ctrl Reg */
4528 + PHY_BCOM_P_EXT_STAT = 0x11,/* 16 bit r/o PHY Extended Stat Reg */
4529 + PHY_BCOM_RE_CTR = 0x12,/* 16 bit r/w Receive Error Counter */
4530 + PHY_BCOM_FC_CTR = 0x13,/* 16 bit r/w False Carrier Sense Cnt */
4531 + PHY_BCOM_RNO_CTR = 0x14,/* 16 bit r/w Receiver NOT_OK Cnt */
4532 +
4533 + PHY_BCOM_AUX_CTRL = 0x18,/* 16 bit r/w Auxiliary Control Reg */
4534 + PHY_BCOM_AUX_STAT = 0x19,/* 16 bit r/o Auxiliary Stat Summary */
4535 + PHY_BCOM_INT_STAT = 0x1a,/* 16 bit r/o Interrupt Status Reg */
4536 + PHY_BCOM_INT_MASK = 0x1b,/* 16 bit r/w Interrupt Mask Reg */
4537 +};
4538 +
4539 +/*
4540 + * Marvel-PHY Registers, indirect addressed over GMAC
4541 + */
4542 +enum {
4543 + PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
4544 + PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
4545 + PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
4546 + PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
4547 + PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
4548 + PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
4549 + PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
4550 + PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
4551 + PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
4552 + /* Marvel-specific registers */
4553 + PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
4554 + PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
4555 + PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
4556 + PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
4557 + PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
4558 + PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
4559 + PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
4560 + PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
4561 + PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
4562 + PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
4563 + PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
4564 + PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
4565 + PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
4566 + PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
4567 + PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
4568 + PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
4569 + PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
4570 + PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
4571 +
4572 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
4573 + PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
4574 + PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
4575 + PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
4576 + PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
4577 + PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
4578 +};
4579 +
4580 +/* Level One-PHY Registers, indirect addressed over XMAC */
4581 +enum {
4582 + PHY_LONE_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
4583 + PHY_LONE_STAT = 0x01,/* 16 bit r/o PHY Status Register */
4584 + PHY_LONE_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
4585 + PHY_LONE_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
4586 + PHY_LONE_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
4587 + PHY_LONE_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
4588 + PHY_LONE_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
4589 + PHY_LONE_NEPG = 0x07,/* 16 bit r/w Next Page Register */
4590 + PHY_LONE_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
4591 + /* Level One-specific registers */
4592 + PHY_LONE_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
4593 + PHY_LONE_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
4594 + PHY_LONE_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
4595 + PHY_LONE_PORT_CFG = 0x10,/* 16 bit r/w Port Configuration Reg*/
4596 + PHY_LONE_Q_STAT = 0x11,/* 16 bit r/o Quick Status Reg */
4597 + PHY_LONE_INT_ENAB = 0x12,/* 16 bit r/w Interrupt Enable Reg */
4598 + PHY_LONE_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
4599 + PHY_LONE_LED_CFG = 0x14,/* 16 bit r/w LED Configuration Reg */
4600 + PHY_LONE_PORT_CTRL = 0x15,/* 16 bit r/w Port Control Reg */
4601 + PHY_LONE_CIM = 0x16,/* 16 bit r/o CIM Reg */
4602 +};
4603 +
4604 +/* National-PHY Registers, indirect addressed over XMAC */
4605 +enum {
4606 + PHY_NAT_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
4607 + PHY_NAT_STAT = 0x01,/* 16 bit r/w PHY Status Register */
4608 + PHY_NAT_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
4609 + PHY_NAT_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
4610 + PHY_NAT_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
4611 + PHY_NAT_AUNE_LP = 0x05,/* 16 bit r/o Link Partner Ability Reg */
4612 + PHY_NAT_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
4613 + PHY_NAT_NEPG = 0x07,/* 16 bit r/w Next Page Register */
4614 + PHY_NAT_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner Reg */
4615 + /* National-specific registers */
4616 + PHY_NAT_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
4617 + PHY_NAT_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
4618 + PHY_NAT_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Register */
4619 + PHY_NAT_EXT_CTRL1 = 0x10,/* 16 bit r/o Extended Control Reg1 */
4620 + PHY_NAT_Q_STAT1 = 0x11,/* 16 bit r/o Quick Status Reg1 */
4621 + PHY_NAT_10B_OP = 0x12,/* 16 bit r/o 10Base-T Operations Reg */
4622 + PHY_NAT_EXT_CTRL2 = 0x13,/* 16 bit r/o Extended Control Reg1 */
4623 + PHY_NAT_Q_STAT2 = 0x14,/* 16 bit r/o Quick Status Reg2 */
4624 +
4625 + PHY_NAT_PHY_ADDR = 0x19,/* 16 bit r/o PHY Address Register */
4626 +};
4627 +
4628 +enum {
4629 + PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
4630 + PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
4631 + PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
4632 + PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
4633 + PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
4634 + PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
4635 + PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
4636 + PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
4637 + PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
4638 + PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
4639 +};
4640 +
4641 +enum {
4642 + PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
4643 + PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
4644 + PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
4645 +};
4646 +
4647 +enum {
4648 + PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
4649 +
4650 + PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
4651 + PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
4652 + PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */
4653 + PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
4654 + PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
4655 + PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
4656 + PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
4657 +};
4658 +
4659 +enum {
4660 + PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
4661 + PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
4662 + PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
4663 +};
4664 +
4665 +/* different Broadcom PHY Ids */
4666 +enum {
4667 + PHY_BCOM_ID1_A1 = 0x6041,
4668 + PHY_BCOM_ID1_B2 = 0x6043,
4669 + PHY_BCOM_ID1_C0 = 0x6044,
4670 + PHY_BCOM_ID1_C5 = 0x6047,
4671 +};
4672 +
4673 +/* different Marvell PHY Ids */
4674 +enum {
4675 + PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
4676 + PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
4677 + PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
4678 + PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
4679 + PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
4680 +};
4681 +
4682 +enum {
4683 + PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
4684 + PHY_X_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
4685 + PHY_X_AN_RFB = 3<<12,/* Bit 13..12: Remote Fault Bits */
4686 +
4687 + PHY_X_AN_PAUSE = 3<<7,/* Bit 8.. 7: Pause Bits */
4688 + PHY_X_AN_HD = 1<<6, /* Bit 6: Half Duplex */
4689 + PHY_X_AN_FD = 1<<5, /* Bit 5: Full Duplex */
4690 +};
4691 +
4692 +enum {
4693 + PHY_B_AN_RF = 1<<13, /* Bit 13: Remote Fault */
4694 +
4695 + PHY_B_AN_ASP = 1<<11, /* Bit 11: Asymmetric Pause */
4696 + PHY_B_AN_PC = 1<<10, /* Bit 10: Pause Capable */
4697 + PHY_B_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
4698 +};
4699 +
4700 +enum {
4701 + PHY_L_AN_RF = 1<<13, /* Bit 13: Remote Fault */
4702 + /* Bit 12: reserved */
4703 + PHY_L_AN_ASP = 1<<11, /* Bit 11: Asymmetric Pause */
4704 + PHY_L_AN_PC = 1<<10, /* Bit 10: Pause Capable */
4705 +
4706 + PHY_L_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
4707 +};
4708 +
4709 +/* PHY_NAT_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement */
4710 +/* PHY_NAT_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/
4711 +/* PHY_AN_NXT_PG (see XMAC) Bit 15: Request Next Page */
4712 +enum {
4713 + PHY_N_AN_RF = 1<<13, /* Bit 13: Remote Fault */
4714 +
4715 + PHY_N_AN_100F = 1<<11, /* Bit 11: 100Base-T2 FD Support */
4716 + PHY_N_AN_100H = 1<<10, /* Bit 10: 100Base-T2 HD Support */
4717 +
4718 + PHY_N_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
4719 +};
4720 +
4721 +/* field type definition for PHY_x_AN_SEL */
4722 +enum {
4723 + PHY_SEL_TYPE = 1, /* 00001 = Ethernet */
4724 +};
4725 +
4726 +enum {
4727 + PHY_ANE_LP_NP = 1<<3, /* Bit 3: Link Partner can Next Page */
4728 + PHY_ANE_LOC_NP = 1<<2, /* Bit 2: Local PHY can Next Page */
4729 + PHY_ANE_RX_PG = 1<<1, /* Bit 1: Page Received */
4730 +};
4731 +
4732 +enum {
4733 + PHY_ANE_PAR_DF = 1<<4, /* Bit 4: Parallel Detection Fault */
4734 +
4735 + PHY_ANE_LP_CAP = 1<<0, /* Bit 0: Link Partner Auto-Neg. Cap. */
4736 +};
4737 +
4738 +enum {
4739 + PHY_NP_MORE = 1<<15, /* Bit 15: More, Next Pages to follow */
4740 + PHY_NP_ACK1 = 1<<14, /* Bit 14: (ro) Ack1, for receiving a message */
4741 + PHY_NP_MSG_VAL = 1<<13, /* Bit 13: Message Page valid */
4742 + PHY_NP_ACK2 = 1<<12, /* Bit 12: Ack2, comply with msg content */
4743 + PHY_NP_TOG = 1<<11, /* Bit 11: Toggle Bit, ensure sync */
4744 + PHY_NP_MSG = 0x07ff, /* Bit 10..0: Message from/to Link Partner */
4745 +};
4746 +
4747 +enum {
4748 + PHY_X_EX_FD = 1<<15, /* Bit 15: Device Supports Full Duplex */
4749 + PHY_X_EX_HD = 1<<14, /* Bit 14: Device Supports Half Duplex */
4750 +};
4751 +
4752 +enum {
4753 + PHY_X_RS_PAUSE = 3<<7,/* Bit 8..7: selected Pause Mode */
4754 + PHY_X_RS_HD = 1<<6, /* Bit 6: Half Duplex Mode selected */
4755 + PHY_X_RS_FD = 1<<5, /* Bit 5: Full Duplex Mode selected */
4756 + PHY_X_RS_ABLMIS = 1<<4, /* Bit 4: duplex or pause cap mismatch */
4757 + PHY_X_RS_PAUMIS = 1<<3, /* Bit 3: pause capability mismatch */
4758 +};
4759 +
4760 +/** Remote Fault Bits (PHY_X_AN_RFB) encoding */
4761 +enum {
4762 + X_RFB_OK = 0<<12,/* Bit 13..12 No errors, Link OK */
4763 + X_RFB_LF = 1<<12, /* Bit 13..12 Link Failure */
4764 + X_RFB_OFF = 2<<12,/* Bit 13..12 Offline */
4765 + X_RFB_AN_ERR = 3<<12,/* Bit 13..12 Auto-Negotiation Error */
4766 +};
4767 +
4768 +/* Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding */
4769 +enum {
4770 + PHY_X_P_NO_PAUSE = 0<<7,/* Bit 8..7: no Pause Mode */
4771 + PHY_X_P_SYM_MD = 1<<7, /* Bit 8..7: symmetric Pause Mode */
4772 + PHY_X_P_ASYM_MD = 2<<7,/* Bit 8..7: asymmetric Pause Mode */
4773 + PHY_X_P_BOTH_MD = 3<<7,/* Bit 8..7: both Pause Mode */
4774 +};
4775 +
4776 +
4777 +/* Broadcom-Specific */
4778 +/***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
4779 +enum {
4780 + PHY_B_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
4781 + PHY_B_1000C_MSE = 1<<12, /* Bit 12: Master/Slave Enable */
4782 + PHY_B_1000C_MSC = 1<<11, /* Bit 11: M/S Configuration */
4783 + PHY_B_1000C_RD = 1<<10, /* Bit 10: Repeater/DTE */
4784 + PHY_B_1000C_AFD = 1<<9, /* Bit 9: Advertise Full Duplex */
4785 + PHY_B_1000C_AHD = 1<<8, /* Bit 8: Advertise Half Duplex */
4786 +};
4787 +
4788 +/***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
4789 +/***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
4790 +enum {
4791 + PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
4792 + PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
4793 + PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
4794 + PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
4795 + PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
4796 + PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
4797 + /* Bit 9..8: reserved */
4798 + PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
4799 +};
4800 +
4801 +/***** PHY_BCOM_EXT_STAT 16 bit r/o Extended Status Register *****/
4802 +enum {
4803 + PHY_B_ES_X_FD_CAP = 1<<15, /* Bit 15: 1000Base-X FD capable */
4804 + PHY_B_ES_X_HD_CAP = 1<<14, /* Bit 14: 1000Base-X HD capable */
4805 + PHY_B_ES_T_FD_CAP = 1<<13, /* Bit 13: 1000Base-T FD capable */
4806 + PHY_B_ES_T_HD_CAP = 1<<12, /* Bit 12: 1000Base-T HD capable */
4807 +};
4808 +
4809 +/***** PHY_BCOM_P_EXT_CTRL 16 bit r/w PHY Extended Control Reg *****/
4810 +enum {
4811 + PHY_B_PEC_MAC_PHY = 1<<15, /* Bit 15: 10BIT/GMI-Interface */
4812 + PHY_B_PEC_DIS_CROSS = 1<<14, /* Bit 14: Disable MDI Crossover */
4813 + PHY_B_PEC_TX_DIS = 1<<13, /* Bit 13: Tx output Disabled */
4814 + PHY_B_PEC_INT_DIS = 1<<12, /* Bit 12: Interrupts Disabled */
4815 + PHY_B_PEC_F_INT = 1<<11, /* Bit 11: Force Interrupt */
4816 + PHY_B_PEC_BY_45 = 1<<10, /* Bit 10: Bypass 4B5B-Decoder */
4817 + PHY_B_PEC_BY_SCR = 1<<9, /* Bit 9: Bypass Scrambler */
4818 + PHY_B_PEC_BY_MLT3 = 1<<8, /* Bit 8: Bypass MLT3 Encoder */
4819 + PHY_B_PEC_BY_RXA = 1<<7, /* Bit 7: Bypass Rx Alignm. */
4820 + PHY_B_PEC_RES_SCR = 1<<6, /* Bit 6: Reset Scrambler */
4821 + PHY_B_PEC_EN_LTR = 1<<5, /* Bit 5: Ena LED Traffic Mode */
4822 + PHY_B_PEC_LED_ON = 1<<4, /* Bit 4: Force LED's on */
4823 + PHY_B_PEC_LED_OFF = 1<<3, /* Bit 3: Force LED's off */
4824 + PHY_B_PEC_EX_IPG = 1<<2, /* Bit 2: Extend Tx IPG Mode */
4825 + PHY_B_PEC_3_LED = 1<<1, /* Bit 1: Three Link LED mode */
4826 + PHY_B_PEC_HIGH_LA = 1<<0, /* Bit 0: GMII FIFO Elasticy */
4827 +};
4828 +
4829 +/***** PHY_BCOM_P_EXT_STAT 16 bit r/o PHY Extended Status Reg *****/
4830 +enum {
4831 + PHY_B_PES_CROSS_STAT = 1<<13, /* Bit 13: MDI Crossover Status */
4832 + PHY_B_PES_INT_STAT = 1<<12, /* Bit 12: Interrupt Status */
4833 + PHY_B_PES_RRS = 1<<11, /* Bit 11: Remote Receiver Stat. */
4834 + PHY_B_PES_LRS = 1<<10, /* Bit 10: Local Receiver Stat. */
4835 + PHY_B_PES_LOCKED = 1<<9, /* Bit 9: Locked */
4836 + PHY_B_PES_LS = 1<<8, /* Bit 8: Link Status */
4837 + PHY_B_PES_RF = 1<<7, /* Bit 7: Remote Fault */
4838 + PHY_B_PES_CE_ER = 1<<6, /* Bit 6: Carrier Ext Error */
4839 + PHY_B_PES_BAD_SSD = 1<<5, /* Bit 5: Bad SSD */
4840 + PHY_B_PES_BAD_ESD = 1<<4, /* Bit 4: Bad ESD */
4841 + PHY_B_PES_RX_ER = 1<<3, /* Bit 3: Receive Error */
4842 + PHY_B_PES_TX_ER = 1<<2, /* Bit 2: Transmit Error */
4843 + PHY_B_PES_LOCK_ER = 1<<1, /* Bit 1: Lock Error */
4844 + PHY_B_PES_MLT3_ER = 1<<0, /* Bit 0: MLT3 code Error */
4845 +};
4846 +
4847 +/***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/
4848 +enum {
4849 + PHY_B_FC_CTR = 0xff, /* Bit 7..0: False Carrier Counter */
4850 +
4851 +/***** PHY_BCOM_RNO_CTR 16 bit r/w Receive NOT_OK Counter *****/
4852 + PHY_B_RC_LOC_MSK = 0xff00, /* Bit 15..8: Local Rx NOT_OK cnt */
4853 + PHY_B_RC_REM_MSK = 0x00ff, /* Bit 7..0: Remote Rx NOT_OK cnt */
4854 +
4855 +/***** PHY_BCOM_AUX_CTRL 16 bit r/w Auxiliary Control Reg *****/
4856 + PHY_B_AC_L_SQE = 1<<15, /* Bit 15: Low Squelch */
4857 + PHY_B_AC_LONG_PACK = 1<<14, /* Bit 14: Rx Long Packets */
4858 + PHY_B_AC_ER_CTRL = 3<<12,/* Bit 13..12: Edgerate Control */
4859 + /* Bit 11: reserved */
4860 + PHY_B_AC_TX_TST = 1<<10, /* Bit 10: Tx test bit, always 1 */
4861 + /* Bit 9.. 8: reserved */
4862 + PHY_B_AC_DIS_PRF = 1<<7, /* Bit 7: dis part resp filter */
4863 + /* Bit 6: reserved */
4864 + PHY_B_AC_DIS_PM = 1<<5, /* Bit 5: dis power management */
4865 + /* Bit 4: reserved */
4866 + PHY_B_AC_DIAG = 1<<3, /* Bit 3: Diagnostic Mode */
4867 +};
4868 +
4869 +/***** PHY_BCOM_AUX_STAT 16 bit r/o Auxiliary Status Reg *****/
4870 +enum {
4871 + PHY_B_AS_AN_C = 1<<15, /* Bit 15: AutoNeg complete */
4872 + PHY_B_AS_AN_CA = 1<<14, /* Bit 14: AN Complete Ack */
4873 + PHY_B_AS_ANACK_D = 1<<13, /* Bit 13: AN Ack Detect */
4874 + PHY_B_AS_ANAB_D = 1<<12, /* Bit 12: AN Ability Detect */
4875 + PHY_B_AS_NPW = 1<<11, /* Bit 11: AN Next Page Wait */
4876 + PHY_B_AS_AN_RES_MSK = 7<<8,/* Bit 10..8: AN HDC */
4877 + PHY_B_AS_PDF = 1<<7, /* Bit 7: Parallel Detect. Fault */
4878 + PHY_B_AS_RF = 1<<6, /* Bit 6: Remote Fault */
4879 + PHY_B_AS_ANP_R = 1<<5, /* Bit 5: AN Page Received */
4880 + PHY_B_AS_LP_ANAB = 1<<4, /* Bit 4: LP AN Ability */
4881 + PHY_B_AS_LP_NPAB = 1<<3, /* Bit 3: LP Next Page Ability */
4882 + PHY_B_AS_LS = 1<<2, /* Bit 2: Link Status */
4883 + PHY_B_AS_PRR = 1<<1, /* Bit 1: Pause Resolution-Rx */
4884 + PHY_B_AS_PRT = 1<<0, /* Bit 0: Pause Resolution-Tx */
4885 +};
4886 +#define PHY_B_AS_PAUSE_MSK (PHY_B_AS_PRR | PHY_B_AS_PRT)
4887 +
4888 +/***** PHY_BCOM_INT_STAT 16 bit r/o Interrupt Status Reg *****/
4889 +/***** PHY_BCOM_INT_MASK 16 bit r/w Interrupt Mask Reg *****/
4890 +enum {
4891 + PHY_B_IS_PSE = 1<<14, /* Bit 14: Pair Swap Error */
4892 + PHY_B_IS_MDXI_SC = 1<<13, /* Bit 13: MDIX Status Change */
4893 + PHY_B_IS_HCT = 1<<12, /* Bit 12: counter above 32k */
4894 + PHY_B_IS_LCT = 1<<11, /* Bit 11: counter above 128 */
4895 + PHY_B_IS_AN_PR = 1<<10, /* Bit 10: Page Received */
4896 + PHY_B_IS_NO_HDCL = 1<<9, /* Bit 9: No HCD Link */
4897 + PHY_B_IS_NO_HDC = 1<<8, /* Bit 8: No HCD */
4898 + PHY_B_IS_NEG_USHDC = 1<<7, /* Bit 7: Negotiated Unsup. HCD */
4899 + PHY_B_IS_SCR_S_ER = 1<<6, /* Bit 6: Scrambler Sync Error */
4900 + PHY_B_IS_RRS_CHANGE = 1<<5, /* Bit 5: Remote Rx Stat Change */
4901 + PHY_B_IS_LRS_CHANGE = 1<<4, /* Bit 4: Local Rx Stat Change */
4902 + PHY_B_IS_DUP_CHANGE = 1<<3, /* Bit 3: Duplex Mode Change */
4903 + PHY_B_IS_LSP_CHANGE = 1<<2, /* Bit 2: Link Speed Change */
4904 + PHY_B_IS_LST_CHANGE = 1<<1, /* Bit 1: Link Status Changed */
4905 + PHY_B_IS_CRC_ER = 1<<0, /* Bit 0: CRC Error */
4906 +};
4907 +#define PHY_B_DEF_MSK (~(PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
4908 +
4909 +/* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */
4910 +enum {
4911 + PHY_B_P_NO_PAUSE = 0<<10,/* Bit 11..10: no Pause Mode */
4912 + PHY_B_P_SYM_MD = 1<<10, /* Bit 11..10: symmetric Pause Mode */
4913 + PHY_B_P_ASYM_MD = 2<<10,/* Bit 11..10: asymmetric Pause Mode */
4914 + PHY_B_P_BOTH_MD = 3<<10,/* Bit 11..10: both Pause Mode */
4915 +};
4916 +/*
4917 + * Resolved Duplex mode and Capabilities (Aux Status Summary Reg)
4918 + */
4919 +enum {
4920 + PHY_B_RES_1000FD = 7<<8,/* Bit 10..8: 1000Base-T Full Dup. */
4921 + PHY_B_RES_1000HD = 6<<8,/* Bit 10..8: 1000Base-T Half Dup. */
4922 +};
4923 +
4924 +/*
4925 + * Level One-Specific
4926 + */
4927 +/***** PHY_LONE_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
4928 +enum {
4929 + PHY_L_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
4930 + PHY_L_1000C_MSE = 1<<12, /* Bit 12: Master/Slave Enable */
4931 + PHY_L_1000C_MSC = 1<<11, /* Bit 11: M/S Configuration */
4932 + PHY_L_1000C_RD = 1<<10, /* Bit 10: Repeater/DTE */
4933 + PHY_L_1000C_AFD = 1<<9, /* Bit 9: Advertise Full Duplex */
4934 + PHY_L_1000C_AHD = 1<<8, /* Bit 8: Advertise Half Duplex */
4935 +};
4936 +
4937 +/***** PHY_LONE_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
4938 +enum {
4939 + PHY_L_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
4940 + PHY_L_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
4941 + PHY_L_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
4942 + PHY_L_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
4943 + PHY_L_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
4944 + PHY_L_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
4945 +
4946 + PHY_L_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
4947 +
4948 +/***** PHY_LONE_EXT_STAT 16 bit r/o Extended Status Register *****/
4949 + PHY_L_ES_X_FD_CAP = 1<<15, /* Bit 15: 1000Base-X FD capable */
4950 + PHY_L_ES_X_HD_CAP = 1<<14, /* Bit 14: 1000Base-X HD capable */
4951 + PHY_L_ES_T_FD_CAP = 1<<13, /* Bit 13: 1000Base-T FD capable */
4952 + PHY_L_ES_T_HD_CAP = 1<<12, /* Bit 12: 1000Base-T HD capable */
4953 +};
4954 +
4955 +/***** PHY_LONE_PORT_CFG 16 bit r/w Port Configuration Reg *****/
4956 +enum {
4957 + PHY_L_PC_REP_MODE = 1<<15, /* Bit 15: Repeater Mode */
4958 +
4959 + PHY_L_PC_TX_DIS = 1<<13, /* Bit 13: Tx output Disabled */
4960 + PHY_L_PC_BY_SCR = 1<<12, /* Bit 12: Bypass Scrambler */
4961 + PHY_L_PC_BY_45 = 1<<11, /* Bit 11: Bypass 4B5B-Decoder */
4962 + PHY_L_PC_JAB_DIS = 1<<10, /* Bit 10: Jabber Disabled */
4963 + PHY_L_PC_SQE = 1<<9, /* Bit 9: Enable Heartbeat */
4964 + PHY_L_PC_TP_LOOP = 1<<8, /* Bit 8: TP Loopback */
4965 + PHY_L_PC_SSS = 1<<7, /* Bit 7: Smart Speed Selection */
4966 + PHY_L_PC_FIFO_SIZE = 1<<6, /* Bit 6: FIFO Size */
4967 + PHY_L_PC_PRE_EN = 1<<5, /* Bit 5: Preamble Enable */
4968 + PHY_L_PC_CIM = 1<<4, /* Bit 4: Carrier Integrity Mon */
4969 + PHY_L_PC_10_SER = 1<<3, /* Bit 3: Use Serial Output */
4970 + PHY_L_PC_ANISOL = 1<<2, /* Bit 2: Unisolate Port */
4971 + PHY_L_PC_TEN_BIT = 1<<1, /* Bit 1: 10bit iface mode on */
4972 + PHY_L_PC_ALTCLOCK = 1<<0, /* Bit 0: (ro) ALTCLOCK Mode on */
4973 +};
4974 +
4975 +/***** PHY_LONE_Q_STAT 16 bit r/o Quick Status Reg *****/
4976 +enum {
4977 + PHY_L_QS_D_RATE = 3<<14,/* Bit 15..14: Data Rate */
4978 + PHY_L_QS_TX_STAT = 1<<13, /* Bit 13: Transmitting */
4979 + PHY_L_QS_RX_STAT = 1<<12, /* Bit 12: Receiving */
4980 + PHY_L_QS_COL_STAT = 1<<11, /* Bit 11: Collision */
4981 + PHY_L_QS_L_STAT = 1<<10, /* Bit 10: Link is up */
4982 + PHY_L_QS_DUP_MOD = 1<<9, /* Bit 9: Full/Half Duplex */
4983 + PHY_L_QS_AN = 1<<8, /* Bit 8: AutoNeg is On */
4984 + PHY_L_QS_AN_C = 1<<7, /* Bit 7: AN is Complete */
4985 + PHY_L_QS_LLE = 7<<4,/* Bit 6..4: Line Length Estim. */
4986 + PHY_L_QS_PAUSE = 1<<3, /* Bit 3: LP advertised Pause */
4987 + PHY_L_QS_AS_PAUSE = 1<<2, /* Bit 2: LP adv. asym. Pause */
4988 + PHY_L_QS_ISOLATE = 1<<1, /* Bit 1: CIM Isolated */
4989 + PHY_L_QS_EVENT = 1<<0, /* Bit 0: Event has occurred */
4990 +};
4991 +
4992 +/***** PHY_LONE_INT_ENAB 16 bit r/w Interrupt Enable Reg *****/
4993 +/***** PHY_LONE_INT_STAT 16 bit r/o Interrupt Status Reg *****/
4994 +enum {
4995 + PHY_L_IS_AN_F = 1<<13, /* Bit 13: Auto-Negotiation fault */
4996 + PHY_L_IS_CROSS = 1<<11, /* Bit 11: Crossover used */
4997 + PHY_L_IS_POL = 1<<10, /* Bit 10: Polarity correct. used */
4998 + PHY_L_IS_SS = 1<<9, /* Bit 9: Smart Speed Downgrade */
4999 + PHY_L_IS_CFULL = 1<<8, /* Bit 8: Counter Full */
5000 + PHY_L_IS_AN_C = 1<<7, /* Bit 7: AutoNeg Complete */
5001 + PHY_L_IS_SPEED = 1<<6, /* Bit 6: Speed Changed */
5002 + PHY_L_IS_DUP = 1<<5, /* Bit 5: Duplex Changed */
5003 + PHY_L_IS_LS = 1<<4, /* Bit 4: Link Status Changed */
5004 + PHY_L_IS_ISOL = 1<<3, /* Bit 3: Isolate Occured */
5005 + PHY_L_IS_MDINT = 1<<2, /* Bit 2: (ro) STAT: MII Int Pending */
5006 + PHY_L_IS_INTEN = 1<<1, /* Bit 1: ENAB: Enable IRQs */
5007 + PHY_L_IS_FORCE = 1<<0, /* Bit 0: ENAB: Force Interrupt */
5008 +};
5009 +
5010 +/* int. mask */
5011 +#define PHY_L_DEF_MSK (PHY_L_IS_LS | PHY_L_IS_ISOL | PHY_L_IS_INTEN)
5012 +
5013 +/***** PHY_LONE_LED_CFG 16 bit r/w LED Configuration Reg *****/
5014 +enum {
5015 + PHY_L_LC_LEDC = 3<<14,/* Bit 15..14: Col/Blink/On/Off */
5016 + PHY_L_LC_LEDR = 3<<12,/* Bit 13..12: Rx/Blink/On/Off */
5017 + PHY_L_LC_LEDT = 3<<10,/* Bit 11..10: Tx/Blink/On/Off */
5018 + PHY_L_LC_LEDG = 3<<8,/* Bit 9..8: Giga/Blink/On/Off */
5019 + PHY_L_LC_LEDS = 3<<6,/* Bit 7..6: 10-100/Blink/On/Off */
5020 + PHY_L_LC_LEDL = 3<<4,/* Bit 5..4: Link/Blink/On/Off */
5021 + PHY_L_LC_LEDF = 3<<2,/* Bit 3..2: Duplex/Blink/On/Off */
5022 + PHY_L_LC_PSTRECH= 1<<1, /* Bit 1: Strech LED Pulses */
5023 + PHY_L_LC_FREQ = 1<<0, /* Bit 0: 30/100 ms */
5024 +};
5025 +
5026 +/***** PHY_LONE_PORT_CTRL 16 bit r/w Port Control Reg *****/
5027 +enum {
5028 + PHY_L_PC_TX_TCLK = 1<<15, /* Bit 15: Enable TX_TCLK */
5029 + PHY_L_PC_ALT_NP = 1<<13, /* Bit 14: Alternate Next Page */
5030 + PHY_L_PC_GMII_ALT= 1<<12, /* Bit 13: Alternate GMII driver */
5031 + PHY_L_PC_TEN_CRS = 1<<10, /* Bit 10: Extend CRS*/
5032 +};
5033 +
5034 +/***** PHY_LONE_CIM 16 bit r/o CIM Reg *****/
5035 +enum {
5036 + PHY_L_CIM_ISOL = 0xff<<8,/* Bit 15..8: Isolate Count */
5037 + PHY_L_CIM_FALSE_CAR = 0xff, /* Bit 7..0: False Carrier Count */
5038 +};
5039 +
5040 +/*
5041 + * Pause Bits (PHY_L_AN_ASP and PHY_L_AN_PC) encoding
5042 + */
5043 +enum {
5044 + PHY_L_P_NO_PAUSE= 0<<10,/* Bit 11..10: no Pause Mode */
5045 + PHY_L_P_SYM_MD = 1<<10, /* Bit 11..10: symmetric Pause Mode */
5046 + PHY_L_P_ASYM_MD = 2<<10,/* Bit 11..10: asymmetric Pause Mode */
5047 + PHY_L_P_BOTH_MD = 3<<10,/* Bit 11..10: both Pause Mode */
5048 +};
5049 +
5050 +/*
5051 + * National-Specific
5052 + */
5053 +/***** PHY_NAT_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
5054 +enum {
5055 + PHY_N_1000C_TEST= 7<<13,/* Bit 15..13: Test Modes */
5056 + PHY_N_1000C_MSE = 1<<12, /* Bit 12: Master/Slave Enable */
5057 + PHY_N_1000C_MSC = 1<<11, /* Bit 11: M/S Configuration */
5058 + PHY_N_1000C_RD = 1<<10, /* Bit 10: Repeater/DTE */
5059 + PHY_N_1000C_AFD = 1<<9, /* Bit 9: Advertise Full Duplex */
5060 + PHY_N_1000C_AHD = 1<<8, /* Bit 8: Advertise Half Duplex */
5061 + PHY_N_1000C_APC = 1<<7, /* Bit 7: Asymmetric Pause Cap. */};
5062 +
5063 +
5064 +/***** PHY_NAT_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
5065 +enum {
5066 + PHY_N_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
5067 + PHY_N_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
5068 + PHY_N_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
5069 + PHY_N_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status*/
5070 + PHY_N_1000S_LP_FD= 1<<11, /* Bit 11: Link Partner can FD */
5071 + PHY_N_1000S_LP_HD= 1<<10, /* Bit 10: Link Partner can HD */
5072 + PHY_N_1000C_LP_APC= 1<<9, /* Bit 9: LP Asym. Pause Cap. */
5073 + PHY_N_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
5074 +};
5075 +
5076 +/***** PHY_NAT_EXT_STAT 16 bit r/o Extended Status Register *****/
5077 +enum {
5078 + PHY_N_ES_X_FD_CAP= 1<<15, /* Bit 15: 1000Base-X FD capable */
5079 + PHY_N_ES_X_HD_CAP= 1<<14, /* Bit 14: 1000Base-X HD capable */
5080 + PHY_N_ES_T_FD_CAP= 1<<13, /* Bit 13: 1000Base-T FD capable */
5081 + PHY_N_ES_T_HD_CAP= 1<<12, /* Bit 12: 1000Base-T HD capable */
5082 +};
5083 +
5084 +/** Marvell-Specific */
5085 +enum {
5086 + PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
5087 + PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */
5088 + PHY_M_AN_RF = 1<<13, /* Remote Fault */
5089 +
5090 + PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */
5091 + PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */
5092 + PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
5093 + PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
5094 + PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
5095 + PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
5096 + PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
5097 + PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
5098 +};
5099 +
5100 +/* special defines for FIBER (88E1011S only) */
5101 +enum {
5102 + PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
5103 + PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
5104 + PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
5105 + PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
5106 +};
5107 +
5108 +/* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
5109 +enum {
5110 + PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
5111 + PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
5112 + PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
5113 + PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
5114 +};
5115 +
5116 +/***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
5117 +enum {
5118 + PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
5119 + PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
5120 + PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
5121 + PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
5122 + PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
5123 + PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
5124 +};
5125 +
5126 +/***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
5127 +enum {
5128 + PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
5129 + PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
5130 + PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
5131 + PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */
5132 + PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
5133 + PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */
5134 + PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
5135 + PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */
5136 + PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */
5137 + PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */
5138 + PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */
5139 + PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */
5140 +};
5141 +
5142 +enum {
5143 + PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */
5144 + PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
5145 +};
5146 +
5147 +#define PHY_M_PC_MDI_XMODE(x) (((x)<<5) & PHY_M_PC_MDIX_MSK)
5148 +
5149 +enum {
5150 + PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
5151 + PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */
5152 + PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
5153 +};
5154 +
5155 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
5156 +enum {
5157 + PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
5158 + PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */
5159 + PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */
5160 + PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */
5161 + PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
5162 +
5163 + PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */
5164 + PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
5165 +
5166 + PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */
5167 + PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
5168 +};
5169 +
5170 +/***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
5171 +enum {
5172 + PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
5173 + PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */
5174 + PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */
5175 + PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */
5176 + PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */
5177 + PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */
5178 + PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */
5179 + PHY_M_PS_LINK_UP = 1<<10, /* Link Up */
5180 + PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
5181 + PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */
5182 + PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */
5183 + PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */
5184 + PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */
5185 + PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */
5186 + PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */
5187 + PHY_M_PS_JABBER = 1<<0, /* Jabber */
5188 +};
5189 +
5190 +#define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
5191 +
5192 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
5193 +enum {
5194 + PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */
5195 + PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
5196 +};
5197 +
5198 +enum {
5199 + PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
5200 + PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */
5201 + PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */
5202 + PHY_M_IS_AN_PR = 1<<12, /* Page Received */
5203 + PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
5204 + PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */
5205 + PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */
5206 + PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */
5207 + PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */
5208 + PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */
5209 + PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */
5210 + PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */
5211 +
5212 + PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */
5213 + PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */
5214 + PHY_M_IS_JABBER = 1<<0, /* Jabber */
5215 +};
5216 +
5217 +#define PHY_M_DEF_MSK ( PHY_M_IS_AN_ERROR | PHY_M_IS_LSP_CHANGE | \
5218 + PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR)
5219 +
5220 +/***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
5221 +enum {
5222 + PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
5223 + PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
5224 +
5225 + PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
5226 + PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
5227 + /* (88E1011 only) */
5228 + PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */
5229 + /* (88E1011 only) */
5230 + PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */
5231 + /* (88E1111 only) */
5232 + PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
5233 + /* !!! Errata in spec. (1 = disable) */
5234 + PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
5235 + PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */
5236 + PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
5237 + PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
5238 + PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
5239 + PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};
5240 +
5241 +#define PHY_M_EC_M_DSC(x) ((x)<<10) /* 00=1x; 01=2x; 10=3x; 11=4x */
5242 +#define PHY_M_EC_S_DSC(x) ((x)<<8) /* 00=dis; 01=1x; 10=2x; 11=3x */
5243 +#define PHY_M_EC_MAC_S(x) ((x)<<4) /* 01X=0; 110=2.5; 111=25 (MHz) */
5244 +
5245 +#define PHY_M_EC_M_DSC_2(x) ((x)<<9) /* 000=1x; 001=2x; 010=3x; 011=4x */
5246 + /* 100=5x; 101=6x; 110=7x; 111=8x */
5247 +enum {
5248 + MAC_TX_CLK_0_MHZ = 2,
5249 + MAC_TX_CLK_2_5_MHZ = 6,
5250 + MAC_TX_CLK_25_MHZ = 7,
5251 +};
5252 +
5253 +/***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
5254 +enum {
5255 + PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */
5256 + PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
5257 + PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
5258 + PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
5259 + PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
5260 + PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
5261 + PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
5262 + /* (88E1111 only) */
5263 +};
5264 +
5265 +enum {
5266 + PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */
5267 + /* (88E1011 only) */
5268 + PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
5269 + PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
5270 + PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
5271 + PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
5272 + PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
5273 +};
5274 +
5275 +#define PHY_M_LED_PULS_DUR(x) ( ((x)<<12) & PHY_M_LEDC_PULS_MSK)
5276 +
5277 +enum {
5278 + PULS_NO_STR = 0,/* no pulse stretching */
5279 + PULS_21MS = 1,/* 21 ms to 42 ms */
5280 + PULS_42MS = 2,/* 42 ms to 84 ms */
5281 + PULS_84MS = 3,/* 84 ms to 170 ms */
5282 + PULS_170MS = 4,/* 170 ms to 340 ms */
5283 + PULS_340MS = 5,/* 340 ms to 670 ms */
5284 + PULS_670MS = 6,/* 670 ms to 1.3 s */
5285 + PULS_1300MS = 7,/* 1.3 s to 2.7 s */
5286