/[linux-patches]/genpatches-2.6/trunk/2.6.15/4100_sky2-0.11.patch
Gentoo

Contents of /genpatches-2.6/trunk/2.6.15/4100_sky2-0.11.patch

Parent Directory Parent Directory | Revision Log Revision Log


Revision 245 - (show annotations) (download) (as text)
Tue Jan 3 18:15:31 2006 UTC (14 years, 8 months ago) by dsd
File MIME type: text/x-diff
File size: 167875 byte(s)
sky2 v0.11
1 Patch generated 2006-01-03
2 Last commit: [PATCH] sky2: version 0.11
3
4 --- linux-2.6.15/drivers/net/Makefile 2006-01-03 17:42:32.000000000 +0000
5 +++ linux-dsd/drivers/net/Makefile 2006-01-03 18:10:52.000000000 +0000
6 @@ -59,6 +59,7 @@ spidernet-y += spider_net.o spider_net_e
7 obj-$(CONFIG_SPIDER_NET) += spidernet.o
8 obj-$(CONFIG_TC35815) += tc35815.o
9 obj-$(CONFIG_SKGE) += skge.o
10 +obj-$(CONFIG_SKY2) += sky2.o
11 obj-$(CONFIG_SK98LIN) += sk98lin/
12 obj-$(CONFIG_SKFP) += skfp/
13 obj-$(CONFIG_VIA_RHINE) += via-rhine.o
14 --- linux-2.6.15/drivers/net/Kconfig 2006-01-03 17:42:32.000000000 +0000
15 +++ linux-dsd/drivers/net/Kconfig 2006-01-03 18:10:52.000000000 +0000
16 @@ -2008,7 +2008,17 @@ config SKGE
17
18 It does not support the link failover and network management
19 features that "portable" vendor supplied sk98lin driver does.
20 -
21 +
22 +config SKY2
23 + tristate "SysKonnect Yukon2 support (EXPERIMENTAL)"
24 + depends on PCI && EXPERIMENTAL
25 + select CRC32
26 + ---help---
27 + This driver support the Marvell Yukon 2 Gigabit Ethernet adapter.
28 +
29 + To compile this driver as a module, choose M here: the module
30 + will be called sky2. This is recommended.
31 +
32 config SK98LIN
33 tristate "Marvell Yukon Chipset / SysKonnect SK-98xx Support"
34 depends on PCI
35 --- linux-2.6.15/drivers/net/sky2.c 1970-01-01 01:00:00.000000000 +0100
36 +++ linux-dsd/drivers/net/sky2.c 2006-01-03 18:11:50.000000000 +0000
37 @@ -0,0 +1,3262 @@
38 +/*
39 + * New driver for Marvell Yukon 2 chipset.
40 + * Based on earlier sk98lin, and skge driver.
41 + *
42 + * This driver intentionally does not support all the features
43 + * of the original driver such as link fail-over and link management because
44 + * those should be done at higher levels.
45 + *
46 + * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
47 + *
48 + * This program is free software; you can redistribute it and/or modify
49 + * it under the terms of the GNU General Public License as published by
50 + * the Free Software Foundation; either version 2 of the License, or
51 + * (at your option) any later version.
52 + *
53 + * This program is distributed in the hope that it will be useful,
54 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
55 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
56 + * GNU General Public License for more details.
57 + *
58 + * You should have received a copy of the GNU General Public License
59 + * along with this program; if not, write to the Free Software
60 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
61 + */
62 +
63 +/*
64 + * TOTEST
65 + * - speed setting
66 + * - suspend/resume
67 + */
68 +
69 +#include <linux/config.h>
70 +#include <linux/crc32.h>
71 +#include <linux/kernel.h>
72 +#include <linux/version.h>
73 +#include <linux/module.h>
74 +#include <linux/netdevice.h>
75 +#include <linux/dma-mapping.h>
76 +#include <linux/etherdevice.h>
77 +#include <linux/ethtool.h>
78 +#include <linux/pci.h>
79 +#include <linux/ip.h>
80 +#include <linux/tcp.h>
81 +#include <linux/in.h>
82 +#include <linux/delay.h>
83 +#include <linux/workqueue.h>
84 +#include <linux/if_vlan.h>
85 +#include <linux/prefetch.h>
86 +#include <linux/mii.h>
87 +
88 +#include <asm/irq.h>
89 +
90 +#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
91 +#define SKY2_VLAN_TAG_USED 1
92 +#endif
93 +
94 +#include "sky2.h"
95 +
96 +#define DRV_NAME "sky2"
97 +#define DRV_VERSION "0.11"
98 +#define PFX DRV_NAME " "
99 +
100 +/*
101 + * The Yukon II chipset takes 64 bit command blocks (called list elements)
102 + * that are organized into three (receive, transmit, status) different rings
103 + * similar to Tigon3. A transmit can require several elements;
104 + * a receive requires one (or two if using 64 bit dma).
105 + */
106 +
107 +#define is_ec_a1(hw) \
108 + unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
109 + (hw)->chip_rev == CHIP_REV_YU_EC_A1)
110 +
111 +#define RX_LE_SIZE 512
112 +#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
113 +#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
114 +#define RX_DEF_PENDING RX_MAX_PENDING
115 +
116 +#define TX_RING_SIZE 512
117 +#define TX_DEF_PENDING (TX_RING_SIZE - 1)
118 +#define TX_MIN_PENDING 64
119 +#define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
120 +
121 +#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
122 +#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
123 +#define ETH_JUMBO_MTU 9000
124 +#define TX_WATCHDOG (5 * HZ)
125 +#define NAPI_WEIGHT 64
126 +#define PHY_RETRIES 1000
127 +
128 +static const u32 default_msg =
129 + NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
130 + | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
131 + | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_INTR;
132 +
133 +static int debug = -1; /* defaults above */
134 +module_param(debug, int, 0);
135 +MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
136 +
137 +static int copybreak __read_mostly = 256;
138 +module_param(copybreak, int, 0);
139 +MODULE_PARM_DESC(copybreak, "Receive copy threshold");
140 +
141 +static const struct pci_device_id sky2_id_table[] = {
142 + { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
143 + { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
144 + { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
145 + { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
146 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
147 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
148 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
149 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
150 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
151 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
152 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
153 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
154 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
155 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
156 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
157 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
158 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
159 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
160 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
161 + { 0 }
162 +};
163 +
164 +MODULE_DEVICE_TABLE(pci, sky2_id_table);
165 +
166 +/* Avoid conditionals by using array */
167 +static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
168 +static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
169 +
170 +/* This driver supports yukon2 chipset only */
171 +static const char *yukon2_name[] = {
172 + "XL", /* 0xb3 */
173 + "EC Ultra", /* 0xb4 */
174 + "UNKNOWN", /* 0xb5 */
175 + "EC", /* 0xb6 */
176 + "FE", /* 0xb7 */
177 +};
178 +
179 +/* Access to external PHY */
180 +static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
181 +{
182 + int i;
183 +
184 + gma_write16(hw, port, GM_SMI_DATA, val);
185 + gma_write16(hw, port, GM_SMI_CTRL,
186 + GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
187 +
188 + for (i = 0; i < PHY_RETRIES; i++) {
189 + if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
190 + return 0;
191 + udelay(1);
192 + }
193 +
194 + printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
195 + return -ETIMEDOUT;
196 +}
197 +
198 +static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
199 +{
200 + int i;
201 +
202 + gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
203 + | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
204 +
205 + for (i = 0; i < PHY_RETRIES; i++) {
206 + if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
207 + *val = gma_read16(hw, port, GM_SMI_DATA);
208 + return 0;
209 + }
210 +
211 + udelay(1);
212 + }
213 +
214 + return -ETIMEDOUT;
215 +}
216 +
217 +static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
218 +{
219 + u16 v;
220 +
221 + if (__gm_phy_read(hw, port, reg, &v) != 0)
222 + printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
223 + return v;
224 +}
225 +
226 +static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
227 +{
228 + u16 power_control;
229 + u32 reg1;
230 + int vaux;
231 + int ret = 0;
232 +
233 + pr_debug("sky2_set_power_state %d\n", state);
234 + sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
235 +
236 + pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control);
237 + vaux = (sky2_read8(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
238 + (power_control & PCI_PM_CAP_PME_D3cold);
239 +
240 + pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control);
241 +
242 + power_control |= PCI_PM_CTRL_PME_STATUS;
243 + power_control &= ~(PCI_PM_CTRL_STATE_MASK);
244 +
245 + switch (state) {
246 + case PCI_D0:
247 + /* switch power to VCC (WA for VAUX problem) */
248 + sky2_write8(hw, B0_POWER_CTRL,
249 + PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
250 +
251 + /* disable Core Clock Division, */
252 + sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
253 +
254 + if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
255 + /* enable bits are inverted */
256 + sky2_write8(hw, B2_Y2_CLK_GATE,
257 + Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
258 + Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
259 + Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
260 + else
261 + sky2_write8(hw, B2_Y2_CLK_GATE, 0);
262 +
263 + /* Turn off phy power saving */
264 + pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
265 + reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
266 +
267 + /* looks like this XL is back asswards .. */
268 + if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
269 + reg1 |= PCI_Y2_PHY1_COMA;
270 + if (hw->ports > 1)
271 + reg1 |= PCI_Y2_PHY2_COMA;
272 + }
273 + pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
274 + break;
275 +
276 + case PCI_D3hot:
277 + case PCI_D3cold:
278 + /* Turn on phy power saving */
279 + pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
280 + if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
281 + reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
282 + else
283 + reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
284 + pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
285 +
286 + if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
287 + sky2_write8(hw, B2_Y2_CLK_GATE, 0);
288 + else
289 + /* enable bits are inverted */
290 + sky2_write8(hw, B2_Y2_CLK_GATE,
291 + Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
292 + Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
293 + Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
294 +
295 + /* switch power to VAUX */
296 + if (vaux && state != PCI_D3cold)
297 + sky2_write8(hw, B0_POWER_CTRL,
298 + (PC_VAUX_ENA | PC_VCC_ENA |
299 + PC_VAUX_ON | PC_VCC_OFF));
300 + break;
301 + default:
302 + printk(KERN_ERR PFX "Unknown power state %d\n", state);
303 + ret = -1;
304 + }
305 +
306 + pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control);
307 + sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
308 + return ret;
309 +}
310 +
311 +static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
312 +{
313 + u16 reg;
314 +
315 + /* disable all GMAC IRQ's */
316 + sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
317 + /* disable PHY IRQs */
318 + gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
319 +
320 + gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
321 + gma_write16(hw, port, GM_MC_ADDR_H2, 0);
322 + gma_write16(hw, port, GM_MC_ADDR_H3, 0);
323 + gma_write16(hw, port, GM_MC_ADDR_H4, 0);
324 +
325 + reg = gma_read16(hw, port, GM_RX_CTRL);
326 + reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
327 + gma_write16(hw, port, GM_RX_CTRL, reg);
328 +}
329 +
330 +static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
331 +{
332 + struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
333 + u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
334 +
335 + if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
336 + u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
337 +
338 + ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
339 + PHY_M_EC_MAC_S_MSK);
340 + ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
341 +
342 + if (hw->chip_id == CHIP_ID_YUKON_EC)
343 + ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
344 + else
345 + ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
346 +
347 + gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
348 + }
349 +
350 + ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
351 + if (hw->copper) {
352 + if (hw->chip_id == CHIP_ID_YUKON_FE) {
353 + /* enable automatic crossover */
354 + ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
355 + } else {
356 + /* disable energy detect */
357 + ctrl &= ~PHY_M_PC_EN_DET_MSK;
358 +
359 + /* enable automatic crossover */
360 + ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
361 +
362 + if (sky2->autoneg == AUTONEG_ENABLE &&
363 + hw->chip_id == CHIP_ID_YUKON_XL) {
364 + ctrl &= ~PHY_M_PC_DSC_MSK;
365 + ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
366 + }
367 + }
368 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
369 + } else {
370 + /* workaround for deviation #4.88 (CRC errors) */
371 + /* disable Automatic Crossover */
372 +
373 + ctrl &= ~PHY_M_PC_MDIX_MSK;
374 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
375 +
376 + if (hw->chip_id == CHIP_ID_YUKON_XL) {
377 + /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
378 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
379 + ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
380 + ctrl &= ~PHY_M_MAC_MD_MSK;
381 + ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
382 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
383 +
384 + /* select page 1 to access Fiber registers */
385 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
386 + }
387 + }
388 +
389 + ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
390 + if (sky2->autoneg == AUTONEG_DISABLE)
391 + ctrl &= ~PHY_CT_ANE;
392 + else
393 + ctrl |= PHY_CT_ANE;
394 +
395 + ctrl |= PHY_CT_RESET;
396 + gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
397 +
398 + ctrl = 0;
399 + ct1000 = 0;
400 + adv = PHY_AN_CSMA;
401 +
402 + if (sky2->autoneg == AUTONEG_ENABLE) {
403 + if (hw->copper) {
404 + if (sky2->advertising & ADVERTISED_1000baseT_Full)
405 + ct1000 |= PHY_M_1000C_AFD;
406 + if (sky2->advertising & ADVERTISED_1000baseT_Half)
407 + ct1000 |= PHY_M_1000C_AHD;
408 + if (sky2->advertising & ADVERTISED_100baseT_Full)
409 + adv |= PHY_M_AN_100_FD;
410 + if (sky2->advertising & ADVERTISED_100baseT_Half)
411 + adv |= PHY_M_AN_100_HD;
412 + if (sky2->advertising & ADVERTISED_10baseT_Full)
413 + adv |= PHY_M_AN_10_FD;
414 + if (sky2->advertising & ADVERTISED_10baseT_Half)
415 + adv |= PHY_M_AN_10_HD;
416 + } else /* special defines for FIBER (88E1011S only) */
417 + adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
418 +
419 + /* Set Flow-control capabilities */
420 + if (sky2->tx_pause && sky2->rx_pause)
421 + adv |= PHY_AN_PAUSE_CAP; /* symmetric */
422 + else if (sky2->rx_pause && !sky2->tx_pause)
423 + adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
424 + else if (!sky2->rx_pause && sky2->tx_pause)
425 + adv |= PHY_AN_PAUSE_ASYM; /* local */
426 +
427 + /* Restart Auto-negotiation */
428 + ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
429 + } else {
430 + /* forced speed/duplex settings */
431 + ct1000 = PHY_M_1000C_MSE;
432 +
433 + if (sky2->duplex == DUPLEX_FULL)
434 + ctrl |= PHY_CT_DUP_MD;
435 +
436 + switch (sky2->speed) {
437 + case SPEED_1000:
438 + ctrl |= PHY_CT_SP1000;
439 + break;
440 + case SPEED_100:
441 + ctrl |= PHY_CT_SP100;
442 + break;
443 + }
444 +
445 + ctrl |= PHY_CT_RESET;
446 + }
447 +
448 + if (hw->chip_id != CHIP_ID_YUKON_FE)
449 + gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
450 +
451 + gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
452 + gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
453 +
454 + /* Setup Phy LED's */
455 + ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
456 + ledover = 0;
457 +
458 + switch (hw->chip_id) {
459 + case CHIP_ID_YUKON_FE:
460 + /* on 88E3082 these bits are at 11..9 (shifted left) */
461 + ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
462 +
463 + ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
464 +
465 + /* delete ACT LED control bits */
466 + ctrl &= ~PHY_M_FELP_LED1_MSK;
467 + /* change ACT LED control to blink mode */
468 + ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
469 + gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
470 + break;
471 +
472 + case CHIP_ID_YUKON_XL:
473 + pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
474 +
475 + /* select page 3 to access LED control register */
476 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
477 +
478 + /* set LED Function Control register */
479 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
480 + PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
481 + PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
482 + PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
483 +
484 + /* set Polarity Control register */
485 + gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
486 + (PHY_M_POLC_LS1_P_MIX(4) |
487 + PHY_M_POLC_IS0_P_MIX(4) |
488 + PHY_M_POLC_LOS_CTRL(2) |
489 + PHY_M_POLC_INIT_CTRL(2) |
490 + PHY_M_POLC_STA1_CTRL(2) |
491 + PHY_M_POLC_STA0_CTRL(2)));
492 +
493 + /* restore page register */
494 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
495 + break;
496 +
497 + default:
498 + /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
499 + ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
500 + /* turn off the Rx LED (LED_RX) */
501 + ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
502 + }
503 +
504 + gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
505 +
506 + if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
507 + /* turn on 100 Mbps LED (LED_LINK100) */
508 + ledover |= PHY_M_LED_MO_100(MO_LED_ON);
509 + }
510 +
511 + if (ledover)
512 + gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
513 +
514 + /* Enable phy interrupt on auto-negotiation complete (or link up) */
515 + if (sky2->autoneg == AUTONEG_ENABLE)
516 + gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
517 + else
518 + gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
519 +}
520 +
521 +/* Force a renegotiation */
522 +static void sky2_phy_reinit(struct sky2_port *sky2)
523 +{
524 + down(&sky2->phy_sema);
525 + sky2_phy_init(sky2->hw, sky2->port);
526 + up(&sky2->phy_sema);
527 +}
528 +
529 +static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
530 +{
531 + struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
532 + u16 reg;
533 + int i;
534 + const u8 *addr = hw->dev[port]->dev_addr;
535 +
536 + sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
537 + sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
538 +
539 + sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
540 +
541 + if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
542 + /* WA DEV_472 -- looks like crossed wires on port 2 */
543 + /* clear GMAC 1 Control reset */
544 + sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
545 + do {
546 + sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
547 + sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
548 + } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
549 + gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
550 + gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
551 + }
552 +
553 + if (sky2->autoneg == AUTONEG_DISABLE) {
554 + reg = gma_read16(hw, port, GM_GP_CTRL);
555 + reg |= GM_GPCR_AU_ALL_DIS;
556 + gma_write16(hw, port, GM_GP_CTRL, reg);
557 + gma_read16(hw, port, GM_GP_CTRL);
558 +
559 + switch (sky2->speed) {
560 + case SPEED_1000:
561 + reg |= GM_GPCR_SPEED_1000;
562 + /* fallthru */
563 + case SPEED_100:
564 + reg |= GM_GPCR_SPEED_100;
565 + }
566 +
567 + if (sky2->duplex == DUPLEX_FULL)
568 + reg |= GM_GPCR_DUP_FULL;
569 + } else
570 + reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
571 +
572 + if (!sky2->tx_pause && !sky2->rx_pause) {
573 + sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
574 + reg |=
575 + GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
576 + } else if (sky2->tx_pause && !sky2->rx_pause) {
577 + /* disable Rx flow-control */
578 + reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
579 + }
580 +
581 + gma_write16(hw, port, GM_GP_CTRL, reg);
582 +
583 + sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
584 +
585 + down(&sky2->phy_sema);
586 + sky2_phy_init(hw, port);
587 + up(&sky2->phy_sema);
588 +
589 + /* MIB clear */
590 + reg = gma_read16(hw, port, GM_PHY_ADDR);
591 + gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
592 +
593 + for (i = 0; i < GM_MIB_CNT_SIZE; i++)
594 + gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
595 + gma_write16(hw, port, GM_PHY_ADDR, reg);
596 +
597 + /* transmit control */
598 + gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
599 +
600 + /* receive control reg: unicast + multicast + no FCS */
601 + gma_write16(hw, port, GM_RX_CTRL,
602 + GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
603 +
604 + /* transmit flow control */
605 + gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
606 +
607 + /* transmit parameter */
608 + gma_write16(hw, port, GM_TX_PARAM,
609 + TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
610 + TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
611 + TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
612 + TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
613 +
614 + /* serial mode register */
615 + reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
616 + GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
617 +
618 + if (hw->dev[port]->mtu > ETH_DATA_LEN)
619 + reg |= GM_SMOD_JUMBO_ENA;
620 +
621 + gma_write16(hw, port, GM_SERIAL_MODE, reg);
622 +
623 + /* virtual address for data */
624 + gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
625 +
626 + /* physical address: used for pause frames */
627 + gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
628 +
629 + /* ignore counter overflows */
630 + gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
631 + gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
632 + gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
633 +
634 + /* Configure Rx MAC FIFO */
635 + sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
636 + sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
637 + GMF_RX_CTRL_DEF);
638 +
639 + /* Flush Rx MAC FIFO on any flow control or error */
640 + sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
641 +
642 + /* Set threshold to 0xa (64 bytes)
643 + * ASF disabled so no need to do WA dev #4.30
644 + */
645 + sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
646 +
647 + /* Configure Tx MAC FIFO */
648 + sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
649 + sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
650 +
651 + if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
652 + sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
653 + sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
654 + if (hw->dev[port]->mtu > ETH_DATA_LEN) {
655 + /* set Tx GMAC FIFO Almost Empty Threshold */
656 + sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
657 + /* Disable Store & Forward mode for TX */
658 + sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
659 + }
660 + }
661 +
662 +}
663 +
664 +static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, size_t len)
665 +{
666 + u32 end;
667 +
668 + start /= 8;
669 + len /= 8;
670 + end = start + len - 1;
671 +
672 + sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
673 + sky2_write32(hw, RB_ADDR(q, RB_START), start);
674 + sky2_write32(hw, RB_ADDR(q, RB_END), end);
675 + sky2_write32(hw, RB_ADDR(q, RB_WP), start);
676 + sky2_write32(hw, RB_ADDR(q, RB_RP), start);
677 +
678 + if (q == Q_R1 || q == Q_R2) {
679 + u32 rxup, rxlo;
680 +
681 + rxlo = len/2;
682 + rxup = rxlo + len/4;
683 +
684 + /* Set thresholds on receive queue's */
685 + sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), rxup);
686 + sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), rxlo);
687 + } else {
688 + /* Enable store & forward on Tx queue's because
689 + * Tx FIFO is only 1K on Yukon
690 + */
691 + sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
692 + }
693 +
694 + sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
695 + sky2_read8(hw, RB_ADDR(q, RB_CTRL));
696 +}
697 +
698 +/* Setup Bus Memory Interface */
699 +static void sky2_qset(struct sky2_hw *hw, u16 q)
700 +{
701 + sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
702 + sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
703 + sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
704 + sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
705 +}
706 +
707 +/* Setup prefetch unit registers. This is the interface between
708 + * hardware and driver list elements
709 + */
710 +static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
711 + u64 addr, u32 last)
712 +{
713 + sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
714 + sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
715 + sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
716 + sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
717 + sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
718 + sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
719 +
720 + sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
721 +}
722 +
723 +static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
724 +{
725 + struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
726 +
727 + sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
728 + return le;
729 +}
730 +
731 +/*
732 + * This is a workaround code taken from SysKonnect sk98lin driver
733 + * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
734 + */
735 +static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q,
736 + u16 idx, u16 *last, u16 size)
737 +{
738 + if (is_ec_a1(hw) && idx < *last) {
739 + u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
740 +
741 + if (hwget == 0) {
742 + /* Start prefetching again */
743 + sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
744 + goto setnew;
745 + }
746 +
747 + if (hwget == size - 1) {
748 + /* set watermark to one list element */
749 + sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
750 +
751 + /* set put index to first list element */
752 + sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
753 + } else /* have hardware go to end of list */
754 + sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
755 + size - 1);
756 + } else {
757 +setnew:
758 + sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
759 + }
760 + *last = idx;
761 +}
762 +
763 +
764 +static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
765 +{
766 + struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
767 + sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
768 + return le;
769 +}
770 +
771 +/* Return high part of DMA address (could be 32 or 64 bit) */
772 +static inline u32 high32(dma_addr_t a)
773 +{
774 + return (a >> 16) >> 16;
775 +}
776 +
777 +/* Build description to hardware about buffer */
778 +static inline void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
779 +{
780 + struct sky2_rx_le *le;
781 + u32 hi = high32(map);
782 + u16 len = sky2->rx_bufsize;
783 +
784 + if (sky2->rx_addr64 != hi) {
785 + le = sky2_next_rx(sky2);
786 + le->addr = cpu_to_le32(hi);
787 + le->ctrl = 0;
788 + le->opcode = OP_ADDR64 | HW_OWNER;
789 + sky2->rx_addr64 = high32(map + len);
790 + }
791 +
792 + le = sky2_next_rx(sky2);
793 + le->addr = cpu_to_le32((u32) map);
794 + le->length = cpu_to_le16(len);
795 + le->ctrl = 0;
796 + le->opcode = OP_PACKET | HW_OWNER;
797 +}
798 +
799 +
800 +/* Tell chip where to start receive checksum.
801 + * Actually has two checksums, but set both same to avoid possible byte
802 + * order problems.
803 + */
804 +static void rx_set_checksum(struct sky2_port *sky2)
805 +{
806 + struct sky2_rx_le *le;
807 +
808 + le = sky2_next_rx(sky2);
809 + le->addr = (ETH_HLEN << 16) | ETH_HLEN;
810 + le->ctrl = 0;
811 + le->opcode = OP_TCPSTART | HW_OWNER;
812 +
813 + sky2_write32(sky2->hw,
814 + Q_ADDR(rxqaddr[sky2->port], Q_CSR),
815 + sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
816 +
817 +}
818 +
819 +/*
820 + * The RX Stop command will not work for Yukon-2 if the BMU does not
821 + * reach the end of packet and since we can't make sure that we have
822 + * incoming data, we must reset the BMU while it is not doing a DMA
823 + * transfer. Since it is possible that the RX path is still active,
824 + * the RX RAM buffer will be stopped first, so any possible incoming
825 + * data will not trigger a DMA. After the RAM buffer is stopped, the
826 + * BMU is polled until any DMA in progress is ended and only then it
827 + * will be reset.
828 + */
829 +static void sky2_rx_stop(struct sky2_port *sky2)
830 +{
831 + struct sky2_hw *hw = sky2->hw;
832 + unsigned rxq = rxqaddr[sky2->port];
833 + int i;
834 +
835 + /* disable the RAM Buffer receive queue */
836 + sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
837 +
838 + for (i = 0; i < 0xffff; i++)
839 + if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
840 + == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
841 + goto stopped;
842 +
843 + printk(KERN_WARNING PFX "%s: receiver stop failed\n",
844 + sky2->netdev->name);
845 +stopped:
846 + sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
847 +
848 + /* reset the Rx prefetch unit */
849 + sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
850 +}
851 +
852 +/* Clean out receive buffer area, assumes receiver hardware stopped */
853 +static void sky2_rx_clean(struct sky2_port *sky2)
854 +{
855 + unsigned i;
856 +
857 + memset(sky2->rx_le, 0, RX_LE_BYTES);
858 + for (i = 0; i < sky2->rx_pending; i++) {
859 + struct ring_info *re = sky2->rx_ring + i;
860 +
861 + if (re->skb) {
862 + pci_unmap_single(sky2->hw->pdev,
863 + re->mapaddr, sky2->rx_bufsize,
864 + PCI_DMA_FROMDEVICE);
865 + kfree_skb(re->skb);
866 + re->skb = NULL;
867 + }
868 + }
869 +}
870 +
871 +/* Basic MII support */
872 +static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
873 +{
874 + struct mii_ioctl_data *data = if_mii(ifr);
875 + struct sky2_port *sky2 = netdev_priv(dev);
876 + struct sky2_hw *hw = sky2->hw;
877 + int err = -EOPNOTSUPP;
878 +
879 + if (!netif_running(dev))
880 + return -ENODEV; /* Phy still in reset */
881 +
882 + switch(cmd) {
883 + case SIOCGMIIPHY:
884 + data->phy_id = PHY_ADDR_MARV;
885 +
886 + /* fallthru */
887 + case SIOCGMIIREG: {
888 + u16 val = 0;
889 +
890 + down(&sky2->phy_sema);
891 + err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
892 + up(&sky2->phy_sema);
893 +
894 + data->val_out = val;
895 + break;
896 + }
897 +
898 + case SIOCSMIIREG:
899 + if (!capable(CAP_NET_ADMIN))
900 + return -EPERM;
901 +
902 + down(&sky2->phy_sema);
903 + err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
904 + data->val_in);
905 + up(&sky2->phy_sema);
906 + break;
907 + }
908 + return err;
909 +}
910 +
911 +#ifdef SKY2_VLAN_TAG_USED
912 +static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
913 +{
914 + struct sky2_port *sky2 = netdev_priv(dev);
915 + struct sky2_hw *hw = sky2->hw;
916 + u16 port = sky2->port;
917 +
918 + spin_lock(&sky2->tx_lock);
919 +
920 + sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
921 + sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
922 + sky2->vlgrp = grp;
923 +
924 + spin_unlock(&sky2->tx_lock);
925 +}
926 +
927 +static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
928 +{
929 + struct sky2_port *sky2 = netdev_priv(dev);
930 + struct sky2_hw *hw = sky2->hw;
931 + u16 port = sky2->port;
932 +
933 + spin_lock(&sky2->tx_lock);
934 +
935 + sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
936 + sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
937 + if (sky2->vlgrp)
938 + sky2->vlgrp->vlan_devices[vid] = NULL;
939 +
940 + spin_unlock(&sky2->tx_lock);
941 +}
942 +#endif
943 +
944 +/*
945 + * Allocate and setup receiver buffer pool.
946 + * In case of 64 bit dma, there are 2X as many list elements
947 + * available as ring entries
948 + * and need to reserve one list element so we don't wrap around.
949 + *
950 + * It appears the hardware has a bug in the FIFO logic that
951 + * cause it to hang if the FIFO gets overrun and the receive buffer
952 + * is not aligned. This means we can't use skb_reserve to align
953 + * the IP header.
954 + */
955 +static int sky2_rx_start(struct sky2_port *sky2)
956 +{
957 + struct sky2_hw *hw = sky2->hw;
958 + unsigned rxq = rxqaddr[sky2->port];
959 + int i;
960 +
961 + sky2->rx_put = sky2->rx_next = 0;
962 + sky2_qset(hw, rxq);
963 + sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
964 +
965 + rx_set_checksum(sky2);
966 + for (i = 0; i < sky2->rx_pending; i++) {
967 + struct ring_info *re = sky2->rx_ring + i;
968 +
969 + re->skb = dev_alloc_skb(sky2->rx_bufsize);
970 + if (!re->skb)
971 + goto nomem;
972 +
973 + re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
974 + sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
975 + sky2_rx_add(sky2, re->mapaddr);
976 + }
977 +
978 + /* Tell chip about available buffers */
979 + sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
980 + sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
981 + return 0;
982 +nomem:
983 + sky2_rx_clean(sky2);
984 + return -ENOMEM;
985 +}
986 +
987 +/* Bring up network interface. */
988 +static int sky2_up(struct net_device *dev)
989 +{
990 + struct sky2_port *sky2 = netdev_priv(dev);
991 + struct sky2_hw *hw = sky2->hw;
992 + unsigned port = sky2->port;
993 + u32 ramsize, rxspace;
994 + int err = -ENOMEM;
995 +
996 + if (netif_msg_ifup(sky2))
997 + printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
998 +
999 + /* must be power of 2 */
1000 + sky2->tx_le = pci_alloc_consistent(hw->pdev,
1001 + TX_RING_SIZE *
1002 + sizeof(struct sky2_tx_le),
1003 + &sky2->tx_le_map);
1004 + if (!sky2->tx_le)
1005 + goto err_out;
1006 +
1007 + sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1008 + GFP_KERNEL);
1009 + if (!sky2->tx_ring)
1010 + goto err_out;
1011 + sky2->tx_prod = sky2->tx_cons = 0;
1012 +
1013 + sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1014 + &sky2->rx_le_map);
1015 + if (!sky2->rx_le)
1016 + goto err_out;
1017 + memset(sky2->rx_le, 0, RX_LE_BYTES);
1018 +
1019 + sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
1020 + GFP_KERNEL);
1021 + if (!sky2->rx_ring)
1022 + goto err_out;
1023 +
1024 + sky2_mac_init(hw, port);
1025 +
1026 + /* Configure RAM buffers */
1027 + if (hw->chip_id == CHIP_ID_YUKON_FE ||
1028 + (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == 2))
1029 + ramsize = 4096;
1030 + else {
1031 + u8 e0 = sky2_read8(hw, B2_E_0);
1032 + ramsize = (e0 == 0) ? (128 * 1024) : (e0 * 4096);
1033 + }
1034 +
1035 + /* 2/3 for Rx */
1036 + rxspace = (2 * ramsize) / 3;
1037 + sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1038 + sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1039 +
1040 + /* Make sure SyncQ is disabled */
1041 + sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1042 + RB_RST_SET);
1043 +
1044 + sky2_qset(hw, txqaddr[port]);
1045 + if (hw->chip_id == CHIP_ID_YUKON_EC_U)
1046 + sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1047 +
1048 +
1049 + sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1050 + TX_RING_SIZE - 1);
1051 +
1052 + err = sky2_rx_start(sky2);
1053 + if (err)
1054 + goto err_out;
1055 +
1056 + /* Enable interrupts from phy/mac for port */
1057 + hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1058 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
1059 + return 0;
1060 +
1061 +err_out:
1062 + if (sky2->rx_le) {
1063 + pci_free_consistent(hw->pdev, RX_LE_BYTES,
1064 + sky2->rx_le, sky2->rx_le_map);
1065 + sky2->rx_le = NULL;
1066 + }
1067 + if (sky2->tx_le) {
1068 + pci_free_consistent(hw->pdev,
1069 + TX_RING_SIZE * sizeof(struct sky2_tx_le),
1070 + sky2->tx_le, sky2->tx_le_map);
1071 + sky2->tx_le = NULL;
1072 + }
1073 + kfree(sky2->tx_ring);
1074 + kfree(sky2->rx_ring);
1075 +
1076 + sky2->tx_ring = NULL;
1077 + sky2->rx_ring = NULL;
1078 + return err;
1079 +}
1080 +
1081 +/* Modular subtraction in ring */
1082 +static inline int tx_dist(unsigned tail, unsigned head)
1083 +{
1084 + return (head - tail) % TX_RING_SIZE;
1085 +}
1086 +
1087 +/* Number of list elements available for next tx */
1088 +static inline int tx_avail(const struct sky2_port *sky2)
1089 +{
1090 + return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1091 +}
1092 +
1093 +/* Estimate of number of transmit list elements required */
1094 +static inline unsigned tx_le_req(const struct sk_buff *skb)
1095 +{
1096 + unsigned count;
1097 +
1098 + count = sizeof(dma_addr_t) / sizeof(u32);
1099 + count += skb_shinfo(skb)->nr_frags * count;
1100 +
1101 + if (skb_shinfo(skb)->tso_size)
1102 + ++count;
1103 +
1104 + if (skb->ip_summed == CHECKSUM_HW)
1105 + ++count;
1106 +
1107 + return count;
1108 +}
1109 +
1110 +/*
1111 + * Put one packet in ring for transmit.
1112 + * A single packet can generate multiple list elements, and
1113 + * the number of ring elements will probably be less than the number
1114 + * of list elements used.
1115 + *
1116 + * No BH disabling for tx_lock here (like tg3)
1117 + */
1118 +static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1119 +{
1120 + struct sky2_port *sky2 = netdev_priv(dev);
1121 + struct sky2_hw *hw = sky2->hw;
1122 + struct sky2_tx_le *le = NULL;
1123 + struct tx_ring_info *re;
1124 + unsigned i, len;
1125 + dma_addr_t mapping;
1126 + u32 addr64;
1127 + u16 mss;
1128 + u8 ctrl;
1129 +
1130 + if (!spin_trylock(&sky2->tx_lock))
1131 + return NETDEV_TX_LOCKED;
1132 +
1133 + if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1134 + /* There is a known but harmless race with lockless tx
1135 + * and netif_stop_queue.
1136 + */
1137 + if (!netif_queue_stopped(dev)) {
1138 + netif_stop_queue(dev);
1139 + printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1140 + dev->name);
1141 + }
1142 + spin_unlock(&sky2->tx_lock);
1143 +
1144 + return NETDEV_TX_BUSY;
1145 + }
1146 +
1147 + if (unlikely(netif_msg_tx_queued(sky2)))
1148 + printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1149 + dev->name, sky2->tx_prod, skb->len);
1150 +
1151 + len = skb_headlen(skb);
1152 + mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1153 + addr64 = high32(mapping);
1154 +
1155 + re = sky2->tx_ring + sky2->tx_prod;
1156 +
1157 + /* Send high bits if changed or crosses boundary */
1158 + if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1159 + le = get_tx_le(sky2);
1160 + le->tx.addr = cpu_to_le32(addr64);
1161 + le->ctrl = 0;
1162 + le->opcode = OP_ADDR64 | HW_OWNER;
1163 + sky2->tx_addr64 = high32(mapping + len);
1164 + }
1165 +
1166 + /* Check for TCP Segmentation Offload */
1167 + mss = skb_shinfo(skb)->tso_size;
1168 + if (mss != 0) {
1169 + /* just drop the packet if non-linear expansion fails */
1170 + if (skb_header_cloned(skb) &&
1171 + pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
1172 + dev_kfree_skb_any(skb);
1173 + goto out_unlock;
1174 + }
1175 +
1176 + mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1177 + mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1178 + mss += ETH_HLEN;
1179 + }
1180 +
1181 + if (mss != sky2->tx_last_mss) {
1182 + le = get_tx_le(sky2);
1183 + le->tx.tso.size = cpu_to_le16(mss);
1184 + le->tx.tso.rsvd = 0;
1185 + le->opcode = OP_LRGLEN | HW_OWNER;
1186 + le->ctrl = 0;
1187 + sky2->tx_last_mss = mss;
1188 + }
1189 +
1190 + ctrl = 0;
1191 +#ifdef SKY2_VLAN_TAG_USED
1192 + /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1193 + if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1194 + if (!le) {
1195 + le = get_tx_le(sky2);
1196 + le->tx.addr = 0;
1197 + le->opcode = OP_VLAN|HW_OWNER;
1198 + le->ctrl = 0;
1199 + } else
1200 + le->opcode |= OP_VLAN;
1201 + le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1202 + ctrl |= INS_VLAN;
1203 + }
1204 +#endif
1205 +
1206 + /* Handle TCP checksum offload */
1207 + if (skb->ip_summed == CHECKSUM_HW) {
1208 + u16 hdr = skb->h.raw - skb->data;
1209 + u16 offset = hdr + skb->csum;
1210 +
1211 + ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1212 + if (skb->nh.iph->protocol == IPPROTO_UDP)
1213 + ctrl |= UDPTCP;
1214 +
1215 + le = get_tx_le(sky2);
1216 + le->tx.csum.start = cpu_to_le16(hdr);
1217 + le->tx.csum.offset = cpu_to_le16(offset);
1218 + le->length = 0; /* initial checksum value */
1219 + le->ctrl = 1; /* one packet */
1220 + le->opcode = OP_TCPLISW | HW_OWNER;
1221 + }
1222 +
1223 + le = get_tx_le(sky2);
1224 + le->tx.addr = cpu_to_le32((u32) mapping);
1225 + le->length = cpu_to_le16(len);
1226 + le->ctrl = ctrl;
1227 + le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1228 +
1229 + /* Record the transmit mapping info */
1230 + re->skb = skb;
1231 + pci_unmap_addr_set(re, mapaddr, mapping);
1232 +
1233 + for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1234 + skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1235 + struct tx_ring_info *fre;
1236 +
1237 + mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1238 + frag->size, PCI_DMA_TODEVICE);
1239 + addr64 = (mapping >> 16) >> 16;
1240 + if (addr64 != sky2->tx_addr64) {
1241 + le = get_tx_le(sky2);
1242 + le->tx.addr = cpu_to_le32(addr64);
1243 + le->ctrl = 0;
1244 + le->opcode = OP_ADDR64 | HW_OWNER;
1245 + sky2->tx_addr64 = addr64;
1246 + }
1247 +
1248 + le = get_tx_le(sky2);
1249 + le->tx.addr = cpu_to_le32((u32) mapping);
1250 + le->length = cpu_to_le16(frag->size);
1251 + le->ctrl = ctrl;
1252 + le->opcode = OP_BUFFER | HW_OWNER;
1253 +
1254 + fre = sky2->tx_ring
1255 + + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
1256 + pci_unmap_addr_set(fre, mapaddr, mapping);
1257 + }
1258 +
1259 + re->idx = sky2->tx_prod;
1260 + le->ctrl |= EOP;
1261 +
1262 + sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
1263 + &sky2->tx_last_put, TX_RING_SIZE);
1264 +
1265 + if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1266 + netif_stop_queue(dev);
1267 +
1268 +out_unlock:
1269 + mmiowb();
1270 + spin_unlock(&sky2->tx_lock);
1271 +
1272 + dev->trans_start = jiffies;
1273 + return NETDEV_TX_OK;
1274 +}
1275 +
1276 +/*
1277 + * Free ring elements from starting at tx_cons until "done"
1278 + *
1279 + * NB: the hardware will tell us about partial completion of multi-part
1280 + * buffers; these are deferred until completion.
1281 + */
1282 +static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1283 +{
1284 + struct net_device *dev = sky2->netdev;
1285 + struct pci_dev *pdev = sky2->hw->pdev;
1286 + u16 nxt, put;
1287 + unsigned i;
1288 +
1289 + BUG_ON(done >= TX_RING_SIZE);
1290 +
1291 + if (unlikely(netif_msg_tx_done(sky2)))
1292 + printk(KERN_DEBUG "%s: tx done, up to %u\n",
1293 + dev->name, done);
1294 +
1295 + for (put = sky2->tx_cons; put != done; put = nxt) {
1296 + struct tx_ring_info *re = sky2->tx_ring + put;
1297 + struct sk_buff *skb = re->skb;
1298 +
1299 + nxt = re->idx;
1300 + BUG_ON(nxt >= TX_RING_SIZE);
1301 + prefetch(sky2->tx_ring + nxt);
1302 +
1303 + /* Check for partial status */
1304 + if (tx_dist(put, done) < tx_dist(put, nxt))
1305 + break;
1306 +
1307 + skb = re->skb;
1308 + pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1309 + skb_headlen(skb), PCI_DMA_TODEVICE);
1310 +
1311 + for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1312 + struct tx_ring_info *fre;
1313 + fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE;
1314 + pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
1315 + skb_shinfo(skb)->frags[i].size,
1316 + PCI_DMA_TODEVICE);
1317 + }
1318 +
1319 + dev_kfree_skb_any(skb);
1320 + }
1321 +
1322 + spin_lock(&sky2->tx_lock);
1323 + sky2->tx_cons = put;
1324 + if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
1325 + netif_wake_queue(dev);
1326 + spin_unlock(&sky2->tx_lock);
1327 +}
1328 +
1329 +/* Cleanup all untransmitted buffers, assume transmitter not running */
1330 +static void sky2_tx_clean(struct sky2_port *sky2)
1331 +{
1332 + sky2_tx_complete(sky2, sky2->tx_prod);
1333 +}
1334 +
1335 +/* Network shutdown */
1336 +static int sky2_down(struct net_device *dev)
1337 +{
1338 + struct sky2_port *sky2 = netdev_priv(dev);
1339 + struct sky2_hw *hw = sky2->hw;
1340 + unsigned port = sky2->port;
1341 + u16 ctrl;
1342 +
1343 + /* Never really got started! */
1344 + if (!sky2->tx_le)
1345 + return 0;
1346 +
1347 + if (netif_msg_ifdown(sky2))
1348 + printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1349 +
1350 + /* Stop more packets from being queued */
1351 + netif_stop_queue(dev);
1352 +
1353 + /* Disable port IRQ */
1354 + local_irq_disable();
1355 + hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1356 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
1357 + local_irq_enable();
1358 +
1359 + flush_scheduled_work();
1360 +
1361 + sky2_phy_reset(hw, port);
1362 +
1363 + /* Stop transmitter */
1364 + sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1365 + sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1366 +
1367 + sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1368 + RB_RST_SET | RB_DIS_OP_MD);
1369 +
1370 + ctrl = gma_read16(hw, port, GM_GP_CTRL);
1371 + ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1372 + gma_write16(hw, port, GM_GP_CTRL, ctrl);
1373 +
1374 + sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1375 +
1376 + /* Workaround shared GMAC reset */
1377 + if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1378 + && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1379 + sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1380 +
1381 + /* Disable Force Sync bit and Enable Alloc bit */
1382 + sky2_write8(hw, SK_REG(port, TXA_CTRL),
1383 + TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1384 +
1385 + /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1386 + sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1387 + sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1388 +
1389 + /* Reset the PCI FIFO of the async Tx queue */
1390 + sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1391 + BMU_RST_SET | BMU_FIFO_RST);
1392 +
1393 + /* Reset the Tx prefetch units */
1394 + sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1395 + PREF_UNIT_RST_SET);
1396 +
1397 + sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1398 +
1399 + sky2_rx_stop(sky2);
1400 +
1401 + sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1402 + sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1403 +
1404 + /* turn off LED's */
1405 + sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1406 +
1407 + synchronize_irq(hw->pdev->irq);
1408 +
1409 + sky2_tx_clean(sky2);
1410 + sky2_rx_clean(sky2);
1411 +
1412 + pci_free_consistent(hw->pdev, RX_LE_BYTES,
1413 + sky2->rx_le, sky2->rx_le_map);
1414 + kfree(sky2->rx_ring);
1415 +
1416 + pci_free_consistent(hw->pdev,
1417 + TX_RING_SIZE * sizeof(struct sky2_tx_le),
1418 + sky2->tx_le, sky2->tx_le_map);
1419 + kfree(sky2->tx_ring);
1420 +
1421 + sky2->tx_le = NULL;
1422 + sky2->rx_le = NULL;
1423 +
1424 + sky2->rx_ring = NULL;
1425 + sky2->tx_ring = NULL;
1426 +
1427 + return 0;
1428 +}
1429 +
1430 +static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1431 +{
1432 + if (!hw->copper)
1433 + return SPEED_1000;
1434 +
1435 + if (hw->chip_id == CHIP_ID_YUKON_FE)
1436 + return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1437 +
1438 + switch (aux & PHY_M_PS_SPEED_MSK) {
1439 + case PHY_M_PS_SPEED_1000:
1440 + return SPEED_1000;
1441 + case PHY_M_PS_SPEED_100:
1442 + return SPEED_100;
1443 + default:
1444 + return SPEED_10;
1445 + }
1446 +}
1447 +
1448 +static void sky2_link_up(struct sky2_port *sky2)
1449 +{
1450 + struct sky2_hw *hw = sky2->hw;
1451 + unsigned port = sky2->port;
1452 + u16 reg;
1453 +
1454 + /* Enable Transmit FIFO Underrun */
1455 + sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1456 +
1457 + reg = gma_read16(hw, port, GM_GP_CTRL);
1458 + if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1459 + reg |= GM_GPCR_DUP_FULL;
1460 +
1461 + /* enable Rx/Tx */
1462 + reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1463 + gma_write16(hw, port, GM_GP_CTRL, reg);
1464 + gma_read16(hw, port, GM_GP_CTRL);
1465 +
1466 + gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1467 +
1468 + netif_carrier_on(sky2->netdev);
1469 + netif_wake_queue(sky2->netdev);
1470 +
1471 + /* Turn on link LED */
1472 + sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1473 + LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1474 +
1475 + if (hw->chip_id == CHIP_ID_YUKON_XL) {
1476 + u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1477 +
1478 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1479 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1480 + PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1481 + SPEED_10 ? 7 : 0) |
1482 + PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1483 + SPEED_100 ? 7 : 0) |
1484 + PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1485 + SPEED_1000 ? 7 : 0));
1486 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1487 + }
1488 +
1489 + if (netif_msg_link(sky2))
1490 + printk(KERN_INFO PFX
1491 + "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1492 + sky2->netdev->name, sky2->speed,
1493 + sky2->duplex == DUPLEX_FULL ? "full" : "half",
1494 + (sky2->tx_pause && sky2->rx_pause) ? "both" :
1495 + sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1496 +}
1497 +
1498 +static void sky2_link_down(struct sky2_port *sky2)
1499 +{
1500 + struct sky2_hw *hw = sky2->hw;
1501 + unsigned port = sky2->port;
1502 + u16 reg;
1503 +
1504 + gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1505 +
1506 + reg = gma_read16(hw, port, GM_GP_CTRL);
1507 + reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1508 + gma_write16(hw, port, GM_GP_CTRL, reg);
1509 + gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1510 +
1511 + if (sky2->rx_pause && !sky2->tx_pause) {
1512 + /* restore Asymmetric Pause bit */
1513 + gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1514 + gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1515 + | PHY_M_AN_ASP);
1516 + }
1517 +
1518 + netif_carrier_off(sky2->netdev);
1519 + netif_stop_queue(sky2->netdev);
1520 +
1521 + /* Turn on link LED */
1522 + sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1523 +
1524 + if (netif_msg_link(sky2))
1525 + printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1526 + sky2_phy_init(hw, port);
1527 +}
1528 +
1529 +static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1530 +{
1531 + struct sky2_hw *hw = sky2->hw;
1532 + unsigned port = sky2->port;
1533 + u16 lpa;
1534 +
1535 + lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1536 +
1537 + if (lpa & PHY_M_AN_RF) {
1538 + printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1539 + return -1;
1540 + }
1541 +
1542 + if (hw->chip_id != CHIP_ID_YUKON_FE &&
1543 + gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1544 + printk(KERN_ERR PFX "%s: master/slave fault",
1545 + sky2->netdev->name);
1546 + return -1;
1547 + }
1548 +
1549 + if (!(aux & PHY_M_PS_SPDUP_RES)) {
1550 + printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1551 + sky2->netdev->name);
1552 + return -1;
1553 + }
1554 +
1555 + sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1556 +
1557 + sky2->speed = sky2_phy_speed(hw, aux);
1558 +
1559 + /* Pause bits are offset (9..8) */
1560 + if (hw->chip_id == CHIP_ID_YUKON_XL)
1561 + aux >>= 6;
1562 +
1563 + sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1564 + sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1565 +
1566 + if ((sky2->tx_pause || sky2->rx_pause)
1567 + && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1568 + sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1569 + else
1570 + sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1571 +
1572 + return 0;
1573 +}
1574 +
1575 +/*
1576 + * Interrupt from PHY are handled outside of interrupt context
1577 + * because accessing phy registers requires spin wait which might
1578 + * cause excess interrupt latency.
1579 + */
1580 +static void sky2_phy_task(void *arg)
1581 +{
1582 + struct sky2_port *sky2 = arg;
1583 + struct sky2_hw *hw = sky2->hw;
1584 + u16 istatus, phystat;
1585 +
1586 + down(&sky2->phy_sema);
1587 + istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1588 + phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
1589 +
1590 + if (netif_msg_intr(sky2))
1591 + printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1592 + sky2->netdev->name, istatus, phystat);
1593 +
1594 + if (istatus & PHY_M_IS_AN_COMPL) {
1595 + if (sky2_autoneg_done(sky2, phystat) == 0)
1596 + sky2_link_up(sky2);
1597 + goto out;
1598 + }
1599 +
1600 + if (istatus & PHY_M_IS_LSP_CHANGE)
1601 + sky2->speed = sky2_phy_speed(hw, phystat);
1602 +
1603 + if (istatus & PHY_M_IS_DUP_CHANGE)
1604 + sky2->duplex =
1605 + (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1606 +
1607 + if (istatus & PHY_M_IS_LST_CHANGE) {
1608 + if (phystat & PHY_M_PS_LINK_UP)
1609 + sky2_link_up(sky2);
1610 + else
1611 + sky2_link_down(sky2);
1612 + }
1613 +out:
1614 + up(&sky2->phy_sema);
1615 +
1616 + local_irq_disable();
1617 + hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
1618 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
1619 + local_irq_enable();
1620 +}
1621 +
1622 +static void sky2_tx_timeout(struct net_device *dev)
1623 +{
1624 + struct sky2_port *sky2 = netdev_priv(dev);
1625 + struct sky2_hw *hw = sky2->hw;
1626 + unsigned txq = txqaddr[sky2->port];
1627 +
1628 + if (netif_msg_timer(sky2))
1629 + printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1630 +
1631 + netif_stop_queue(dev);
1632 +
1633 + sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1634 + sky2_read32(hw, Q_ADDR(txq, Q_CSR));
1635 +
1636 + sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1637 +
1638 + sky2_tx_clean(sky2);
1639 +
1640 + sky2_qset(hw, txq);
1641 + sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1642 +
1643 + netif_wake_queue(dev);
1644 +}
1645 +
1646 +
1647 +#define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
1648 +/* Want receive buffer size to be multiple of 64 bits, and incl room for vlan */
1649 +static inline unsigned sky2_buf_size(int mtu)
1650 +{
1651 + return roundup(mtu + ETH_HLEN + 4, 8);
1652 +}
1653 +
1654 +static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1655 +{
1656 + struct sky2_port *sky2 = netdev_priv(dev);
1657 + struct sky2_hw *hw = sky2->hw;
1658 + int err;
1659 + u16 ctl, mode;
1660 +
1661 + if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1662 + return -EINVAL;
1663 +
1664 + if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1665 + return -EINVAL;
1666 +
1667 + if (!netif_running(dev)) {
1668 + dev->mtu = new_mtu;
1669 + return 0;
1670 + }
1671 +
1672 + sky2_write32(hw, B0_IMSK, 0);
1673 +
1674 + dev->trans_start = jiffies; /* prevent tx timeout */
1675 + netif_stop_queue(dev);
1676 + netif_poll_disable(hw->dev[0]);
1677 +
1678 + ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1679 + gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1680 + sky2_rx_stop(sky2);
1681 + sky2_rx_clean(sky2);
1682 +
1683 + dev->mtu = new_mtu;
1684 + sky2->rx_bufsize = sky2_buf_size(new_mtu);
1685 + mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1686 + GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1687 +
1688 + if (dev->mtu > ETH_DATA_LEN)
1689 + mode |= GM_SMOD_JUMBO_ENA;
1690 +
1691 + gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1692 +
1693 + sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1694 +
1695 + err = sky2_rx_start(sky2);
1696 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
1697 +
1698 + if (err)
1699 + dev_close(dev);
1700 + else {
1701 + gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1702 +
1703 + netif_poll_enable(hw->dev[0]);
1704 + netif_wake_queue(dev);
1705 + }
1706 +
1707 + return err;
1708 +}
1709 +
1710 +/*
1711 + * Receive one packet.
1712 + * For small packets or errors, just reuse existing skb.
1713 + * For larger packets, get new buffer.
1714 + */
1715 +static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1716 + u16 length, u32 status)
1717 +{
1718 + struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1719 + struct sk_buff *skb = NULL;
1720 +
1721 + if (unlikely(netif_msg_rx_status(sky2)))
1722 + printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1723 + sky2->netdev->name, sky2->rx_next, status, length);
1724 +
1725 + sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1726 + prefetch(sky2->rx_ring + sky2->rx_next);
1727 +
1728 + if (status & GMR_FS_ANY_ERR)
1729 + goto error;
1730 +
1731 + if (!(status & GMR_FS_RX_OK))
1732 + goto resubmit;
1733 +
1734 + if ((status >> 16) != length || length > sky2->rx_bufsize)
1735 + goto oversize;
1736 +
1737 + if (length < copybreak) {
1738 + skb = alloc_skb(length + 2, GFP_ATOMIC);
1739 + if (!skb)
1740 + goto resubmit;
1741 +
1742 + skb_reserve(skb, 2);
1743 + pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1744 + length, PCI_DMA_FROMDEVICE);
1745 + memcpy(skb->data, re->skb->data, length);
1746 + skb->ip_summed = re->skb->ip_summed;
1747 + skb->csum = re->skb->csum;
1748 + pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1749 + length, PCI_DMA_FROMDEVICE);
1750 + } else {
1751 + struct sk_buff *nskb;
1752 +
1753 + nskb = dev_alloc_skb(sky2->rx_bufsize);
1754 + if (!nskb)
1755 + goto resubmit;
1756 +
1757 + skb = re->skb;
1758 + re->skb = nskb;
1759 + pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1760 + sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1761 + prefetch(skb->data);
1762 +
1763 + re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1764 + sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1765 + }
1766 +
1767 + skb_put(skb, length);
1768 +resubmit:
1769 + re->skb->ip_summed = CHECKSUM_NONE;
1770 + sky2_rx_add(sky2, re->mapaddr);
1771 +
1772 + /* Tell receiver about new buffers. */
1773 + sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
1774 + &sky2->rx_last_put, RX_LE_SIZE);
1775 +
1776 + return skb;
1777 +
1778 +oversize:
1779 + ++sky2->net_stats.rx_over_errors;
1780 + goto resubmit;
1781 +
1782 +error:
1783 + ++sky2->net_stats.rx_errors;
1784 +
1785 + if (netif_msg_rx_err(sky2))
1786 + printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1787 + sky2->netdev->name, status, length);
1788 +
1789 + if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1790 + sky2->net_stats.rx_length_errors++;
1791 + if (status & GMR_FS_FRAGMENT)
1792 + sky2->net_stats.rx_frame_errors++;
1793 + if (status & GMR_FS_CRC_ERR)
1794 + sky2->net_stats.rx_crc_errors++;
1795 + if (status & GMR_FS_RX_FF_OV)
1796 + sky2->net_stats.rx_fifo_errors++;
1797 +
1798 + goto resubmit;
1799 +}
1800 +
1801 +/*
1802 + * Check for transmit complete
1803 + */
1804 +#define TX_NO_STATUS 0xffff
1805 +
1806 +static inline void sky2_tx_check(struct sky2_hw *hw, int port, u16 last)
1807 +{
1808 + if (last != TX_NO_STATUS) {
1809 + struct net_device *dev = hw->dev[port];
1810 + if (dev && netif_running(dev)) {
1811 + struct sky2_port *sky2 = netdev_priv(dev);
1812 + sky2_tx_complete(sky2, last);
1813 + }
1814 + }
1815 +}
1816 +
1817 +/*
1818 + * Both ports share the same status interrupt, therefore there is only
1819 + * one poll routine.
1820 + */
1821 +static int sky2_poll(struct net_device *dev0, int *budget)
1822 +{
1823 + struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1824 + unsigned int to_do = min(dev0->quota, *budget);
1825 + unsigned int work_done = 0;
1826 + u16 hwidx;
1827 + u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS };
1828 +
1829 + hwidx = sky2_read16(hw, STAT_PUT_IDX);
1830 + BUG_ON(hwidx >= STATUS_RING_SIZE);
1831 + rmb();
1832 +
1833 + while (hwidx != hw->st_idx) {
1834 + struct sky2_status_le *le = hw->st_le + hw->st_idx;
1835 + struct net_device *dev;
1836 + struct sky2_port *sky2;
1837 + struct sk_buff *skb;
1838 + u32 status;
1839 + u16 length;
1840 + u8 op;
1841 +
1842 + le = hw->st_le + hw->st_idx;
1843 + hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
1844 + prefetch(hw->st_le + hw->st_idx);
1845 +
1846 + BUG_ON(le->link >= 2);
1847 + dev = hw->dev[le->link];
1848 + if (dev == NULL || !netif_running(dev))
1849 + continue;
1850 +
1851 + sky2 = netdev_priv(dev);
1852 + status = le32_to_cpu(le->status);
1853 + length = le16_to_cpu(le->length);
1854 + op = le->opcode & ~HW_OWNER;
1855 + le->opcode = 0;
1856 +
1857 + switch (op) {
1858 + case OP_RXSTAT:
1859 + skb = sky2_receive(sky2, length, status);
1860 + if (!skb)
1861 + break;
1862 +
1863 + skb->dev = dev;
1864 + skb->protocol = eth_type_trans(skb, dev);
1865 + dev->last_rx = jiffies;
1866 +
1867 +#ifdef SKY2_VLAN_TAG_USED
1868 + if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1869 + vlan_hwaccel_receive_skb(skb,
1870 + sky2->vlgrp,
1871 + be16_to_cpu(sky2->rx_tag));
1872 + } else
1873 +#endif
1874 + netif_receive_skb(skb);
1875 +
1876 + if (++work_done >= to_do)
1877 + goto exit_loop;
1878 + break;
1879 +
1880 +#ifdef SKY2_VLAN_TAG_USED
1881 + case OP_RXVLAN:
1882 + sky2->rx_tag = length;
1883 + break;
1884 +
1885 + case OP_RXCHKSVLAN:
1886 + sky2->rx_tag = length;
1887 + /* fall through */
1888 +#endif
1889 + case OP_RXCHKS:
1890 + skb = sky2->rx_ring[sky2->rx_next].skb;
1891 + skb->ip_summed = CHECKSUM_HW;
1892 + skb->csum = le16_to_cpu(status);
1893 + break;
1894 +
1895 + case OP_TXINDEXLE:
1896 + /* TX index reports status for both ports */
1897 + tx_done[0] = status & 0xffff;
1898 + tx_done[1] = ((status >> 24) & 0xff)
1899 + | (u16)(length & 0xf) << 8;
1900 + break;
1901 +
1902 + default:
1903 + if (net_ratelimit())
1904 + printk(KERN_WARNING PFX
1905 + "unknown status opcode 0x%x\n", op);
1906 + break;
1907 + }
1908 + }
1909 +
1910 +exit_loop:
1911 + sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1912 + mmiowb();
1913 +
1914 + sky2_tx_check(hw, 0, tx_done[0]);
1915 + sky2_tx_check(hw, 1, tx_done[1]);
1916 +
1917 + if (sky2_read16(hw, STAT_PUT_IDX) == hw->st_idx) {
1918 + /* need to restart TX timer */
1919 + if (is_ec_a1(hw)) {
1920 + sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1921 + sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1922 + }
1923 +
1924 + netif_rx_complete(dev0);
1925 + hw->intr_mask |= Y2_IS_STAT_BMU;
1926 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
1927 + mmiowb();
1928 + return 0;
1929 + } else {
1930 + *budget -= work_done;
1931 + dev0->quota -= work_done;
1932 + return 1;
1933 + }
1934 +}
1935 +
1936 +static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1937 +{
1938 + struct net_device *dev = hw->dev[port];
1939 +
1940 + printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1941 + dev->name, status);
1942 +
1943 + if (status & Y2_IS_PAR_RD1) {
1944 + printk(KERN_ERR PFX "%s: ram data read parity error\n",
1945 + dev->name);
1946 + /* Clear IRQ */
1947 + sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1948 + }
1949 +
1950 + if (status & Y2_IS_PAR_WR1) {
1951 + printk(KERN_ERR PFX "%s: ram data write parity error\n",
1952 + dev->name);
1953 +
1954 + sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1955 + }
1956 +
1957 + if (status & Y2_IS_PAR_MAC1) {
1958 + printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
1959 + sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1960 + }
1961 +
1962 + if (status & Y2_IS_PAR_RX1) {
1963 + printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
1964 + sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1965 + }
1966 +
1967 + if (status & Y2_IS_TCP_TXA1) {
1968 + printk(KERN_ERR PFX "%s: TCP segmentation error\n", dev->name);
1969 + sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1970 + }
1971 +}
1972 +
1973 +static void sky2_hw_intr(struct sky2_hw *hw)
1974 +{
1975 + u32 status = sky2_read32(hw, B0_HWE_ISRC);
1976 +
1977 + if (status & Y2_IS_TIST_OV)
1978 + sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1979 +
1980 + if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
1981 + u16 pci_err;
1982 +
1983 + pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
1984 + printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
1985 + pci_name(hw->pdev), pci_err);
1986 +
1987 + sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1988 + pci_write_config_word(hw->pdev, PCI_STATUS,
1989 + pci_err | PCI_STATUS_ERROR_BITS);
1990 + sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1991 + }
1992 +
1993 + if (status & Y2_IS_PCI_EXP) {
1994 + /* PCI-Express uncorrectable Error occurred */
1995 + u32 pex_err;
1996 +
1997 + pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
1998 +
1999 + printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2000 + pci_name(hw->pdev), pex_err);
2001 +
2002 + /* clear the interrupt */
2003 + sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2004 + pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
2005 + 0xffffffffUL);
2006 + sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2007 +
2008 + if (pex_err & PEX_FATAL_ERRORS) {
2009 + u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2010 + hwmsk &= ~Y2_IS_PCI_EXP;
2011 + sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2012 + }
2013 + }
2014 +
2015 + if (status & Y2_HWE_L1_MASK)
2016 + sky2_hw_error(hw, 0, status);
2017 + status >>= 8;
2018 + if (status & Y2_HWE_L1_MASK)
2019 + sky2_hw_error(hw, 1, status);
2020 +}
2021 +
2022 +static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2023 +{
2024 + struct net_device *dev = hw->dev[port];
2025 + struct sky2_port *sky2 = netdev_priv(dev);
2026 + u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2027 +
2028 + if (netif_msg_intr(sky2))
2029 + printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2030 + dev->name, status);
2031 +
2032 + if (status & GM_IS_RX_FF_OR) {
2033 + ++sky2->net_stats.rx_fifo_errors;
2034 + sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2035 + }
2036 +
2037 + if (status & GM_IS_TX_FF_UR) {
2038 + ++sky2->net_stats.tx_fifo_errors;
2039 + sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2040 + }
2041 +}
2042 +
2043 +static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2044 +{
2045 + struct net_device *dev = hw->dev[port];
2046 + struct sky2_port *sky2 = netdev_priv(dev);
2047 +
2048 + hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
2049 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
2050 + schedule_work(&sky2->phy_task);
2051 +}
2052 +
2053 +static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2054 +{
2055 + struct sky2_hw *hw = dev_id;
2056 + struct net_device *dev0 = hw->dev[0];
2057 + u32 status;
2058 +
2059 + status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2060 + if (status == 0 || status == ~0)
2061 + return IRQ_NONE;
2062 +
2063 + if (status & Y2_IS_HW_ERR)
2064 + sky2_hw_intr(hw);
2065 +
2066 + /* Do NAPI for Rx and Tx status */
2067 + if (status & Y2_IS_STAT_BMU) {
2068 + hw->intr_mask &= ~Y2_IS_STAT_BMU;
2069 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
2070 +
2071 + if (likely(__netif_rx_schedule_prep(dev0))) {
2072 + prefetch(&hw->st_le[hw->st_idx]);
2073 + __netif_rx_schedule(dev0);
2074 + }
2075 + }
2076 +
2077 + if (status & Y2_IS_IRQ_PHY1)
2078 + sky2_phy_intr(hw, 0);
2079 +
2080 + if (status & Y2_IS_IRQ_PHY2)
2081 + sky2_phy_intr(hw, 1);
2082 +
2083 + if (status & Y2_IS_IRQ_MAC1)
2084 + sky2_mac_intr(hw, 0);
2085 +
2086 + if (status & Y2_IS_IRQ_MAC2)
2087 + sky2_mac_intr(hw, 1);
2088 +
2089 + sky2_write32(hw, B0_Y2_SP_ICR, 2);
2090 +
2091 + sky2_read32(hw, B0_IMSK);
2092 +
2093 + return IRQ_HANDLED;
2094 +}
2095 +
2096 +#ifdef CONFIG_NET_POLL_CONTROLLER
2097 +static void sky2_netpoll(struct net_device *dev)
2098 +{
2099 + struct sky2_port *sky2 = netdev_priv(dev);
2100 +
2101 + sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
2102 +}
2103 +#endif
2104 +
2105 +/* Chip internal frequency for clock calculations */
2106 +static inline u32 sky2_mhz(const struct sky2_hw *hw)
2107 +{
2108 + switch (hw->chip_id) {
2109 + case CHIP_ID_YUKON_EC:
2110 + case CHIP_ID_YUKON_EC_U:
2111 + return 125; /* 125 Mhz */
2112 + case CHIP_ID_YUKON_FE:
2113 + return 100; /* 100 Mhz */
2114 + default: /* YUKON_XL */
2115 + return 156; /* 156 Mhz */
2116 + }
2117 +}
2118 +
2119 +static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2120 +{
2121 + return sky2_mhz(hw) * us;
2122 +}
2123 +
2124 +static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2125 +{
2126 + return clk / sky2_mhz(hw);
2127 +}
2128 +
2129 +
2130 +static int sky2_reset(struct sky2_hw *hw)
2131 +{
2132 + u32 ctst;
2133 + u16 status;
2134 + u8 t8, pmd_type;
2135 + int i;
2136 +
2137 + ctst = sky2_read32(hw, B0_CTST);
2138 +
2139 + sky2_write8(hw, B0_CTST, CS_RST_CLR);
2140 + hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2141 + if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2142 + printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2143 + pci_name(hw->pdev), hw->chip_id);
2144 + return -EOPNOTSUPP;
2145 + }
2146 +
2147 + /* ring for status responses */
2148 + hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
2149 + &hw->st_dma);
2150 + if (!hw->st_le)
2151 + return -ENOMEM;
2152 +
2153 + /* disable ASF */
2154 + if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2155 + sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2156 + sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2157 + }
2158 +
2159 + /* do a SW reset */
2160 + sky2_write8(hw, B0_CTST, CS_RST_SET);
2161 + sky2_write8(hw, B0_CTST, CS_RST_CLR);
2162 +
2163 + /* clear PCI errors, if any */
2164 + pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2165 + sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2166 + pci_write_config_word(hw->pdev, PCI_STATUS,
2167 + status | PCI_STATUS_ERROR_BITS);
2168 +
2169 + sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2170 +
2171 + /* clear any PEX errors */
2172 + if (is_pciex(hw)) {
2173 + u16 lstat;
2174 + pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
2175 + 0xffffffffUL);
2176 + pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat);
2177 + }
2178 +
2179 + pmd_type = sky2_read8(hw, B2_PMD_TYP);
2180 + hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2181 +
2182 + hw->ports = 1;
2183 + t8 = sky2_read8(hw, B2_Y2_HW_RES);
2184 + if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2185 + if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2186 + ++hw->ports;
2187 + }
2188 + hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2189 +
2190 + sky2_set_power_state(hw, PCI_D0);
2191 +
2192 + for (i = 0; i < hw->ports; i++) {
2193 + sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2194 + sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2195 + }
2196 +
2197 + sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2198 +
2199 + /* Clear I2C IRQ noise */
2200 + sky2_write32(hw, B2_I2C_IRQ, 1);
2201 +
2202 + /* turn off hardware timer (unused) */
2203 + sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2204 + sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2205 +
2206 + sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2207 +
2208 + /* Turn off descriptor polling */
2209 + sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2210 +
2211 + /* Turn off receive timestamp */
2212 + sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2213 + sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2214 +
2215 + /* enable the Tx Arbiters */
2216 + for (i = 0; i < hw->ports; i++)
2217 + sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2218 +
2219 + /* Initialize ram interface */
2220 + for (i = 0; i < hw->ports; i++) {
2221 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2222 +
2223 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2224 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2225 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2226 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2227 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2228 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2229 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2230 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2231 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2232 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2233 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2234 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2235 + }
2236 +
2237 + sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2238 +
2239 + for (i = 0; i < hw->ports; i++)
2240 + sky2_phy_reset(hw, i);
2241 +
2242 + memset(hw->st_le, 0, STATUS_LE_BYTES);
2243 + hw->st_idx = 0;
2244 +
2245 + sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2246 + sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2247 +
2248 + sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2249 + sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2250 +
2251 + /* Set the list last index */
2252 + sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2253 +
2254 + /* These status setup values are copied from SysKonnect's driver */
2255 + if (is_ec_a1(hw)) {
2256 + /* WA for dev. #4.3 */
2257 + sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
2258 +
2259 + /* set Status-FIFO watermark */
2260 + sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
2261 +
2262 + /* set Status-FIFO ISR watermark */
2263 + sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
2264 + sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 10000));
2265 + } else {
2266 + sky2_write16(hw, STAT_TX_IDX_TH, 10);
2267 + sky2_write8(hw, STAT_FIFO_WM, 16);
2268 +
2269 + /* set Status-FIFO ISR watermark */
2270 + if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2271 + sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2272 + else
2273 + sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2274 +
2275 + sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2276 + sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2277 + sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2278 + }
2279 +
2280 + /* enable status unit */
2281 + sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2282 +
2283 + sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2284 + sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2285 + sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2286 +
2287 + return 0;
2288 +}
2289 +
2290 +static inline u32 sky2_supported_modes(const struct sky2_hw *hw)
2291 +{
2292 + u32 modes;
2293 + if (hw->copper) {
2294 + modes = SUPPORTED_10baseT_Half
2295 + | SUPPORTED_10baseT_Full
2296 + | SUPPORTED_100baseT_Half
2297 + | SUPPORTED_100baseT_Full
2298 + | SUPPORTED_Autoneg | SUPPORTED_TP;
2299 +
2300 + if (hw->chip_id != CHIP_ID_YUKON_FE)
2301 + modes |= SUPPORTED_1000baseT_Half
2302 + | SUPPORTED_1000baseT_Full;
2303 + } else
2304 + modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
2305 + | SUPPORTED_Autoneg;
2306 + return modes;
2307 +}
2308 +
2309 +static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2310 +{
2311 + struct sky2_port *sky2 = netdev_priv(dev);
2312 + struct sky2_hw *hw = sky2->hw;
2313 +
2314 + ecmd->transceiver = XCVR_INTERNAL;
2315 + ecmd->supported = sky2_supported_modes(hw);
2316 + ecmd->phy_address = PHY_ADDR_MARV;
2317 + if (hw->copper) {
2318 + ecmd->supported = SUPPORTED_10baseT_Half
2319 + | SUPPORTED_10baseT_Full
2320 + | SUPPORTED_100baseT_Half
2321 + | SUPPORTED_100baseT_Full
2322 + | SUPPORTED_1000baseT_Half
2323 + | SUPPORTED_1000baseT_Full
2324 + | SUPPORTED_Autoneg | SUPPORTED_TP;
2325 + ecmd->port = PORT_TP;
2326 + } else
2327 + ecmd->port = PORT_FIBRE;
2328 +
2329 + ecmd->advertising = sky2->advertising;
2330 + ecmd->autoneg = sky2->autoneg;
2331 + ecmd->speed = sky2->speed;
2332 + ecmd->duplex = sky2->duplex;
2333 + return 0;
2334 +}
2335 +
2336 +static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2337 +{
2338 + struct sky2_port *sky2 = netdev_priv(dev);
2339 + const struct sky2_hw *hw = sky2->hw;
2340 + u32 supported = sky2_supported_modes(hw);
2341 +
2342 + if (ecmd->autoneg == AUTONEG_ENABLE) {
2343 + ecmd->advertising = supported;
2344 + sky2->duplex = -1;
2345 + sky2->speed = -1;
2346 + } else {
2347 + u32 setting;
2348 +
2349 + switch (ecmd->speed) {
2350 + case SPEED_1000:
2351 + if (ecmd->duplex == DUPLEX_FULL)
2352 + setting = SUPPORTED_1000baseT_Full;
2353 + else if (ecmd->duplex == DUPLEX_HALF)
2354 + setting = SUPPORTED_1000baseT_Half;
2355 + else
2356 + return -EINVAL;
2357 + break;
2358 + case SPEED_100:
2359 + if (ecmd->duplex == DUPLEX_FULL)
2360 + setting = SUPPORTED_100baseT_Full;
2361 + else if (ecmd->duplex == DUPLEX_HALF)
2362 + setting = SUPPORTED_100baseT_Half;
2363 + else
2364 + return -EINVAL;
2365 + break;
2366 +
2367 + case SPEED_10:
2368 + if (ecmd->duplex == DUPLEX_FULL)
2369 + setting = SUPPORTED_10baseT_Full;
2370 + else if (ecmd->duplex == DUPLEX_HALF)
2371 + setting = SUPPORTED_10baseT_Half;
2372 + else
2373 + return -EINVAL;
2374 + break;
2375 + default:
2376 + return -EINVAL;
2377 + }
2378 +
2379 + if ((setting & supported) == 0)
2380 + return -EINVAL;
2381 +
2382 + sky2->speed = ecmd->speed;
2383 + sky2->duplex = ecmd->duplex;
2384 + }
2385 +
2386 + sky2->autoneg = ecmd->autoneg;
2387 + sky2->advertising = ecmd->advertising;
2388 +
2389 + if (netif_running(dev))
2390 + sky2_phy_reinit(sky2);
2391 +
2392 + return 0;
2393 +}
2394 +
2395 +static void sky2_get_drvinfo(struct net_device *dev,
2396 + struct ethtool_drvinfo *info)
2397 +{
2398 + struct sky2_port *sky2 = netdev_priv(dev);
2399 +
2400 + strcpy(info->driver, DRV_NAME);
2401 + strcpy(info->version, DRV_VERSION);
2402 + strcpy(info->fw_version, "N/A");
2403 + strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2404 +}
2405 +
2406 +static const struct sky2_stat {
2407 + char name[ETH_GSTRING_LEN];
2408 + u16 offset;
2409 +} sky2_stats[] = {
2410 + { "tx_bytes", GM_TXO_OK_HI },
2411 + { "rx_bytes", GM_RXO_OK_HI },
2412 + { "tx_broadcast", GM_TXF_BC_OK },
2413 + { "rx_broadcast", GM_RXF_BC_OK },
2414 + { "tx_multicast", GM_TXF_MC_OK },
2415 + { "rx_multicast", GM_RXF_MC_OK },
2416 + { "tx_unicast", GM_TXF_UC_OK },
2417 + { "rx_unicast", GM_RXF_UC_OK },
2418 + { "tx_mac_pause", GM_TXF_MPAUSE },
2419 + { "rx_mac_pause", GM_RXF_MPAUSE },
2420 + { "collisions", GM_TXF_SNG_COL },
2421 + { "late_collision",GM_TXF_LAT_COL },
2422 + { "aborted", GM_TXF_ABO_COL },
2423 + { "multi_collisions", GM_TXF_MUL_COL },
2424 + { "fifo_underrun", GM_TXE_FIFO_UR },
2425 + { "fifo_overflow", GM_RXE_FIFO_OV },
2426 + { "rx_toolong", GM_RXF_LNG_ERR },
2427 + { "rx_jabber", GM_RXF_JAB_PKT },
2428 + { "rx_runt", GM_RXE_FRAG },
2429 + { "rx_too_long", GM_RXF_LNG_ERR },
2430 + { "rx_fcs_error", GM_RXF_FCS_ERR },
2431 +};
2432 +
2433 +static u32 sky2_get_rx_csum(struct net_device *dev)
2434 +{
2435 + struct sky2_port *sky2 = netdev_priv(dev);
2436 +
2437 + return sky2->rx_csum;
2438 +}
2439 +
2440 +static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2441 +{
2442 + struct sky2_port *sky2 = netdev_priv(dev);
2443 +
2444 + sky2->rx_csum = data;
2445 +
2446 + sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2447 + data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2448 +
2449 + return 0;
2450 +}
2451 +
2452 +static u32 sky2_get_msglevel(struct net_device *netdev)
2453 +{
2454 + struct sky2_port *sky2 = netdev_priv(netdev);
2455 + return sky2->msg_enable;
2456 +}
2457 +
2458 +static int sky2_nway_reset(struct net_device *dev)
2459 +{
2460 + struct sky2_port *sky2 = netdev_priv(dev);
2461 +
2462 + if (sky2->autoneg != AUTONEG_ENABLE)
2463 + return -EINVAL;
2464 +
2465 + sky2_phy_reinit(sky2);
2466 +
2467 + return 0;
2468 +}
2469 +
2470 +static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2471 +{
2472 + struct sky2_hw *hw = sky2->hw;
2473 + unsigned port = sky2->port;
2474 + int i;
2475 +
2476 + data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2477 + | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2478 + data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2479 + | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2480 +
2481 + for (i = 2; i < count; i++)
2482 + data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2483 +}
2484 +
2485 +static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2486 +{
2487 + struct sky2_port *sky2 = netdev_priv(netdev);
2488 + sky2->msg_enable = value;
2489 +}
2490 +
2491 +static int sky2_get_stats_count(struct net_device *dev)
2492 +{
2493 + return ARRAY_SIZE(sky2_stats);
2494 +}
2495 +
2496 +static void sky2_get_ethtool_stats(struct net_device *dev,
2497 + struct ethtool_stats *stats, u64 * data)
2498 +{
2499 + struct sky2_port *sky2 = netdev_priv(dev);
2500 +
2501 + sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2502 +}
2503 +
2504 +static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2505 +{
2506 + int i;
2507 +
2508 + switch (stringset) {
2509 + case ETH_SS_STATS:
2510 + for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2511 + memcpy(data + i * ETH_GSTRING_LEN,
2512 + sky2_stats[i].name, ETH_GSTRING_LEN);
2513 + break;
2514 + }
2515 +}
2516 +
2517 +/* Use hardware MIB variables for critical path statistics and
2518 + * transmit feedback not reported at interrupt.
2519 + * Other errors are accounted for in interrupt handler.
2520 + */
2521 +static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2522 +{
2523 + struct sky2_port *sky2 = netdev_priv(dev);
2524 + u64 data[13];
2525 +
2526 + sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2527 +
2528 + sky2->net_stats.tx_bytes = data[0];
2529 + sky2->net_stats.rx_bytes = data[1];
2530 + sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2531 + sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2532 + sky2->net_stats.multicast = data[5] + data[7];
2533 + sky2->net_stats.collisions = data[10];
2534 + sky2->net_stats.tx_aborted_errors = data[12];
2535 +
2536 + return &sky2->net_stats;
2537 +}
2538 +
2539 +static int sky2_set_mac_address(struct net_device *dev, void *p)
2540 +{
2541 + struct sky2_port *sky2 = netdev_priv(dev);
2542 + struct sockaddr *addr = p;
2543 +
2544 + if (!is_valid_ether_addr(addr->sa_data))
2545 + return -EADDRNOTAVAIL;
2546 +
2547 + memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2548 + memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8,
2549 + dev->dev_addr, ETH_ALEN);
2550 + memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8,
2551 + dev->dev_addr, ETH_ALEN);
2552 +
2553 + if (netif_running(dev))
2554 + sky2_phy_reinit(sky2);
2555 +
2556 + return 0;
2557 +}
2558 +
2559 +static void sky2_set_multicast(struct net_device *dev)
2560 +{
2561 + struct sky2_port *sky2 = netdev_priv(dev);
2562 + struct sky2_hw *hw = sky2->hw;
2563 + unsigned port = sky2->port;
2564 + struct dev_mc_list *list = dev->mc_list;
2565 + u16 reg;
2566 + u8 filter[8];
2567 +
2568 + memset(filter, 0, sizeof(filter));
2569 +
2570 + reg = gma_read16(hw, port, GM_RX_CTRL);
2571 + reg |= GM_RXCR_UCF_ENA;
2572 +
2573 + if (dev->flags & IFF_PROMISC) /* promiscuous */
2574 + reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2575 + else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2576 + memset(filter, 0xff, sizeof(filter));
2577 + else if (dev->mc_count == 0) /* no multicast */
2578 + reg &= ~GM_RXCR_MCF_ENA;
2579 + else {
2580 + int i;
2581 + reg |= GM_RXCR_MCF_ENA;
2582 +
2583 + for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2584 + u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2585 + filter[bit / 8] |= 1 << (bit % 8);
2586 + }
2587 + }
2588 +
2589 + gma_write16(hw, port, GM_MC_ADDR_H1,
2590 + (u16) filter[0] | ((u16) filter[1] << 8));
2591 + gma_write16(hw, port, GM_MC_ADDR_H2,
2592 + (u16) filter[2] | ((u16) filter[3] << 8));
2593 + gma_write16(hw, port, GM_MC_ADDR_H3,
2594 + (u16) filter[4] | ((u16) filter[5] << 8));
2595 + gma_write16(hw, port, GM_MC_ADDR_H4,
2596 + (u16) filter[6] | ((u16) filter[7] << 8));
2597 +
2598 + gma_write16(hw, port, GM_RX_CTRL, reg);
2599 +}
2600 +
2601 +/* Can have one global because blinking is controlled by
2602 + * ethtool and that is always under RTNL mutex
2603 + */
2604 +static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2605 +{
2606 + u16 pg;
2607 +
2608 + switch (hw->chip_id) {
2609 + case CHIP_ID_YUKON_XL:
2610 + pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2611 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2612 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2613 + on ? (PHY_M_LEDC_LOS_CTRL(1) |
2614 + PHY_M_LEDC_INIT_CTRL(7) |
2615 + PHY_M_LEDC_STA1_CTRL(7) |
2616 + PHY_M_LEDC_STA0_CTRL(7))
2617 + : 0);
2618 +
2619 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2620 + break;
2621 +
2622 + default:
2623 + gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2624 + gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2625 + on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2626 + PHY_M_LED_MO_10(MO_LED_ON) |
2627 + PHY_M_LED_MO_100(MO_LED_ON) |
2628 + PHY_M_LED_MO_1000(MO_LED_ON) |
2629 + PHY_M_LED_MO_RX(MO_LED_ON)
2630 + : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2631 + PHY_M_LED_MO_10(MO_LED_OFF) |
2632 + PHY_M_LED_MO_100(MO_LED_OFF) |
2633 + PHY_M_LED_MO_1000(MO_LED_OFF) |
2634 + PHY_M_LED_MO_RX(MO_LED_OFF));
2635 +
2636 + }
2637 +}
2638 +
2639 +/* blink LED's for finding board */
2640 +static int sky2_phys_id(struct net_device *dev, u32 data)
2641 +{
2642 + struct sky2_port *sky2 = netdev_priv(dev);
2643 + struct sky2_hw *hw = sky2->hw;
2644 + unsigned port = sky2->port;
2645 + u16 ledctrl, ledover = 0;
2646 + long ms;
2647 + int interrupted;
2648 + int onoff = 1;
2649 +
2650 + if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2651 + ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2652 + else
2653 + ms = data * 1000;
2654 +
2655 + /* save initial values */
2656 + down(&sky2->phy_sema);
2657 + if (hw->chip_id == CHIP_ID_YUKON_XL) {
2658 + u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2659 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2660 + ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2661 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2662 + } else {
2663 + ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2664 + ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2665 + }
2666 +
2667 + interrupted = 0;
2668 + while (!interrupted && ms > 0) {
2669 + sky2_led(hw, port, onoff);
2670 + onoff = !onoff;
2671 +
2672 + up(&sky2->phy_sema);
2673 + interrupted = msleep_interruptible(250);
2674 + down(&sky2->phy_sema);
2675 +
2676 + ms -= 250;
2677 + }
2678 +
2679 + /* resume regularly scheduled programming */
2680 + if (hw->chip_id == CHIP_ID_YUKON_XL) {
2681 + u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2682 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2683 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2684 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2685 + } else {
2686 + gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2687 + gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2688 + }
2689 + up(&sky2->phy_sema);
2690 +
2691 + return 0;
2692 +}
2693 +
2694 +static void sky2_get_pauseparam(struct net_device *dev,
2695 + struct ethtool_pauseparam *ecmd)
2696 +{
2697 + struct sky2_port *sky2 = netdev_priv(dev);
2698 +
2699 + ecmd->tx_pause = sky2->tx_pause;
2700 + ecmd->rx_pause = sky2->rx_pause;
2701 + ecmd->autoneg = sky2->autoneg;
2702 +}
2703 +
2704 +static int sky2_set_pauseparam(struct net_device *dev,
2705 + struct ethtool_pauseparam *ecmd)
2706 +{
2707 + struct sky2_port *sky2 = netdev_priv(dev);
2708 + int err = 0;
2709 +
2710 + sky2->autoneg = ecmd->autoneg;
2711 + sky2->tx_pause = ecmd->tx_pause != 0;
2712 + sky2->rx_pause = ecmd->rx_pause != 0;
2713 +
2714 + sky2_phy_reinit(sky2);
2715 +
2716 + return err;
2717 +}
2718 +
2719 +#ifdef CONFIG_PM
2720 +static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2721 +{
2722 + struct sky2_port *sky2 = netdev_priv(dev);
2723 +
2724 + wol->supported = WAKE_MAGIC;
2725 + wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2726 +}
2727 +
2728 +static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2729 +{
2730 + struct sky2_port *sky2 = netdev_priv(dev);
2731 + struct sky2_hw *hw = sky2->hw;
2732 +
2733 + if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2734 + return -EOPNOTSUPP;
2735 +
2736 + sky2->wol = wol->wolopts == WAKE_MAGIC;
2737 +
2738 + if (sky2->wol) {
2739 + memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2740 +
2741 + sky2_write16(hw, WOL_CTRL_STAT,
2742 + WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2743 + WOL_CTL_ENA_MAGIC_PKT_UNIT);
2744 + } else
2745 + sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2746 +
2747 + return 0;
2748 +}
2749 +#endif
2750 +
2751 +static int sky2_get_coalesce(struct net_device *dev,
2752 + struct ethtool_coalesce *ecmd)
2753 +{
2754 + struct sky2_port *sky2 = netdev_priv(dev);
2755 + struct sky2_hw *hw = sky2->hw;
2756 +
2757 + if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2758 + ecmd->tx_coalesce_usecs = 0;
2759 + else {
2760 + u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2761 + ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2762 + }
2763 + ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2764 +
2765 + if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2766 + ecmd->rx_coalesce_usecs = 0;
2767 + else {
2768 + u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2769 + ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2770 + }
2771 + ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2772 +
2773 + if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2774 + ecmd->rx_coalesce_usecs_irq = 0;
2775 + else {
2776 + u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2777 + ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2778 + }
2779 +
2780 + ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2781 +
2782 + return 0;
2783 +}
2784 +
2785 +/* Note: this affect both ports */
2786 +static int sky2_set_coalesce(struct net_device *dev,
2787 + struct ethtool_coalesce *ecmd)
2788 +{
2789 + struct sky2_port *sky2 = netdev_priv(dev);
2790 + struct sky2_hw *hw = sky2->hw;
2791 + const u32 tmin = sky2_clk2us(hw, 1);
2792 + const u32 tmax = 5000;
2793 +
2794 + if (ecmd->tx_coalesce_usecs != 0 &&
2795 + (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax))
2796 + return -EINVAL;
2797 +
2798 + if (ecmd->rx_coalesce_usecs != 0 &&
2799 + (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax))
2800 + return -EINVAL;
2801 +
2802 + if (ecmd->rx_coalesce_usecs_irq != 0 &&
2803 + (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax))
2804 + return -EINVAL;
2805 +
2806 + if (ecmd->tx_max_coalesced_frames > 0xffff)
2807 + return -EINVAL;
2808 + if (ecmd->rx_max_coalesced_frames > 0xff)
2809 + return -EINVAL;
2810 + if (ecmd->rx_max_coalesced_frames_irq > 0xff)
2811 + return -EINVAL;
2812 +
2813 + if (ecmd->tx_coalesce_usecs == 0)
2814 + sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2815 + else {
2816 + sky2_write32(hw, STAT_TX_TIMER_INI,
2817 + sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2818 + sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2819 + }
2820 + sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2821 +
2822 + if (ecmd->rx_coalesce_usecs == 0)
2823 + sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2824 + else {
2825 + sky2_write32(hw, STAT_LEV_TIMER_INI,
2826 + sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2827 + sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2828 + }
2829 + sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2830 +
2831 + if (ecmd->rx_coalesce_usecs_irq == 0)
2832 + sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2833 + else {
2834 + sky2_write32(hw, STAT_TX_TIMER_INI,
2835 + sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2836 + sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2837 + }
2838 + sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2839 + return 0;
2840 +}
2841 +
2842 +static void sky2_get_ringparam(struct net_device *dev,
2843 + struct ethtool_ringparam *ering)
2844 +{
2845 + struct sky2_port *sky2 = netdev_priv(dev);
2846 +
2847 + ering->rx_max_pending = RX_MAX_PENDING;
2848 + ering->rx_mini_max_pending = 0;
2849 + ering->rx_jumbo_max_pending = 0;
2850 + ering->tx_max_pending = TX_RING_SIZE - 1;
2851 +
2852 + ering->rx_pending = sky2->rx_pending;
2853 + ering->rx_mini_pending = 0;
2854 + ering->rx_jumbo_pending = 0;
2855 + ering->tx_pending = sky2->tx_pending;
2856 +}
2857 +
2858 +static int sky2_set_ringparam(struct net_device *dev,
2859 + struct ethtool_ringparam *ering)
2860 +{
2861 + struct sky2_port *sky2 = netdev_priv(dev);
2862 + int err = 0;
2863 +
2864 + if (ering->rx_pending > RX_MAX_PENDING ||
2865 + ering->rx_pending < 8 ||
2866 + ering->tx_pending < MAX_SKB_TX_LE ||
2867 + ering->tx_pending > TX_RING_SIZE - 1)
2868 + return -EINVAL;
2869 +
2870 + if (netif_running(dev))
2871 + sky2_down(dev);
2872 +
2873 + sky2->rx_pending = ering->rx_pending;
2874 + sky2->tx_pending = ering->tx_pending;
2875 +
2876 + if (netif_running(dev)) {
2877 + err = sky2_up(dev);
2878 + if (err)
2879 + dev_close(dev);
2880 + else
2881 + sky2_set_multicast(dev);
2882 + }
2883 +
2884 + return err;
2885 +}
2886 +
2887 +static int sky2_get_regs_len(struct net_device *dev)
2888 +{
2889 + return 0x4000;
2890 +}
2891 +
2892 +/*
2893 + * Returns copy of control register region
2894 + * Note: access to the RAM address register set will cause timeouts.
2895 + */
2896 +static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2897 + void *p)
2898 +{
2899 + const struct sky2_port *sky2 = netdev_priv(dev);
2900 + const void __iomem *io = sky2->hw->regs;
2901 +
2902 + BUG_ON(regs->len < B3_RI_WTO_R1);
2903 + regs->version = 1;
2904 + memset(p, 0, regs->len);
2905 +
2906 + memcpy_fromio(p, io, B3_RAM_ADDR);
2907 +
2908 + memcpy_fromio(p + B3_RI_WTO_R1,
2909 + io + B3_RI_WTO_R1,
2910 + regs->len - B3_RI_WTO_R1);
2911 +}
2912 +
2913 +static struct ethtool_ops sky2_ethtool_ops = {
2914 + .get_settings = sky2_get_settings,
2915 + .set_settings = sky2_set_settings,
2916 + .get_drvinfo = sky2_get_drvinfo,
2917 + .get_msglevel = sky2_get_msglevel,
2918 + .set_msglevel = sky2_set_msglevel,
2919 + .nway_reset = sky2_nway_reset,
2920 + .get_regs_len = sky2_get_regs_len,
2921 + .get_regs = sky2_get_regs,
2922 + .get_link = ethtool_op_get_link,
2923 + .get_sg = ethtool_op_get_sg,
2924 + .set_sg = ethtool_op_set_sg,
2925 + .get_tx_csum = ethtool_op_get_tx_csum,
2926 + .set_tx_csum = ethtool_op_set_tx_csum,
2927 + .get_tso = ethtool_op_get_tso,
2928 + .set_tso = ethtool_op_set_tso,
2929 + .get_rx_csum = sky2_get_rx_csum,
2930 + .set_rx_csum = sky2_set_rx_csum,
2931 + .get_strings = sky2_get_strings,
2932 + .get_coalesce = sky2_get_coalesce,
2933 + .set_coalesce = sky2_set_coalesce,
2934 + .get_ringparam = sky2_get_ringparam,
2935 + .set_ringparam = sky2_set_ringparam,
2936 + .get_pauseparam = sky2_get_pauseparam,
2937 + .set_pauseparam = sky2_set_pauseparam,
2938 +#ifdef CONFIG_PM
2939 + .get_wol = sky2_get_wol,
2940 + .set_wol = sky2_set_wol,
2941 +#endif
2942 + .phys_id = sky2_phys_id,
2943 + .get_stats_count = sky2_get_stats_count,
2944 + .get_ethtool_stats = sky2_get_ethtool_stats,
2945 + .get_perm_addr = ethtool_op_get_perm_addr,
2946 +};
2947 +
2948 +/* Initialize network device */
2949 +static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2950 + unsigned port, int highmem)
2951 +{
2952 + struct sky2_port *sky2;
2953 + struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2954 +
2955 + if (!dev) {
2956 + printk(KERN_ERR "sky2 etherdev alloc failed");
2957 + return NULL;
2958 + }
2959 +
2960 + SET_MODULE_OWNER(dev);
2961 + SET_NETDEV_DEV(dev, &hw->pdev->dev);
2962 + dev->irq = hw->pdev->irq;
2963 + dev->open = sky2_up;
2964 + dev->stop = sky2_down;
2965 + dev->do_ioctl = sky2_ioctl;
2966 + dev->hard_start_xmit = sky2_xmit_frame;
2967 + dev->get_stats = sky2_get_stats;
2968 + dev->set_multicast_list = sky2_set_multicast;
2969 + dev->set_mac_address = sky2_set_mac_address;
2970 + dev->change_mtu = sky2_change_mtu;
2971 + SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
2972 + dev->tx_timeout = sky2_tx_timeout;
2973 + dev->watchdog_timeo = TX_WATCHDOG;
2974 + if (port == 0)
2975 + dev->poll = sky2_poll;
2976 + dev->weight = NAPI_WEIGHT;
2977 +#ifdef CONFIG_NET_POLL_CONTROLLER
2978 + dev->poll_controller = sky2_netpoll;
2979 +#endif
2980 +
2981 + sky2 = netdev_priv(dev);
2982 + sky2->netdev = dev;
2983 + sky2->hw = hw;
2984 + sky2->msg_enable = netif_msg_init(debug, default_msg);
2985 +
2986 + spin_lock_init(&sky2->tx_lock);
2987 + /* Auto speed and flow control */
2988 + sky2->autoneg = AUTONEG_ENABLE;
2989 + sky2->tx_pause = 1;
2990 + sky2->rx_pause = 1;
2991 + sky2->duplex = -1;
2992 + sky2->speed = -1;
2993 + sky2->advertising = sky2_supported_modes(hw);
2994 +
2995 + /* Receive checksum disabled for Yukon XL
2996 + * because of observed problems with incorrect
2997 + * values when multiple packets are received in one interrupt
2998 + */
2999 + sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
3000 +
3001 + INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2);
3002 + init_MUTEX(&sky2->phy_sema);
3003 + sky2->tx_pending = TX_DEF_PENDING;
3004 + sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
3005 + sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
3006 +
3007 + hw->dev[port] = dev;
3008 +
3009 + sky2->port = port;
3010 +
3011 + dev->features |= NETIF_F_LLTX;
3012 + if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3013 + dev->features |= NETIF_F_TSO;
3014 + if (highmem)
3015 + dev->features |= NETIF_F_HIGHDMA;
3016 + dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3017 +
3018 +#ifdef SKY2_VLAN_TAG_USED
3019 + dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3020 + dev->vlan_rx_register = sky2_vlan_rx_register;
3021 + dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3022 +#endif
3023 +
3024 + /* read the mac address */
3025 + memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3026 + memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3027 +
3028 + /* device is off until link detection */
3029 + netif_carrier_off(dev);
3030 + netif_stop_queue(dev);
3031 +
3032 + return dev;
3033 +}
3034 +
3035 +static inline void sky2_show_addr(struct net_device *dev)
3036 +{
3037 + const struct sky2_port *sky2 = netdev_priv(dev);
3038 +
3039 + if (netif_msg_probe(sky2))
3040 + printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3041 + dev->name,
3042 + dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3043 + dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3044 +}
3045 +
3046 +static int __devinit sky2_probe(struct pci_dev *pdev,
3047 + const struct pci_device_id *ent)
3048 +{
3049 + struct net_device *dev, *dev1 = NULL;
3050 + struct sky2_hw *hw;
3051 + int err, pm_cap, using_dac = 0;
3052 +
3053 + err = pci_enable_device(pdev);
3054 + if (err) {
3055 + printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3056 + pci_name(pdev));
3057 + goto err_out;
3058 + }
3059 +
3060 + err = pci_request_regions(pdev, DRV_NAME);
3061 + if (err) {
3062 + printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3063 + pci_name(pdev));
3064 + goto err_out;
3065 + }
3066 +
3067 + pci_set_master(pdev);
3068 +
3069 + /* Find power-management capability. */
3070 + pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3071 + if (pm_cap == 0) {
3072 + printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3073 + "aborting.\n");
3074 + err = -EIO;
3075 + goto err_out_free_regions;
3076 + }
3077 +
3078 + if (sizeof(dma_addr_t) > sizeof(u32)) {
3079 + err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
3080 + if (!err)
3081 + using_dac = 1;
3082 + }
3083 +
3084 + if (!using_dac) {
3085 + err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3086 + if (err) {
3087 + printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3088 + pci_name(pdev));
3089 + goto err_out_free_regions;
3090 + }
3091 + }
3092 +#ifdef __BIG_ENDIAN
3093 + /* byte swap descriptors in hardware */
3094 + {
3095 + u32 reg;
3096 +
3097 + pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3098 + reg |= PCI_REV_DESC;
3099 + pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3100 + }
3101 +#endif
3102 +
3103 + err = -ENOMEM;
3104 + hw = kmalloc(sizeof(*hw), GFP_KERNEL);
3105 + if (!hw) {
3106 + printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3107 + pci_name(pdev));
3108 + goto err_out_free_regions;
3109 + }
3110 +
3111 + memset(hw, 0, sizeof(*hw));
3112 + hw->pdev = pdev;
3113 +
3114 + hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3115 + if (!hw->regs) {
3116 + printk(KERN_ERR PFX "%s: cannot map device registers\n",
3117 + pci_name(pdev));
3118 + goto err_out_free_hw;
3119 + }
3120 + hw->pm_cap = pm_cap;
3121 +
3122 + err = sky2_reset(hw);
3123 + if (err)
3124 + goto err_out_iounmap;
3125 +
3126 + printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3127 + DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
3128 + yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3129 + hw->chip_id, hw->chip_rev);
3130 +
3131 + dev = sky2_init_netdev(hw, 0, using_dac);
3132 + if (!dev)
3133 + goto err_out_free_pci;
3134 +
3135 + err = register_netdev(dev);
3136 + if (err) {
3137 + printk(KERN_ERR PFX "%s: cannot register net device\n",
3138 + pci_name(pdev));
3139 + goto err_out_free_netdev;
3140 + }
3141 +
3142 + sky2_show_addr(dev);
3143 +
3144 + if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3145 + if (register_netdev(dev1) == 0)
3146 + sky2_show_addr(dev1);
3147 + else {
3148 + /* Failure to register second port need not be fatal */
3149 + printk(KERN_WARNING PFX
3150 + "register of second port failed\n");
3151 + hw->dev[1] = NULL;
3152 + free_netdev(dev1);
3153 + }
3154 + }
3155 +
3156 + err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
3157 + if (err) {
3158 + printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3159 + pci_name(pdev), pdev->irq);
3160 + goto err_out_unregister;
3161 + }
3162 +
3163 + hw->intr_mask = Y2_IS_BASE;
3164 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
3165 +
3166 + pci_set_drvdata(pdev, hw);
3167 +
3168 + return 0;
3169 +
3170 +err_out_unregister:
3171 + if (dev1) {
3172 + unregister_netdev(dev1);
3173 + free_netdev(dev1);
3174 + }
3175 + unregister_netdev(dev);
3176 +err_out_free_netdev:
3177 + free_netdev(dev);
3178 +err_out_free_pci:
3179 + sky2_write8(hw, B0_CTST, CS_RST_SET);
3180 + pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3181 +err_out_iounmap:
3182 + iounmap(hw->regs);
3183 +err_out_free_hw:
3184 + kfree(hw);
3185 +err_out_free_regions:
3186 + pci_release_regions(pdev);
3187 + pci_disable_device(pdev);
3188 +err_out:
3189 + return err;
3190 +}
3191 +
3192 +static void __devexit sky2_remove(struct pci_dev *pdev)
3193 +{
3194 + struct sky2_hw *hw = pci_get_drvdata(pdev);
3195 + struct net_device *dev0, *dev1;
3196 +
3197 + if (!hw)
3198 + return;
3199 +
3200 + dev0 = hw->dev[0];
3201 + dev1 = hw->dev[1];
3202 + if (dev1)
3203 + unregister_netdev(dev1);
3204 + unregister_netdev(dev0);
3205 +
3206 + sky2_write32(hw, B0_IMSK, 0);
3207 + sky2_set_power_state(hw, PCI_D3hot);
3208 + sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3209 + sky2_write8(hw, B0_CTST, CS_RST_SET);
3210 + sky2_read8(hw, B0_CTST);
3211 +
3212 + free_irq(pdev->irq, hw);
3213 + pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3214 + pci_release_regions(pdev);
3215 + pci_disable_device(pdev);
3216 +
3217 + if (dev1)
3218 + free_netdev(dev1);
3219 + free_netdev(dev0);
3220 + iounmap(hw->regs);
3221 + kfree(hw);
3222 +
3223 + pci_set_drvdata(pdev, NULL);
3224 +}
3225 +
3226 +#ifdef CONFIG_PM
3227 +static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3228 +{
3229 + struct sky2_hw *hw = pci_get_drvdata(pdev);
3230 + int i;
3231 +
3232 + for (i = 0; i < 2; i++) {
3233 + struct net_device *dev = hw->dev[i];
3234 +
3235 + if (dev) {
3236 + if (!netif_running(dev))
3237 + continue;
3238 +
3239 + sky2_down(dev);
3240 + netif_device_detach(dev);
3241 + }
3242 + }
3243 +
3244 + return sky2_set_power_state(hw, pci_choose_state(pdev, state));
3245 +}
3246 +
3247 +static int sky2_resume(struct pci_dev *pdev)
3248 +{
3249 + struct sky2_hw *hw = pci_get_drvdata(pdev);
3250 + int i;
3251 +
3252 + pci_restore_state(pdev);
3253 + pci_enable_wake(pdev, PCI_D0, 0);
3254 + sky2_set_power_state(hw, PCI_D0);
3255 +
3256 + sky2_reset(hw);
3257 +
3258 + for (i = 0; i < 2; i++) {
3259 + struct net_device *dev = hw->dev[i];
3260 + if (dev) {
3261 + if (netif_running(dev)) {
3262 + netif_device_attach(dev);
3263 + if (sky2_up(dev))
3264 + dev_close(dev);
3265 + }
3266 + }
3267 + }
3268 + return 0;
3269 +}
3270 +#endif
3271 +
3272 +static struct pci_driver sky2_driver = {
3273 + .name = DRV_NAME,
3274 + .id_table = sky2_id_table,
3275 + .probe = sky2_probe,
3276 + .remove = __devexit_p(sky2_remove),
3277 +#ifdef CONFIG_PM
3278 + .suspend = sky2_suspend,
3279 + .resume = sky2_resume,
3280 +#endif
3281 +};
3282 +
3283 +static int __init sky2_init_module(void)
3284 +{
3285 + return pci_register_driver(&sky2_driver);
3286 +}
3287 +
3288 +static void __exit sky2_cleanup_module(void)
3289 +{
3290 + pci_unregister_driver(&sky2_driver);
3291 +}
3292 +
3293 +module_init(sky2_init_module);
3294 +module_exit(sky2_cleanup_module);
3295 +
3296 +MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3297 +MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3298 +MODULE_LICENSE("GPL");
3299 +MODULE_VERSION(DRV_VERSION);
3300 --- linux-2.6.15/drivers/net/sky2.h 1970-01-01 01:00:00.000000000 +0100
3301 +++ linux-dsd/drivers/net/sky2.h 2006-01-03 18:10:52.000000000 +0000
3302 @@ -0,0 +1,1922 @@
3303 +/*
3304 + * Definitions for the new Marvell Yukon 2 driver.
3305 + */
3306 +#ifndef _SKY2_H
3307 +#define _SKY2_H
3308 +
3309 +/* PCI config registers */
3310 +#define PCI_DEV_REG1 0x40
3311 +#define PCI_DEV_REG2 0x44
3312 +#define PCI_DEV_STATUS 0x7c
3313 +#define PCI_OS_PCI_X (1<<26)
3314 +
3315 +#define PEX_LNK_STAT 0xf2
3316 +#define PEX_UNC_ERR_STAT 0x104
3317 +#define PEX_DEV_CTRL 0xe8
3318 +
3319 +/* Yukon-2 */
3320 +enum pci_dev_reg_1 {
3321 + PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
3322 + PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
3323 + PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
3324 + PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
3325 + PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
3326 + PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
3327 +};
3328 +
3329 +enum pci_dev_reg_2 {
3330 + PCI_VPD_WR_THR = 0xffL<<24, /* Bit 31..24: VPD Write Threshold */
3331 + PCI_DEV_SEL = 0x7fL<<17, /* Bit 23..17: EEPROM Device Select */
3332 + PCI_VPD_ROM_SZ = 7L<<14, /* Bit 16..14: VPD ROM Size */
3333 +
3334 + PCI_PATCH_DIR = 0xfL<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */
3335 + PCI_EXT_PATCHS = 0xfL<<4, /* Bit 7.. 4: Extended Patches 3..0 */
3336 + PCI_EN_DUMMY_RD = 1<<3, /* Enable Dummy Read */
3337 + PCI_REV_DESC = 1<<2, /* Reverse Desc. Bytes */
3338 +
3339 + PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */
3340 +};
3341 +
3342 +
3343 +#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
3344 + PCI_STATUS_SIG_SYSTEM_ERROR | \
3345 + PCI_STATUS_REC_MASTER_ABORT | \
3346 + PCI_STATUS_REC_TARGET_ABORT | \
3347 + PCI_STATUS_PARITY)
3348 +
3349 +enum pex_dev_ctrl {
3350 + PEX_DC_MAX_RRS_MSK = 7<<12, /* Bit 14..12: Max. Read Request Size */
3351 + PEX_DC_EN_NO_SNOOP = 1<<11,/* Enable No Snoop */
3352 + PEX_DC_EN_AUX_POW = 1<<10,/* Enable AUX Power */
3353 + PEX_DC_EN_PHANTOM = 1<<9, /* Enable Phantom Functions */
3354 + PEX_DC_EN_EXT_TAG = 1<<8, /* Enable Extended Tag Field */
3355 + PEX_DC_MAX_PLS_MSK = 7<<5, /* Bit 7.. 5: Max. Payload Size Mask */
3356 + PEX_DC_EN_REL_ORD = 1<<4, /* Enable Relaxed Ordering */
3357 + PEX_DC_EN_UNS_RQ_RP = 1<<3, /* Enable Unsupported Request Reporting */
3358 + PEX_DC_EN_FAT_ER_RP = 1<<2, /* Enable Fatal Error Reporting */
3359 + PEX_DC_EN_NFA_ER_RP = 1<<1, /* Enable Non-Fatal Error Reporting */
3360 + PEX_DC_EN_COR_ER_RP = 1<<0, /* Enable Correctable Error Reporting */
3361 +};
3362 +#define PEX_DC_MAX_RD_RQ_SIZE(x) (((x)<<12) & PEX_DC_MAX_RRS_MSK)
3363 +
3364 +/* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */
3365 +enum pex_err {
3366 + PEX_UNSUP_REQ = 1<<20, /* Unsupported Request Error */
3367 +
3368 + PEX_MALFOR_TLP = 1<<18, /* Malformed TLP */
3369 +
3370 + PEX_UNEXP_COMP = 1<<16, /* Unexpected Completion */
3371 +
3372 + PEX_COMP_TO = 1<<14, /* Completion Timeout */
3373 + PEX_FLOW_CTRL_P = 1<<13, /* Flow Control Protocol Error */
3374 + PEX_POIS_TLP = 1<<12, /* Poisoned TLP */
3375 +
3376 + PEX_DATA_LINK_P = 1<<4, /* Data Link Protocol Error */
3377 + PEX_FATAL_ERRORS= (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P),
3378 +};
3379 +
3380 +
3381 +enum csr_regs {
3382 + B0_RAP = 0x0000,
3383 + B0_CTST = 0x0004,
3384 + B0_Y2LED = 0x0005,
3385 + B0_POWER_CTRL = 0x0007,
3386 + B0_ISRC = 0x0008,
3387 + B0_IMSK = 0x000c,
3388 + B0_HWE_ISRC = 0x0010,
3389 + B0_HWE_IMSK = 0x0014,
3390 +
3391 + /* Special ISR registers (Yukon-2 only) */
3392 + B0_Y2_SP_ISRC2 = 0x001c,
3393 + B0_Y2_SP_ISRC3 = 0x0020,
3394 + B0_Y2_SP_EISR = 0x0024,
3395 + B0_Y2_SP_LISR = 0x0028,
3396 + B0_Y2_SP_ICR = 0x002c,
3397 +
3398 + B2_MAC_1 = 0x0100,
3399 + B2_MAC_2 = 0x0108,
3400 + B2_MAC_3 = 0x0110,
3401 + B2_CONN_TYP = 0x0118,
3402 + B2_PMD_TYP = 0x0119,
3403 + B2_MAC_CFG = 0x011a,
3404 + B2_CHIP_ID = 0x011b,
3405 + B2_E_0 = 0x011c,
3406 +
3407 + B2_Y2_CLK_GATE = 0x011d,
3408 + B2_Y2_HW_RES = 0x011e,
3409 + B2_E_3 = 0x011f,
3410 + B2_Y2_CLK_CTRL = 0x0120,
3411 +
3412 + B2_TI_INI = 0x0130,
3413 + B2_TI_VAL = 0x0134,
3414 + B2_TI_CTRL = 0x0138,
3415 + B2_TI_TEST = 0x0139,
3416 +
3417 + B2_TST_CTRL1 = 0x0158,
3418 + B2_TST_CTRL2 = 0x0159,
3419 + B2_GP_IO = 0x015c,
3420 +
3421 + B2_I2C_CTRL = 0x0160,
3422 + B2_I2C_DATA = 0x0164,
3423 + B2_I2C_IRQ = 0x0168,
3424 + B2_I2C_SW = 0x016c,
3425 +
3426 + B3_RAM_ADDR = 0x0180,
3427 + B3_RAM_DATA_LO = 0x0184,
3428 + B3_RAM_DATA_HI = 0x0188,
3429 +
3430 +/* RAM Interface Registers */
3431 +/* Yukon-2: use RAM_BUFFER() to access the RAM buffer */
3432 +/*
3433 + * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
3434 + * not usable in SW. Please notice these are NOT real timeouts, these are
3435 + * the number of qWords transferred continuously.
3436 + */
3437 +#define RAM_BUFFER(port, reg) (reg | (port <<6))
3438 +
3439 + B3_RI_WTO_R1 = 0x0190,
3440 + B3_RI_WTO_XA1 = 0x0191,
3441 + B3_RI_WTO_XS1 = 0x0192,
3442 + B3_RI_RTO_R1 = 0x0193,
3443 + B3_RI_RTO_XA1 = 0x0194,
3444 + B3_RI_RTO_XS1 = 0x0195,
3445 + B3_RI_WTO_R2 = 0x0196,
3446 + B3_RI_WTO_XA2 = 0x0197,
3447 + B3_RI_WTO_XS2 = 0x0198,
3448 + B3_RI_RTO_R2 = 0x0199,
3449 + B3_RI_RTO_XA2 = 0x019a,
3450 + B3_RI_RTO_XS2 = 0x019b,
3451 + B3_RI_TO_VAL = 0x019c,
3452 + B3_RI_CTRL = 0x01a0,
3453 + B3_RI_TEST = 0x01a2,
3454 + B3_MA_TOINI_RX1 = 0x01b0,
3455 + B3_MA_TOINI_RX2 = 0x01b1,
3456 + B3_MA_TOINI_TX1 = 0x01b2,
3457 + B3_MA_TOINI_TX2 = 0x01b3,
3458 + B3_MA_TOVAL_RX1 = 0x01b4,
3459 + B3_MA_TOVAL_RX2 = 0x01b5,
3460 + B3_MA_TOVAL_TX1 = 0x01b6,
3461 + B3_MA_TOVAL_TX2 = 0x01b7,
3462 + B3_MA_TO_CTRL = 0x01b8,
3463 + B3_MA_TO_TEST = 0x01ba,
3464 + B3_MA_RCINI_RX1 = 0x01c0,
3465 + B3_MA_RCINI_RX2 = 0x01c1,
3466 + B3_MA_RCINI_TX1 = 0x01c2,
3467 + B3_MA_RCINI_TX2 = 0x01c3,
3468 + B3_MA_RCVAL_RX1 = 0x01c4,
3469 + B3_MA_RCVAL_RX2 = 0x01c5,
3470 + B3_MA_RCVAL_TX1 = 0x01c6,
3471 + B3_MA_RCVAL_TX2 = 0x01c7,
3472 + B3_MA_RC_CTRL = 0x01c8,
3473 + B3_MA_RC_TEST = 0x01ca,
3474 + B3_PA_TOINI_RX1 = 0x01d0,
3475 + B3_PA_TOINI_RX2 = 0x01d4,
3476 + B3_PA_TOINI_TX1 = 0x01d8,
3477 + B3_PA_TOINI_TX2 = 0x01dc,
3478 + B3_PA_TOVAL_RX1 = 0x01e0,
3479 + B3_PA_TOVAL_RX2 = 0x01e4,
3480 + B3_PA_TOVAL_TX1 = 0x01e8,
3481 + B3_PA_TOVAL_TX2 = 0x01ec,
3482 + B3_PA_CTRL = 0x01f0,
3483 + B3_PA_TEST = 0x01f2,
3484 +
3485 + Y2_CFG_SPC = 0x1c00,
3486 +};
3487 +
3488 +/* B0_CTST 16 bit Control/Status register */
3489 +enum {
3490 + Y2_VMAIN_AVAIL = 1<<17,/* VMAIN available (YUKON-2 only) */
3491 + Y2_VAUX_AVAIL = 1<<16,/* VAUX available (YUKON-2 only) */
3492 + Y2_ASF_ENABLE = 1<<13,/* ASF Unit Enable (YUKON-2 only) */
3493 + Y2_ASF_DISABLE = 1<<12,/* ASF Unit Disable (YUKON-2 only) */
3494 + Y2_CLK_RUN_ENA = 1<<11,/* CLK_RUN Enable (YUKON-2 only) */
3495 + Y2_CLK_RUN_DIS = 1<<10,/* CLK_RUN Disable (YUKON-2 only) */
3496 + Y2_LED_STAT_ON = 1<<9, /* Status LED On (YUKON-2 only) */
3497 + Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */
3498 +
3499 + CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
3500 + CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
3501 + CS_STOP_DONE = 1<<5, /* Stop Master is finished */
3502 + CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
3503 + CS_MRST_CLR = 1<<3, /* Clear Master reset */
3504 + CS_MRST_SET = 1<<2, /* Set Master reset */
3505 + CS_RST_CLR = 1<<1, /* Clear Software reset */
3506 + CS_RST_SET = 1, /* Set Software reset */
3507 +};
3508 +
3509 +/* B0_LED 8 Bit LED register */
3510 +enum {
3511 +/* Bit 7.. 2: reserved */
3512 + LED_STAT_ON = 1<<1, /* Status LED on */
3513 + LED_STAT_OFF = 1, /* Status LED off */
3514 +};
3515 +
3516 +/* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
3517 +enum {
3518 + PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
3519 + PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
3520 + PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
3521 + PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
3522 + PC_VAUX_ON = 1<<3, /* Switch VAUX On */
3523 + PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
3524 + PC_VCC_ON = 1<<1, /* Switch VCC On */
3525 + PC_VCC_OFF = 1<<0, /* Switch VCC Off */
3526 +};
3527 +
3528 +/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
3529 +
3530 +/* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */
3531 +/* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */
3532 +/* B0_Y2_SP_EISR 32 bit Enter ISR Reg */
3533 +/* B0_Y2_SP_LISR 32 bit Leave ISR Reg */
3534 +enum {
3535 + Y2_IS_HW_ERR = 1<<31, /* Interrupt HW Error */
3536 + Y2_IS_STAT_BMU = 1<<30, /* Status BMU Interrupt */
3537 + Y2_IS_ASF = 1<<29, /* ASF subsystem Interrupt */
3538 +
3539 + Y2_IS_POLL_CHK = 1<<27, /* Check IRQ from polling unit */
3540 + Y2_IS_TWSI_RDY = 1<<26, /* IRQ on end of TWSI Tx */
3541 + Y2_IS_IRQ_SW = 1<<25, /* SW forced IRQ */
3542 + Y2_IS_TIMINT = 1<<24, /* IRQ from Timer */
3543 +
3544 + Y2_IS_IRQ_PHY2 = 1<<12, /* Interrupt from PHY 2 */
3545 + Y2_IS_IRQ_MAC2 = 1<<11, /* Interrupt from MAC 2 */
3546 + Y2_IS_CHK_RX2 = 1<<10, /* Descriptor error Rx 2 */
3547 + Y2_IS_CHK_TXS2 = 1<<9, /* Descriptor error TXS 2 */
3548 + Y2_IS_CHK_TXA2 = 1<<8, /* Descriptor error TXA 2 */
3549 +
3550 + Y2_IS_IRQ_PHY1 = 1<<4, /* Interrupt from PHY 1 */
3551 + Y2_IS_IRQ_MAC1 = 1<<3, /* Interrupt from MAC 1 */
3552 + Y2_IS_CHK_RX1 = 1<<2, /* Descriptor error Rx 1 */
3553 + Y2_IS_CHK_TXS1 = 1<<1, /* Descriptor error TXS 1 */
3554 + Y2_IS_CHK_TXA1 = 1<<0, /* Descriptor error TXA 1 */
3555 +
3556 + Y2_IS_BASE = Y2_IS_HW_ERR | Y2_IS_STAT_BMU |
3557 + Y2_IS_POLL_CHK | Y2_IS_TWSI_RDY |
3558 + Y2_IS_IRQ_SW | Y2_IS_TIMINT,
3559 + Y2_IS_PORT_1 = Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1 |
3560 + Y2_IS_CHK_RX1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXS1,
3561 + Y2_IS_PORT_2 = Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 |
3562 + Y2_IS_CHK_RX2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_TXS2,
3563 +};
3564 +
3565 +/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
3566 +enum {
3567 + IS_ERR_MSK = 0x00003fff,/* All Error bits */
3568 +
3569 + IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
3570 + IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
3571 + IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
3572 + IS_IRQ_STAT = 1<<10, /* IRQ status exception */
3573 + IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
3574 + IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
3575 + IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
3576 + IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
3577 + IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
3578 + IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
3579 + IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
3580 + IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
3581 + IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
3582 + IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
3583 +};
3584 +
3585 +/* Hardware error interrupt mask for Yukon 2 */
3586 +enum {
3587 + Y2_IS_TIST_OV = 1<<29,/* Time Stamp Timer overflow interrupt */
3588 + Y2_IS_SENSOR = 1<<28, /* Sensor interrupt */
3589 + Y2_IS_MST_ERR = 1<<27, /* Master error interrupt */
3590 + Y2_IS_IRQ_STAT = 1<<26, /* Status exception interrupt */
3591 + Y2_IS_PCI_EXP = 1<<25, /* PCI-Express interrupt */
3592 + Y2_IS_PCI_NEXP = 1<<24, /* PCI-Express error similar to PCI error */
3593 + /* Link 2 */
3594 + Y2_IS_PAR_RD2 = 1<<13, /* Read RAM parity error interrupt */
3595 + Y2_IS_PAR_WR2 = 1<<12, /* Write RAM parity error interrupt */
3596 + Y2_IS_PAR_MAC2 = 1<<11, /* MAC hardware fault interrupt */
3597 + Y2_IS_PAR_RX2 = 1<<10, /* Parity Error Rx Queue 2 */
3598 + Y2_IS_TCP_TXS2 = 1<<9, /* TCP length mismatch sync Tx queue IRQ */
3599 + Y2_IS_TCP_TXA2 = 1<<8, /* TCP length mismatch async Tx queue IRQ */
3600 + /* Link 1 */
3601 + Y2_IS_PAR_RD1 = 1<<5, /* Read RAM parity error interrupt */
3602 + Y2_IS_PAR_WR1 = 1<<4, /* Write RAM parity error interrupt */
3603 + Y2_IS_PAR_MAC1 = 1<<3, /* MAC hardware fault interrupt */
3604 + Y2_IS_PAR_RX1 = 1<<2, /* Parity Error Rx Queue 1 */
3605 + Y2_IS_TCP_TXS1 = 1<<1, /* TCP length mismatch sync Tx queue IRQ */
3606 + Y2_IS_TCP_TXA1 = 1<<0, /* TCP length mismatch async Tx queue IRQ */
3607 +
3608 + Y2_HWE_L1_MASK = Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |
3609 + Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1,
3610 + Y2_HWE_L2_MASK = Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |
3611 + Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2,
3612 +
3613 + Y2_HWE_ALL_MASK = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT |
3614 + Y2_IS_PCI_EXP |
3615 + Y2_HWE_L1_MASK | Y2_HWE_L2_MASK,
3616 +};
3617 +
3618 +/* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
3619 +enum {
3620 + DPT_START = 1<<1,
3621 + DPT_STOP = 1<<0,
3622 +};
3623 +
3624 +/* B2_TST_CTRL1 8 bit Test Control Register 1 */
3625 +enum {
3626 + TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
3627 + TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
3628 + TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
3629 + TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
3630 + TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
3631 + TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
3632 + TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
3633 + TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
3634 +};
3635 +
3636 +/* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
3637 +enum {
3638 + CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
3639 + /* Bit 3.. 2: reserved */
3640 + CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
3641 + CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
3642 +};
3643 +
3644 +/* B2_CHIP_ID 8 bit Chip Identification Number */
3645 +enum {
3646 + CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */
3647 + CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */
3648 + CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
3649 + CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
3650 + CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
3651 + CHIP_ID_YUKON_EC_U = 0xb4, /* Chip ID for YUKON-2 EC Ultra */
3652 + CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
3653 + CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
3654 +
3655 + CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */
3656 + CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */
3657 + CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */
3658 +};
3659 +
3660 +/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
3661 +enum {
3662 + Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactive (0 = active) */
3663 + Y2_CLK_GAT_LNK2_DIS = 1<<6, /* Disable clock gating Link 2 */
3664 + Y2_COR_CLK_LNK2_DIS = 1<<5, /* Disable Core clock Link 2 */
3665 + Y2_PCI_CLK_LNK2_DIS = 1<<4, /* Disable PCI clock Link 2 */
3666 + Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactive (0 = active) */
3667 + Y2_CLK_GAT_LNK1_DIS = 1<<2, /* Disable clock gating Link 1 */
3668 + Y2_COR_CLK_LNK1_DIS = 1<<1, /* Disable Core clock Link 1 */
3669 + Y2_PCI_CLK_LNK1_DIS = 1<<0, /* Disable PCI clock Link 1 */
3670 +};
3671 +
3672 +/* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
3673 +enum {
3674 + CFG_LED_MODE_MSK = 7<<2, /* Bit 4.. 2: LED Mode Mask */
3675 + CFG_LINK_2_AVAIL = 1<<1, /* Link 2 available */
3676 + CFG_LINK_1_AVAIL = 1<<0, /* Link 1 available */
3677 +};
3678 +#define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2)
3679 +#define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)
3680 +
3681 +
3682 +/* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */
3683 +enum {
3684 + Y2_CLK_DIV_VAL_MSK = 0xff<<16,/* Bit 23..16: Clock Divisor Value */
3685 +#define Y2_CLK_DIV_VAL(x) (((x)<<16) & Y2_CLK_DIV_VAL_MSK)
3686 + Y2_CLK_DIV_VAL2_MSK = 7<<21, /* Bit 23..21: Clock Divisor Value */
3687 + Y2_CLK_SELECT2_MSK = 0x1f<<16,/* Bit 20..16: Clock Select */
3688 +#define Y2_CLK_DIV_VAL_2(x) (((x)<<21) & Y2_CLK_DIV_VAL2_MSK)
3689 +#define Y2_CLK_SEL_VAL_2(x) (((x)<<16) & Y2_CLK_SELECT2_MSK)
3690 + Y2_CLK_DIV_ENA = 1<<1, /* Enable Core Clock Division */
3691 + Y2_CLK_DIV_DIS = 1<<0, /* Disable Core Clock Division */
3692 +};
3693 +
3694 +/* B2_TI_CTRL 8 bit Timer control */
3695 +/* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
3696 +enum {
3697 + TIM_START = 1<<2, /* Start Timer */
3698 + TIM_STOP = 1<<1, /* Stop Timer */
3699 + TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
3700 +};
3701 +
3702 +/* B2_TI_TEST 8 Bit Timer Test */
3703 +/* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
3704 +/* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
3705 +enum {
3706 + TIM_T_ON = 1<<2, /* Test mode on */
3707 + TIM_T_OFF = 1<<1, /* Test mode off */
3708 + TIM_T_STEP = 1<<0, /* Test step */
3709 +};
3710 +
3711 +/* B3_RAM_ADDR 32 bit RAM Address, to read or write */
3712 + /* Bit 31..19: reserved */
3713 +#define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
3714 +/* RAM Interface Registers */
3715 +
3716 +/* B3_RI_CTRL 16 bit RAM Interface Control Register */
3717 +enum {
3718 + RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
3719 + RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
3720 +
3721 + RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
3722 + RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
3723 +};
3724 +
3725 +#define SK_RI_TO_53 36 /* RAM interface timeout */
3726 +
3727 +
3728 +/* Port related registers FIFO, and Arbiter */
3729 +#define SK_REG(port,reg) (((port)<<7)+(reg))
3730 +
3731 +/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
3732 +/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
3733 +/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
3734 +/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
3735 +/* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
3736 +
3737 +#define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
3738 +
3739 +/* TXA_CTRL 8 bit Tx Arbiter Control Register */
3740 +enum {
3741 + TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
3742 + TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
3743 + TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
3744 + TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
3745 + TXA_START_RC = 1<<3, /* Start sync Rate Control */
3746 + TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
3747 + TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
3748 + TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
3749 +};
3750 +
3751 +/*
3752 + * Bank 4 - 5
3753 + */
3754 +/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
3755 +enum {
3756 + TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
3757 + TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
3758 + TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
3759 + TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
3760 + TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
3761 + TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
3762 + TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
3763 +};
3764 +
3765 +
3766 +enum {
3767 + B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
3768 + B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
3769 + B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
3770 + B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
3771 + B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
3772 + B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
3773 + B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
3774 + B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
3775 + B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
3776 +};
3777 +
3778 +/* Queue Register Offsets, use Q_ADDR() to access */
3779 +enum {
3780 + B8_Q_REGS = 0x0400, /* base of Queue registers */
3781 + Q_D = 0x00, /* 8*32 bit Current Descriptor */
3782 + Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */
3783 + Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */
3784 + Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
3785 + Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
3786 + Q_BC = 0x30, /* 32 bit Current Byte Counter */
3787 + Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
3788 + Q_F = 0x38, /* 32 bit Flag Register */
3789 + Q_T1 = 0x3c, /* 32 bit Test Register 1 */
3790 + Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */
3791 + Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */
3792 + Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */
3793 + Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */
3794 + Q_T2 = 0x40, /* 32 bit Test Register 2 */
3795 + Q_T3 = 0x44, /* 32 bit Test Register 3 */
3796 +
3797 +/* Yukon-2 */
3798 + Q_DONE = 0x24, /* 16 bit Done Index (Yukon-2 only) */
3799 + Q_WM = 0x40, /* 16 bit FIFO Watermark */
3800 + Q_AL = 0x42, /* 8 bit FIFO Alignment */
3801 + Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */
3802 + Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */
3803 + Q_RP = 0x48, /* 8 bit FIFO Read Pointer */
3804 + Q_RL = 0x4a, /* 8 bit FIFO Read Level */
3805 + Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */
3806 + Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */
3807 + Q_WL = 0x4e, /* 8 bit FIFO Write Level */
3808 + Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */
3809 +};
3810 +#define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
3811 +
3812 +
3813 +/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
3814 +enum {
3815 + Y2_B8_PREF_REGS = 0x0450,
3816 +
3817 + PREF_UNIT_CTRL = 0x00, /* 32 bit Control register */
3818 + PREF_UNIT_LAST_IDX = 0x04, /* 16 bit Last Index */
3819 + PREF_UNIT_ADDR_LO = 0x08, /* 32 bit List start addr, low part */
3820 + PREF_UNIT_ADDR_HI = 0x0c, /* 32 bit List start addr, high part*/
3821 + PREF_UNIT_GET_IDX = 0x10, /* 16 bit Get Index */
3822 + PREF_UNIT_PUT_IDX = 0x14, /* 16 bit Put Index */
3823 + PREF_UNIT_FIFO_WP = 0x20, /* 8 bit FIFO write pointer */
3824 + PREF_UNIT_FIFO_RP = 0x24, /* 8 bit FIFO read pointer */
3825 + PREF_UNIT_FIFO_WM = 0x28, /* 8 bit FIFO watermark */
3826 + PREF_UNIT_FIFO_LEV = 0x2c, /* 8 bit FIFO level */
3827 +
3828 + PREF_UNIT_MASK_IDX = 0x0fff,
3829 +};
3830 +#define Y2_QADDR(q,reg) (Y2_B8_PREF_REGS + (q) + (reg))
3831 +
3832 +/* RAM Buffer Register Offsets */
3833 +enum {
3834 +
3835 + RB_START = 0x00,/* 32 bit RAM Buffer Start Address */
3836 + RB_END = 0x04,/* 32 bit RAM Buffer End Address */
3837 + RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
3838 + RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
3839 + RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
3840 + RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
3841 + RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */
3842 + RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
3843 + /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
3844 + RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
3845 + RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
3846 + RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
3847 + RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
3848 + RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
3849 +};
3850 +
3851 +/* Receive and Transmit Queues */
3852 +enum {
3853 + Q_R1 = 0x0000, /* Receive Queue 1 */
3854 + Q_R2 = 0x0080, /* Receive Queue 2 */
3855 + Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
3856 + Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
3857 + Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
3858 + Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
3859 +};
3860 +
3861 +/* Different PHY Types */
3862 +enum {
3863 + PHY_ADDR_MARV = 0,
3864 +};
3865 +
3866 +#define RB_ADDR(offs, queue) (B16_RAM_REGS + (queue) + (offs))
3867 +
3868 +
3869 +enum {
3870 + LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
3871 + LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
3872 + LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
3873 + LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
3874 +
3875 + LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
3876 +
3877 +/* Receive GMAC FIFO (YUKON and Yukon-2) */
3878 +
3879 + RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
3880 + RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
3881 + RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
3882 + RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
3883 + RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
3884 + RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
3885 + RX_GMF_UP_THR = 0x0c58,/* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */
3886 + RX_GMF_LP_THR = 0x0c5a,/* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */
3887 + RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
3888 + RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
3889 +
3890 + RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
3891 +
3892 + RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
3893 +
3894 + RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
3895 +};
3896 +
3897 +
3898 +/* Q_BC 32 bit Current Byte Counter */
3899 +
3900 +/* BMU Control Status Registers */
3901 +/* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
3902 +/* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
3903 +/* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
3904 +/* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
3905 +/* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
3906 +/* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
3907 +/* Q_CSR 32 bit BMU Control/Status Register */
3908 +
3909 +/* Rx BMU Control / Status Registers (Yukon-2) */
3910 +enum {
3911 + BMU_IDLE = 1<<31, /* BMU Idle State */
3912 + BMU_RX_TCP_PKT = 1<<30, /* Rx TCP Packet (when RSS Hash enabled) */
3913 + BMU_RX_IP_PKT = 1<<29, /* Rx IP Packet (when RSS Hash enabled) */
3914 +
3915 + BMU_ENA_RX_RSS_HASH = 1<<15, /* Enable Rx RSS Hash */
3916 + BMU_DIS_RX_RSS_HASH = 1<<14, /* Disable Rx RSS Hash */
3917 + BMU_ENA_RX_CHKSUM = 1<<13, /* Enable Rx TCP/IP Checksum Check */
3918 + BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */
3919 + BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */
3920 + BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment. error (Tx) */
3921 + BMU_CLR_IRQ_CHK = 1<<10, /* Clear IRQ Check */
3922 + BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */
3923 + BMU_START = 1<<8, /* Start Rx/Tx Queue */
3924 + BMU_FIFO_OP_ON = 1<<7, /* FIFO Operational On */
3925 + BMU_FIFO_OP_OFF = 1<<6, /* FIFO Operational Off */
3926 + BMU_FIFO_ENA = 1<<5, /* Enable FIFO */
3927 + BMU_FIFO_RST = 1<<4, /* Reset FIFO */
3928 + BMU_OP_ON = 1<<3, /* BMU Operational On */
3929 + BMU_OP_OFF = 1<<2, /* BMU Operational Off */
3930 + BMU_RST_CLR = 1<<1, /* Clear BMU Reset (Enable) */
3931 + BMU_RST_SET = 1<<0, /* Set BMU Reset */
3932 +
3933 + BMU_CLR_RESET = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR,
3934 + BMU_OPER_INIT = BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START |
3935 + BMU_FIFO_ENA | BMU_OP_ON,
3936 +
3937 + BMU_WM_DEFAULT = 0x600,
3938 +};
3939 +
3940 +/* Tx BMU Control / Status Registers (Yukon-2) */
3941 + /* Bit 31: same as for Rx */
3942 +enum {
3943 + BMU_TX_IPIDINCR_ON = 1<<13, /* Enable IP ID Increment */
3944 + BMU_TX_IPIDINCR_OFF = 1<<12, /* Disable IP ID Increment */
3945 + BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment length mismatch */
3946 +};
3947 +
3948 +/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
3949 +/* PREF_UNIT_CTRL 32 bit Prefetch Control register */
3950 +enum {
3951 + PREF_UNIT_OP_ON = 1<<3, /* prefetch unit operational */
3952 + PREF_UNIT_OP_OFF = 1<<2, /* prefetch unit not operational */
3953 + PREF_UNIT_RST_CLR = 1<<1, /* Clear Prefetch Unit Reset */
3954 + PREF_UNIT_RST_SET = 1<<0, /* Set Prefetch Unit Reset */
3955 +};
3956 +
3957 +/* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
3958 +/* RB_START 32 bit RAM Buffer Start Address */
3959 +/* RB_END 32 bit RAM Buffer End Address */
3960 +/* RB_WP 32 bit RAM Buffer Write Pointer */
3961 +/* RB_RP 32 bit RAM Buffer Read Pointer */
3962 +/* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
3963 +/* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
3964 +/* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
3965 +/* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
3966 +/* RB_PC 32 bit RAM Buffer Packet Counter */
3967 +/* RB_LEV 32 bit RAM Buffer Level Register */
3968 +
3969 +#define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
3970 +/* RB_TST2 8 bit RAM Buffer Test Register 2 */
3971 +/* RB_TST1 8 bit RAM Buffer Test Register 1 */
3972 +
3973 +/* RB_CTRL 8 bit RAM Buffer Control Register */
3974 +enum {
3975 + RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
3976 + RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
3977 + RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
3978 + RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
3979 + RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
3980 + RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
3981 +};
3982 +
3983 +
3984 +/* Transmit GMAC FIFO (YUKON only) */
3985 +enum {
3986 + TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
3987 + TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
3988 + TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
3989 +
3990 + TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
3991 + TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
3992 + TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
3993 +
3994 + TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
3995 + TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
3996 + TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
3997 +};
3998 +
3999 +/* Descriptor Poll Timer Registers */
4000 +enum {
4001 + B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
4002 + B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
4003 + B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
4004 +
4005 + B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
4006 +};
4007 +
4008 +/* Time Stamp Timer Registers (YUKON only) */
4009 +enum {
4010 + GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
4011 + GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
4012 + GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
4013 +};
4014 +
4015 +/* Polling Unit Registers (Yukon-2 only) */
4016 +enum {
4017 + POLL_CTRL = 0x0e20, /* 32 bit Polling Unit Control Reg */
4018 + POLL_LAST_IDX = 0x0e24,/* 16 bit Polling Unit List Last Index */
4019 +
4020 + POLL_LIST_ADDR_LO= 0x0e28,/* 32 bit Poll. List Start Addr (low) */
4021 + POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */
4022 +};
4023 +
4024 +/* ASF Subsystem Registers (Yukon-2 only) */
4025 +enum {
4026 + B28_Y2_SMB_CONFIG = 0x0e40,/* 32 bit ASF SMBus Config Register */
4027 + B28_Y2_SMB_CSD_REG = 0x0e44,/* 32 bit ASF SMB Control/Status/Data */
4028 + B28_Y2_ASF_IRQ_V_BASE=0x0e60,/* 32 bit ASF IRQ Vector Base */
4029 +
4030 + B28_Y2_ASF_STAT_CMD= 0x0e68,/* 32 bit ASF Status and Command Reg */
4031 + B28_Y2_ASF_HOST_COM= 0x0e6c,/* 32 bit ASF Host Communication Reg */
4032 + B28_Y2_DATA_REG_1 = 0x0e70,/* 32 bit ASF/Host Data Register 1 */
4033 + B28_Y2_DATA_REG_2 = 0x0e74,/* 32 bit ASF/Host Data Register 2 */
4034 + B28_Y2_DATA_REG_3 = 0x0e78,/* 32 bit ASF/Host Data Register 3 */
4035 + B28_Y2_DATA_REG_4 = 0x0e7c,/* 32 bit ASF/Host Data Register 4 */
4036 +};
4037 +
4038 +/* Status BMU Registers (Yukon-2 only)*/
4039 +enum {
4040 + STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */
4041 + STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */
4042 +
4043 + STAT_LIST_ADDR_LO= 0x0e88,/* 32 bit Status List Start Addr (low) */
4044 + STAT_LIST_ADDR_HI= 0x0e8c,/* 32 bit Status List Start Addr (high) */
4045 + STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */
4046 + STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */
4047 + STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */
4048 + STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */
4049 + STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */
4050 + STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */
4051 +
4052 +/* FIFO Control/Status Registers (Yukon-2 only)*/
4053 + STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */
4054 + STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */
4055 + STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */
4056 + STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */
4057 + STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */
4058 + STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */
4059 + STAT_FIFO_ISR_WM= 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */
4060 +
4061 +/* Level and ISR Timer Registers (Yukon-2 only)*/
4062 + STAT_LEV_TIMER_INI= 0x0eb0,/* 32 bit Level Timer Init. Value Reg */
4063 + STAT_LEV_TIMER_CNT= 0x0eb4,/* 32 bit Level Timer Counter Reg */
4064 + STAT_LEV_TIMER_CTRL= 0x0eb8,/* 8 bit Level Timer Control Reg */
4065 + STAT_LEV_TIMER_TEST= 0x0eb9,/* 8 bit Level Timer Test Reg */
4066 + STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */
4067 + STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */
4068 + STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */
4069 + STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */
4070 + STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */
4071 + STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */
4072 + STAT_ISR_TIMER_CTRL= 0x0ed8,/* 8 bit ISR Timer Control Reg */
4073 + STAT_ISR_TIMER_TEST= 0x0ed9,/* 8 bit ISR Timer Test Reg */
4074 +};
4075 +
4076 +enum {
4077 + LINKLED_OFF = 0x01,
4078 + LINKLED_ON = 0x02,
4079 + LINKLED_LINKSYNC_OFF = 0x04,
4080 + LINKLED_LINKSYNC_ON = 0x08,
4081 + LINKLED_BLINK_OFF = 0x10,
4082 + LINKLED_BLINK_ON = 0x20,
4083 +};
4084 +
4085 +/* GMAC and GPHY Control Registers (YUKON only) */
4086 +enum {
4087 + GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
4088 + GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
4089 + GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
4090 + GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
4091 + GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
4092 +
4093 +/* Wake-up Frame Pattern Match Control Registers (YUKON only) */
4094 +
4095 + WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
4096 +
4097 + WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
4098 + WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
4099 + WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
4100 + WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
4101 + WOL_PATT_PME = 0x0f2a,/* 8 bit WOL PME Match Enable (Yukon-2) */
4102 + WOL_PATT_ASFM = 0x0f2b,/* 8 bit WOL ASF Match Enable (Yukon-2) */
4103 + WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
4104 +
4105 +/* WOL Pattern Length Registers (YUKON only) */
4106 +
4107 + WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
4108 + WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
4109 +
4110 +/* WOL Pattern Counter Registers (YUKON only) */
4111 +
4112 +
4113 + WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
4114 + WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
4115 +};
4116 +
4117 +enum {
4118 + WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
4119 + WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
4120 +};
4121 +
4122 +enum {
4123 + BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
4124 + BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
4125 +};
4126 +
4127 +/*
4128 + * Marvel-PHY Registers, indirect addressed over GMAC
4129 + */
4130 +enum {
4131 + PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
4132 + PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
4133 + PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
4134 + PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
4135 + PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
4136 + PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
4137 + PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
4138 + PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
4139 + PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
4140 + /* Marvel-specific registers */
4141 + PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
4142 + PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
4143 + PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
4144 + PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
4145 + PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
4146 + PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
4147 + PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
4148 + PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
4149 + PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
4150 + PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
4151 + PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
4152 + PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
4153 + PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
4154 + PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
4155 + PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
4156 + PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
4157 + PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
4158 + PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
4159 +
4160 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
4161 + PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
4162 + PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
4163 + PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
4164 + PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
4165 + PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
4166 +};
4167 +
4168 +enum {
4169 + PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
4170 + PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
4171 + PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
4172 + PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
4173 + PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
4174 + PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
4175 + PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
4176 + PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
4177 + PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
4178 + PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
4179 +};
4180 +
4181 +enum {
4182 + PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
4183 + PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
4184 + PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
4185 +};
4186 +
4187 +enum {
4188 + PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
4189 +
4190 + PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
4191 + PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
4192 + PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */
4193 + PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
4194 + PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
4195 + PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
4196 + PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
4197 +};
4198 +
4199 +enum {
4200 + PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
4201 + PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
4202 + PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
4203 +};
4204 +
4205 +/* different Marvell PHY Ids */
4206 +enum {
4207 + PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
4208 +
4209 + PHY_BCOM_ID1_A1 = 0x6041,
4210 + PHY_BCOM_ID1_B2 = 0x6043,
4211 + PHY_BCOM_ID1_C0 = 0x6044,
4212 + PHY_BCOM_ID1_C5 = 0x6047,
4213 +
4214 + PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
4215 + PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
4216 + PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
4217 + PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
4218 +};
4219 +
4220 +/* Advertisement register bits */
4221 +enum {
4222 + PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
4223 + PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
4224 + PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */
4225 +
4226 + PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
4227 + PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */
4228 + PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */
4229 + PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
4230 + PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
4231 + PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
4232 + PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
4233 + PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
4234 + PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
4235 + PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
4236 + PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL |
4237 + PHY_AN_100HALF | PHY_AN_100FULL,
4238 +};
4239 +
4240 +/***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
4241 +/***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
4242 +enum {
4243 + PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
4244 + PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
4245 + PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
4246 + PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
4247 + PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
4248 + PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
4249 + /* Bit 9..8: reserved */
4250 + PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
4251 +};
4252 +
4253 +/** Marvell-Specific */
4254 +enum {
4255 + PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
4256 + PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */
4257 + PHY_M_AN_RF = 1<<13, /* Remote Fault */
4258 +
4259 + PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */
4260 + PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */
4261 + PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
4262 + PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
4263 + PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
4264 + PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
4265 + PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
4266 + PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
4267 +};
4268 +
4269 +/* special defines for FIBER (88E1011S only) */
4270 +enum {
4271 + PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
4272 + PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
4273 + PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
4274 + PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
4275 +};
4276 +
4277 +/* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
4278 +enum {
4279 + PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
4280 + PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
4281 + PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
4282 + PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
4283 +};
4284 +
4285 +/***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
4286 +enum {
4287 + PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
4288 + PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
4289 + PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
4290 + PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
4291 + PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
4292 + PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
4293 +};
4294 +
4295 +/***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
4296 +enum {
4297 + PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
4298 + PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
4299 + PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
4300 + PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */
4301 + PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
4302 + PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */
4303 + PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
4304 + PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */
4305 + PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */
4306 + PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */
4307 + PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */
4308 + PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */
4309 +};
4310 +
4311 +enum {
4312 + PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */
4313 + PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
4314 +};
4315 +
4316 +#define PHY_M_PC_MDI_XMODE(x) (((x)<<5) & PHY_M_PC_MDIX_MSK)
4317 +
4318 +enum {
4319 + PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
4320 + PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */
4321 + PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
4322 +};
4323 +
4324 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
4325 +enum {
4326 + PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
4327 + PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */
4328 + PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */
4329 + PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */
4330 + PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
4331 +
4332 + PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */
4333 + PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
4334 +
4335 + PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */
4336 + PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
4337 +};
4338 +
4339 +/***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
4340 +enum {
4341 + PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
4342 + PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */
4343 + PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */
4344 + PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */
4345 + PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */
4346 + PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */
4347 + PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */
4348 + PHY_M_PS_LINK_UP = 1<<10, /* Link Up */
4349 + PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
4350 + PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */
4351 + PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */
4352 + PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */
4353 + PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */
4354 + PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */
4355 + PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */
4356 + PHY_M_PS_JABBER = 1<<0, /* Jabber */
4357 +};
4358 +
4359 +#define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
4360 +
4361 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
4362 +enum {
4363 + PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */
4364 + PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
4365 +};
4366 +
4367 +enum {
4368 + PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
4369 + PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */
4370 + PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */
4371 + PHY_M_IS_AN_PR = 1<<12, /* Page Received */
4372 + PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
4373 + PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */
4374 + PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */
4375 + PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */
4376 + PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */
4377 + PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */
4378 + PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */
4379 + PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */
4380 +
4381 + PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */
4382 + PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */
4383 + PHY_M_IS_JABBER = 1<<0, /* Jabber */
4384 +
4385 + PHY_M_DEF_MSK = PHY_M_IS_LSP_CHANGE | PHY_M_IS_LST_CHANGE
4386 + | PHY_M_IS_FIFO_ERROR,
4387 + PHY_M_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
4388 +};
4389 +
4390 +
4391 +/***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
4392 +enum {
4393 + PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
4394 + PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
4395 +
4396 + PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
4397 + PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
4398 + /* (88E1011 only) */
4399 + PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */
4400 + /* (88E1011 only) */
4401 + PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */
4402 + /* (88E1111 only) */
4403 + PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
4404 + /* !!! Errata in spec. (1 = disable) */
4405 + PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
4406 + PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */
4407 + PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
4408 + PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
4409 + PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
4410 + PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};
4411 +
4412 +#define PHY_M_EC_M_DSC(x) ((x)<<10 & PHY_M_EC_M_DSC_MSK)
4413 + /* 00=1x; 01=2x; 10=3x; 11=4x */
4414 +#define PHY_M_EC_S_DSC(x) ((x)<<8 & PHY_M_EC_S_DSC_MSK)
4415 + /* 00=dis; 01=1x; 10=2x; 11=3x */
4416 +#define PHY_M_EC_DSC_2(x) ((x)<<9 & PHY_M_EC_M_DSC_MSK2)
4417 + /* 000=1x; 001=2x; 010=3x; 011=4x */
4418 +#define PHY_M_EC_MAC_S(x) ((x)<<4 & PHY_M_EC_MAC_S_MSK)
4419 + /* 01X=0; 110=2.5; 111=25 (MHz) */
4420 +
4421 +/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
4422 +enum {
4423 + PHY_M_PC_DIS_LINK_Pa = 1<<15,/* Disable Link Pulses */
4424 + PHY_M_PC_DSC_MSK = 7<<12,/* Bit 14..12: Downshift Counter */
4425 + PHY_M_PC_DOWN_S_ENA = 1<<11,/* Downshift Enable */
4426 +};
4427 +/* !!! Errata in spec. (1 = disable) */
4428 +
4429 +#define PHY_M_PC_DSC(x) (((x)<<12) & PHY_M_PC_DSC_MSK)
4430 + /* 100=5x; 101=6x; 110=7x; 111=8x */
4431 +enum {
4432 + MAC_TX_CLK_0_MHZ = 2,
4433 + MAC_TX_CLK_2_5_MHZ = 6,
4434 + MAC_TX_CLK_25_MHZ = 7,
4435 +};
4436 +
4437 +/***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
4438 +enum {
4439 + PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */
4440 + PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
4441 + PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
4442 + PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
4443 + PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
4444 + PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
4445 + PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
4446 + /* (88E1111 only) */
4447 +};
4448 +
4449 +enum {
4450 + PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */
4451 + /* (88E1011 only) */
4452 + PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
4453 + PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
4454 + PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
4455 + PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
4456 + PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
4457 +};
4458 +
4459 +#define PHY_M_LED_PULS_DUR(x) (((x)<<12) & PHY_M_LEDC_PULS_MSK)
4460 +
4461 +/***** PHY_MARV_PHY_STAT (page 3)16 bit r/w Polarity Control Reg. *****/
4462 +enum {
4463 + PHY_M_POLC_LS1M_MSK = 0xf<<12, /* Bit 15..12: LOS,STAT1 Mix % Mask */
4464 + PHY_M_POLC_IS0M_MSK = 0xf<<8, /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
4465 + PHY_M_POLC_LOS_MSK = 0x3<<6, /* Bit 7.. 6: LOS Pol. Ctrl. Mask */
4466 + PHY_M_POLC_INIT_MSK = 0x3<<4, /* Bit 5.. 4: INIT Pol. Ctrl. Mask */
4467 + PHY_M_POLC_STA1_MSK = 0x3<<2, /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */
4468 + PHY_M_POLC_STA0_MSK = 0x3, /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */
4469 +};
4470 +
4471 +#define PHY_M_POLC_LS1_P_MIX(x) (((x)<<12) & PHY_M_POLC_LS1M_MSK)
4472 +#define PHY_M_POLC_IS0_P_MIX(x) (((x)<<8) & PHY_M_POLC_IS0M_MSK)
4473 +#define PHY_M_POLC_LOS_CTRL(x) (((x)<<6) & PHY_M_POLC_LOS_MSK)
4474 +#define PHY_M_POLC_INIT_CTRL(x) (((x)<<4) & PHY_M_POLC_INIT_MSK)
4475 +#define PHY_M_POLC_STA1_CTRL(x) (((x)<<2) & PHY_M_POLC_STA1_MSK)
4476 +#define PHY_M_POLC_STA0_CTRL(x) (((x)<<0) & PHY_M_POLC_STA0_MSK)
4477 +
4478 +enum {
4479 + PULS_NO_STR = 0,/* no pulse stretching */
4480 + PULS_21MS = 1,/* 21 ms to 42 ms */
4481 + PULS_42MS = 2,/* 42 ms to 84 ms */
4482 + PULS_84MS = 3,/* 84 ms to 170 ms */
4483 + PULS_170MS = 4,/* 170 ms to 340 ms */
4484 + PULS_340MS = 5,/* 340 ms to 670 ms */
4485 + PULS_670MS = 6,/* 670 ms to 1.3 s */
4486 + PULS_1300MS = 7,/* 1.3 s to 2.7 s */
4487 +};
4488 +
4489 +#define PHY_M_LED_BLINK_RT(x) (((x)<<8) & PHY_M_LEDC_BL_R_MSK)
4490 +
4491 +enum {
4492 + BLINK_42MS = 0,/* 42 ms */
4493 + BLINK_84MS = 1,/* 84 ms */
4494 + BLINK_170MS = 2,/* 170 ms */
4495 + BLINK_340MS = 3,/* 340 ms */
4496 + BLINK_670MS = 4,/* 670 ms */
4497 +};
4498 +
4499 +/***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
4500 +#define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */
4501 + /* Bit 13..12: reserved */
4502 +#define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */
4503 +#define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */
4504 +#define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */
4505 +#define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */
4506 +#define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */
4507 +#define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */
4508 +
4509 +enum {
4510 + MO_LED_NORM = 0,
4511 + MO_LED_BLINK = 1,
4512 + MO_LED_OFF = 2,
4513 + MO_LED_ON = 3,
4514 +};
4515 +
4516 +/***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
4517 +enum {
4518 + PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */
4519 + PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */
4520 + PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
4521 + PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */
4522 + PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */
4523 +};
4524 +
4525 +/***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
4526 +enum {
4527 + PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
4528 + PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */
4529 + PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */
4530 + PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */
4531 + PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */
4532 + PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */
4533 + PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */
4534 + /* (88E1111 only) */
4535 +
4536 + PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
4537 + PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */
4538 + PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
4539 +};
4540 +
4541 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
4542 +/***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
4543 + /* Bit 15..12: reserved (used internally) */
4544 +enum {
4545 + PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
4546 + PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
4547 + PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
4548 +};
4549 +
4550 +#define PHY_M_FELP_LED2_CTRL(x) (((x)<<8) & PHY_M_FELP_LED2_MSK)
4551 +#define PHY_M_FELP_LED1_CTRL(x) (((x)<<4) & PHY_M_FELP_LED1_MSK)
4552 +#define PHY_M_FELP_LED0_CTRL(x) (((x)<<0) & PHY_M_FELP_LED0_MSK)
4553 +
4554 +enum {
4555 + LED_PAR_CTRL_COLX = 0x00,
4556 + LED_PAR_CTRL_ERROR = 0x01,
4557 + LED_PAR_CTRL_DUPLEX = 0x02,
4558 + LED_PAR_CTRL_DP_COL = 0x03,
4559 + LED_PAR_CTRL_SPEED = 0x04,
4560 + LED_PAR_CTRL_LINK = 0x05,
4561 + LED_PAR_CTRL_TX = 0x06,
4562 + LED_PAR_CTRL_RX = 0x07,
4563 + LED_PAR_CTRL_ACT = 0x08,
4564 + LED_PAR_CTRL_LNK_RX = 0x09,
4565 + LED_PAR_CTRL_LNK_AC = 0x0a,
4566 + LED_PAR_CTRL_ACT_BL = 0x0b,
4567 + LED_PAR_CTRL_TX_BL = 0x0c,
4568 + LED_PAR_CTRL_RX_BL = 0x0d,
4569 + LED_PAR_CTRL_COL_BL = 0x0e,
4570 + LED_PAR_CTRL_INACT = 0x0f
4571 +};
4572 +
4573 +/*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
4574 +enum {
4575 + PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */
4576 + PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
4577 + PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
4578 +};
4579 +
4580 +/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
4581 +/***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
4582 +enum {
4583 + PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */
4584 + PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */
4585 + PHY_M_MAC_MD_COPPER = 5,/* Copper only */
4586 + PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */
4587 +};
4588 +#define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK)
4589 +
4590 +/***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
4591 +enum {
4592 + PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */
4593 + PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
4594 + PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */
4595 + PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
4596 +};
4597 +
4598 +#define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK)
4599 +#define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK)
4600 +#define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK)
4601 +#define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK)
4602 +
4603 +/* GMAC registers */
4604 +/* Port Registers */
4605 +enum {
4606 + GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
4607 + GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
4608 + GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
4609 + GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
4610 + GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
4611 + GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
4612 + GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
4613 +/* Source Address Registers */
4614 + GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
4615 + GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
4616 + GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
4617 + GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
4618 + GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
4619 + GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
4620 +
4621 +/* Multicast Address Hash Registers */
4622 + GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
4623 + GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
4624 + GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
4625 + GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
4626 +
4627 +/* Interrupt Source Registers */
4628 + GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
4629 + GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
4630 + GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
4631 +
4632 +/* Interrupt Mask Registers */
4633 + GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
4634 + GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
4635 + GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
4636 +
4637 +/* Serial Management Interface (SMI) Registers */
4638 + GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
4639 + GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
4640 + GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
4641 +};
4642 +
4643 +/* MIB Counters */
4644 +#define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */
4645 +#define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */
4646 +
4647 +/*
4648 + * MIB Counters base address definitions (low word) -
4649 + * use offset 4 for access to high word (32 bit r/o)
4650 + */
4651 +enum {
4652 + GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */
4653 + GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */
4654 + GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
4655 + GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
4656 + GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
4657 + /* GM_MIB_CNT_BASE + 40: reserved */
4658 + GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
4659 + GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
4660 + GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
4661 + GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */
4662 + GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
4663 + GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
4664 + GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
4665 + GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */
4666 + GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */
4667 + GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */
4668 + GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */
4669 + GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */
4670 + GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */
4671 + GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152, /* Rx Frame too Long Error */
4672 + GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160, /* Rx Jabber Packet Frame */
4673 + /* GM_MIB_CNT_BASE + 168: reserved */
4674 + GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176, /* Rx FIFO overflow Event */
4675 + /* GM_MIB_CNT_BASE + 184: reserved */
4676 + GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192, /* Unicast Frames Xmitted OK */
4677 + GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200, /* Broadcast Frames Xmitted OK */
4678 + GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208, /* Pause MAC Ctrl Frames Xmitted */
4679 + GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216, /* Multicast Frames Xmitted OK */
4680 + GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224, /* Octets Transmitted OK Low */
4681 + GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232, /* Octets Transmitted OK High */
4682 + GM_TXF_64B = GM_MIB_CNT_BASE + 240, /* 64 Byte Tx Frame */
4683 + GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */
4684 + GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */
4685 + GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */
4686 + GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */
4687 + GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */
4688 + GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */
4689 +
4690 + GM_TXF_COL = GM_MIB_CNT_BASE + 304, /* Tx Collision */
4691 + GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312, /* Tx Late Collision */
4692 + GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320, /* Tx aborted due to Exces. Col. */
4693 + GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328, /* Tx Multiple Collision */
4694 + GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336, /* Tx Single Collision */
4695 + GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344, /* Tx FIFO Underrun Event */
4696 +};
4697 +
4698 +/* GMAC Bit Definitions */
4699 +/* GM_GP_STAT 16 bit r/o General Purpose Status Register */
4700 +enum {
4701 + GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */
4702 + GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
4703 + GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
4704 + GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
4705 + GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
4706 + GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
4707 + GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occured */
4708 + GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occured */
4709 +
4710 + GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
4711 + GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
4712 + GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */
4713 + GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
4714 + GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
4715 +};
4716 +
4717 +/* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
4718 +enum {
4719 + GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
4720 + GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
4721 + GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
4722 + GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
4723 + GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
4724 + GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
4725 + GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
4726 + GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */
4727 + GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */
4728 + GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
4729 + GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
4730 + GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */
4731 + GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
4732 + GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
4733 + GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
4734 +};
4735 +
4736 +#define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
4737 +#define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
4738 +
4739 +/* GM_TX_CTRL 16 bit r/w Transmit Control Register */
4740 +enum {
4741 + GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
4742 + GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
4743 + GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
4744 + GM_TXCR_COL_THR_MSK = 1<<10, /* Bit 12..10: Collision Threshold */
4745 +};
4746 +
4747 +#define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
4748 +#define TX_COL_DEF 0x04
4749 +
4750 +/* GM_RX_CTRL 16 bit r/w Receive Control Register */
4751 +enum {
4752 + GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
4753 + GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
4754 + GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
4755 + GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
4756 +};
4757 +
4758 +/* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
4759 +enum {
4760 + GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
4761 + GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */
4762 + GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */
4763 + GM_TXPA_BO_LIM_MSK = 0x0f, /* Bit 3.. 0: Backoff Limit Mask */
4764 +
4765 + TX_JAM_LEN_DEF = 0x03,
4766 + TX_JAM_IPG_DEF = 0x0b,
4767 + TX_IPG_JAM_DEF = 0x1c,
4768 + TX_BOF_LIM_DEF = 0x04,
4769 +};
4770 +
4771 +#define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK)
4772 +#define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK)
4773 +#define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK)
4774 +#define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK)
4775 +
4776 +
4777 +/* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
4778 +enum {
4779 + GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
4780 + GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */
4781 + GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */
4782 + GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
4783 + GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
4784 +};
4785 +
4786 +#define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
4787 +#define DATA_BLIND_DEF 0x04
4788 +
4789 +#define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
4790 +#define IPG_DATA_DEF 0x1e
4791 +
4792 +/* GM_SMI_CTRL 16 bit r/w SMI Control Register */
4793 +enum {
4794 + GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */
4795 + GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */
4796 + GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
4797 + GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
4798 + GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
4799 +};
4800 +
4801 +#define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
4802 +#define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK)
4803 +
4804 +/* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
4805 +enum {
4806 + GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
4807 + GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
4808 +};
4809 +
4810 +/* Receive Frame Status Encoding */
4811 +enum {
4812 + GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */
4813 + GMR_FS_VLAN = 1<<13, /* VLAN Packet */
4814 + GMR_FS_JABBER = 1<<12, /* Jabber Packet */
4815 + GMR_FS_UN_SIZE = 1<<11, /* Undersize Packet */
4816 + GMR_FS_MC = 1<<10, /* Multicast Packet */
4817 + GMR_FS_BC = 1<<9, /* Broadcast Packet */
4818 + GMR_FS_RX_OK = 1<<8, /* Receive OK (Good Packet) */
4819 + GMR_FS_GOOD_FC = 1<<7, /* Good Flow-Control Packet */
4820 + GMR_FS_BAD_FC = 1<<6, /* Bad Flow-Control Packet */
4821 + GMR_FS_MII_ERR = 1<<5, /* MII Error */
4822 + GMR_FS_LONG_ERR = 1<<4, /* Too Long Packet */
4823 + GMR_FS_FRAGMENT = 1<<3, /* Fragment */
4824 +
4825 + GMR_FS_CRC_ERR = 1<<1, /* CRC Error */
4826 + GMR_FS_RX_FF_OV = 1<<0, /* Rx FIFO Overflow */
4827 +
4828 + GMR_FS_ANY_ERR = GMR_FS_RX_FF_OV | GMR_FS_CRC_ERR |
4829 + GMR_FS_FRAGMENT | GMR_FS_LONG_ERR |
4830 + GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
4831 + GMR_FS_UN_SIZE | GMR_FS_JABBER,
4832 +};
4833 +
4834 +/* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
4835 +enum {
4836 + RX_TRUNC_ON = 1<<27, /* enable packet truncation */
4837 + RX_TRUNC_OFF = 1<<26, /* disable packet truncation */
4838 + RX_VLAN_STRIP_ON = 1<<25, /* enable VLAN stripping */
4839 + RX_VLAN_STRIP_OFF = 1<<24, /* disable VLAN stripping */
4840 +
4841 + GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */
4842 + GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */
4843 + GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */
4844 +
4845 + GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */
4846 + GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */
4847 + GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */
4848 + GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
4849 + GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
4850 + GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
4851 + GMF_CLI_RX_C = 1<<4, /* Clear IRQ Rx Frame Complete */
4852 +
4853 + GMF_OPER_ON = 1<<3, /* Operational Mode On */
4854 + GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
4855 + GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
4856 + GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */
4857 +
4858 + RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */
4859 +
4860 + GMF_RX_CTRL_DEF = GMF_OPER_ON | GMF_RX_F_FL_ON,
4861 +};
4862 +
4863 +
4864 +/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
4865 +enum {
4866 + TX_STFW_DIS = 1<<31,/* Disable Store & Forward (Yukon-EC Ultra) */
4867 + TX_STFW_ENA = 1<<30,/* Enable Store & Forward (Yukon-EC Ultra) */
4868 +
4869 + TX_VLAN_TAG_ON = 1<<25,/* enable VLAN tagging */
4870 + TX_VLAN_TAG_OFF = 1<<24,/* disable VLAN tagging */
4871 +
4872 + GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */
4873 + GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */
4874 + GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */
4875 +
4876 + GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */
4877 + GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
4878 + GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */
4879 +};
4880 +
4881 +/* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
4882 +enum {
4883 + GMT_ST_START = 1<<2, /* Start Time Stamp Timer */
4884 + GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */
4885 + GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */
4886 +};
4887 +
4888 +/* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */
4889 +enum {
4890 + Y2_ASF_OS_PRES = 1<<4, /* ASF operation system present */
4891 + Y2_ASF_RESET = 1<<3, /* ASF system in reset state */
4892 + Y2_ASF_RUNNING = 1<<2, /* ASF system operational */
4893 + Y2_ASF_CLR_HSTI = 1<<1, /* Clear ASF IRQ */
4894 + Y2_ASF_IRQ = 1<<0, /* Issue an IRQ to ASF system */
4895 +
4896 + Y2_ASF_UC_STATE = 3<<2, /* ASF uC State */
4897 + Y2_ASF_CLK_HALT = 0, /* ASF system clock stopped */
4898 +};
4899 +
4900 +/* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */
4901 +enum {
4902 + Y2_ASF_CLR_ASFI = 1<<1, /* Clear host IRQ */
4903 + Y2_ASF_HOST_IRQ = 1<<0, /* Issue an IRQ to HOST system */
4904 +};
4905 +
4906 +/* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
4907 +enum {
4908 + SC_STAT_CLR_IRQ = 1<<4, /* Status Burst IRQ clear */
4909 + SC_STAT_OP_ON = 1<<3, /* Operational Mode On */
4910 + SC_STAT_OP_OFF = 1<<2, /* Operational Mode Off */
4911 + SC_STAT_RST_CLR = 1<<1, /* Clear Status Unit Reset (Enable) */
4912 + SC_STAT_RST_SET = 1<<0, /* Set Status Unit Reset */
4913 +};
4914 +
4915 +/* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
4916 +enum {
4917 + GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */
4918 + GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
4919 + GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */
4920 + GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */
4921 + GMC_PAUSE_ON = 1<<3, /* Pause On */
4922 + GMC_PAUSE_OFF = 1<<2, /* Pause Off */
4923 + GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */
4924 + GMC_RST_SET = 1<<0, /* Set GMAC Reset */
4925 +};
4926 +
4927 +/* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
4928 +enum {
4929 + GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
4930 + GPC_INT_POL_HI = 1<<27, /* IRQ Polarity is Active HIGH */
4931 + GPC_75_OHM = 1<<26, /* Use 75 Ohm Termination instead of 50 */
4932 + GPC_DIS_FC = 1<<25, /* Disable Automatic Fiber/Copper Detection */
4933 + GPC_DIS_SLEEP = 1<<24, /* Disable Energy Detect */
4934 + GPC_HWCFG_M_3 = 1<<23, /* HWCFG_MODE[3] */
4935 + GPC_HWCFG_M_2 = 1<<22, /* HWCFG_MODE[2] */
4936 + GPC_HWCFG_M_1 = 1<<21, /* HWCFG_MODE[1] */
4937 + GPC_HWCFG_M_0 = 1<<20, /* HWCFG_MODE[0] */
4938 + GPC_ANEG_0 = 1<<19, /* ANEG[0] */
4939 + GPC_ENA_XC = 1<<18, /* Enable MDI crossover */
4940 + GPC_DIS_125 = 1<<17, /* Disable 125 MHz clock */
4941 + GPC_ANEG_3 = 1<<16, /* ANEG[3] */
4942 + GPC_ANEG_2 = 1<<15, /* ANEG[2] */
4943 + GPC_ANEG_1 = 1<<14, /* ANEG[1] */
4944 + GPC_ENA_PAUSE = 1<<13, /* Enable Pause (SYM_OR_REM) */
4945 + GPC_PHYADDR_4 = 1<<12, /* Bit 4 of Phy Addr */
4946 + GPC_PHYADDR_3 = 1<<11, /* Bit 3 of Phy Addr */
4947 + GPC_PHYADDR_2 = 1<<10, /* Bit 2 of Phy Addr */
4948 + GPC_PHYADDR_1 = 1<<9, /* Bit 1 of Phy Addr */
4949 + GPC_PHYADDR_0 = 1<<8, /* Bit 0 of Phy Addr */
4950 + /* Bits 7..2: reserved */
4951 + GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */
4952 + GPC_RST_SET = 1<<0, /* Set GPHY Reset */
4953 +};
4954 +
4955 +/* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
4956 +/* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
4957 +enum {
4958 + GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */
4959 + GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */
4960 + GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */
4961 + GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */
4962 + GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */
4963 + GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
4964 +
4965 +#define GMAC_DEF_MSK GM_IS_TX_FF_UR
4966 +
4967 +/* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
4968 + /* Bits 15.. 2: reserved */
4969 + GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */
4970 + GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */
4971 +
4972 +
4973 +/* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
4974 + WOL_CTL_LINK_CHG_OCC = 1<<15,
4975 + WOL_CTL_MAGIC_PKT_OCC = 1<<14,
4976 + WOL_CTL_PATTERN_OCC = 1<<13,
4977 + WOL_CTL_CLEAR_RESULT = 1<<12,
4978 + WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11,
4979 + WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10,
4980 + WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9,
4981 + WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8,
4982 + WOL_CTL_ENA_PME_ON_PATTERN = 1<<7,
4983 + WOL_CTL_DIS_PME_ON_PATTERN = 1<<6,
4984 + WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5,
4985 + WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4,
4986 + WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3,
4987 + WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2,
4988 + WOL_CTL_ENA_PATTERN_UNIT = 1<<1,
4989 + WOL_CTL_DIS_PATTERN_UNIT = 1<<0,
4990 +};
4991 +
4992 +#define WOL_CTL_DEFAULT \
4993 + (WOL_CTL_DIS_PME_ON_LINK_CHG | \
4994 + WOL_CTL_DIS_PME_ON_PATTERN | \
4995 + WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
4996 + WOL_CTL_DIS_LINK_CHG_UNIT | \
4997 + WOL_CTL_DIS_PATTERN_UNIT | \
4998 + WOL_CTL_DIS_MAGIC_PKT_UNIT)
4999 +
5000 +/* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
5001 +#define WOL_CTL_PATT_ENA(x) (1 << (x))
5002 +
5003 +
5004 +/* Control flags */
5005 +enum {
5006 + UDPTCP = 1<<0,
5007 + CALSUM = 1<<1,
5008 + WR_SUM = 1<<2,
5009 + INIT_SUM= 1<<3,
5010 + LOCK_SUM= 1<<4,
5011 + INS_VLAN= 1<<5,
5012 + FRC_STAT= 1<<6,
5013 + EOP = 1<<7,
5014 +};
5015 +
5016 +enum {
5017 + HW_OWNER = 1<<7,
5018 + OP_TCPWRITE = 0x11,
5019 + OP_TCPSTART = 0x12,
5020 + OP_TCPINIT = 0x14,
5021 + OP_TCPLCK = 0x18,
5022 + OP_TCPCHKSUM = OP_TCPSTART,
5023 + OP_TCPIS = OP_TCPINIT | OP_TCPSTART,
5024 + OP_TCPLW = OP_TCPLCK | OP_TCPWRITE,
5025 + OP_TCPLSW = OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE,
5026 + OP_TCPLISW = OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE,
5027 +
5028 + OP_ADDR64 = 0x21,
5029 + OP_VLAN = 0x22,
5030 + OP_ADDR64VLAN = OP_ADDR64 | OP_VLAN,
5031 + OP_LRGLEN = 0x24,
5032 + OP_LRGLENVLAN = OP_LRGLEN | OP_VLAN,
5033 + OP_BUFFER = 0x40,
5034 + OP_PACKET = 0x41,
5035 + OP_LARGESEND = 0x43,
5036 +
5037 +/* YUKON-2 STATUS opcodes defines */
5038 + OP_RXSTAT = 0x60,
5039 + OP_RXTIMESTAMP = 0x61,
5040 + OP_RXVLAN = 0x62,
5041 + OP_RXCHKS = 0x64,
5042 + OP_RXCHKSVLAN = OP_RXCHKS | OP_RXVLAN,
5043 + OP_RXTIMEVLAN = OP_RXTIMESTAMP | OP_RXVLAN,
5044 + OP_RSS_HASH = 0x65,
5045 + OP_TXINDEXLE = 0x68,
5046 +};
5047 +
5048 +/* Yukon 2 hardware interface
5049 + * Not tested on big endian
5050 + */
5051 +struct sky2_tx_le {
5052 + union {
5053 + __le32 addr;
5054 + struct {
5055 + __le16 offset;
5056 + __le16 start;
5057 + } csum __attribute((packed));
5058 + struct {
5059 + __le16 size;
5060 + __le16 rsvd;
5061 + } tso __attribute((packed));
5062 + } tx;
5063 + __le16 length; /* also vlan tag or checksum start */
5064 + u8 ctrl;
5065 + u8 opcode;
5066 +} __attribute((packed));
5067 +
5068 +struct sky2_rx_le {
5069 + __le32 addr;
5070 + __le16 length;
5071 + u8 ctrl;
5072 + u8 opcode;
5073 +} __attribute((packed));;
5074 +
5075 +struct sky2_status_le {
5076 + __le32 status; /* also checksum */
5077 + __le16 length; /* also vlan tag */
5078 + u8 link;
5079 + u8 opcode;
5080 +} __attribute((packed));
5081 +
5082 +struct tx_ring_info {
5083 + struct sk_buff *skb;
5084 + DECLARE_PCI_UNMAP_ADDR(mapaddr);
5085 + u16 idx;
5086 +};
5087 +
5088 +struct ring_info {
5089 + struct sk_buff *skb;
5090 + dma_addr_t mapaddr;
5091 +};
5092 +
5093 +struct sky2_port {
5094 + struct sky2_hw *hw;
5095 + struct net_device *netdev;
5096 + unsigned port;
5097 + u32 msg_enable;
5098 +
5099 + spinlock_t tx_lock ____cacheline_aligned_in_smp;
5100 + struct tx_ring_info *tx_ring;
5101 + struct sky2_tx_le *tx_le;
5102 + u16 tx_cons; /* next le to check */
5103 + u16 tx_prod; /* next le to use */
5104 + u32 tx_addr64;
5105 + u16 tx_pending;
5106 + u16 tx_last_put;
5107 + u16 tx_last_mss;
5108 +
5109 + struct ring_info *rx_ring ____cacheline_aligned_in_smp;
5110 + struct sky2_rx_le *rx_le;
5111 + u32 rx_addr64;
5112 + u16 rx_next; /* next re to check */
5113 + u16 rx_put; /* next le index to use */
5114 + u16 rx_pending;
5115 + u16 rx_last_put;
5116 + u16 rx_bufsize;
5117 +#ifdef SKY2_VLAN_TAG_USED
5118 + u16 rx_tag;
5119 + struct vlan_group *vlgrp;
5120 +#endif
5121 +
5122 + dma_addr_t rx_le_map;
5123 + dma_addr_t tx_le_map;
5124 + u32 advertising; /* ADVERTISED_ bits */
5125 + u16 speed; /* SPEED_1000, SPEED_100, ... */
5126 + u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */
5127 + u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */
5128 + u8 rx_pause;
5129 + u8 tx_pause;
5130 + u8 rx_csum;
5131 + u8 wol;
5132 +
5133 + struct net_device_stats net_stats;
5134 +
5135 + struct work_struct phy_task;
5136 + struct semaphore phy_sema;
5137 +};
5138 +
5139 +struct sky2_hw {
5140 + void __iomem *regs;
5141 + struct pci_dev *pdev;
5142 + u32 intr_mask;
5143 + struct net_device *dev[2];
5144 +
5145 + int pm_cap;
5146 + u8 chip_id;
5147 + u8 chip_rev;
5148 + u8 copper;
5149 + u8 ports;
5150 +
5151 + struct sky2_status_le *st_le;
5152 + u32 st_idx;
5153 + dma_addr_t st_dma;
5154 +};
5155 +
5156 +/* Register accessor for memory mapped device */
5157 +static inline u32 sky2_read32(const struct sky2_hw *hw, unsigned reg)
5158 +{
5159 + return readl(hw->regs + reg);
5160 +}
5161 +
5162 +static inline u16 sky2_read16(const struct sky2_hw *hw, unsigned reg)
5163 +{
5164 + return readw(hw->regs + reg);
5165 +}
5166 +
5167 +static inline u8 sky2_read8(const struct sky2_hw *hw, unsigned reg)
5168 +{
5169 + return readb(hw->regs + reg);
5170 +}
5171 +
5172 +/* This should probably go away, bus based tweeks suck */
5173 +static inline int is_pciex(const struct sky2_hw *hw)
5174 +{
5175 + u32 status;
5176 + pci_read_config_dword(hw->pdev, PCI_DEV_STATUS, &status);
5177 + return (status & PCI_OS_PCI_X) == 0;
5178 +}
5179 +
5180 +static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val)
5181 +{
5182 + writel(val, hw->regs + reg);
5183 +}
5184 +
5185 +static inline void sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val)
5186 +{
5187 + writew(val, hw->regs + reg);
5188 +}
5189 +
5190 +static inline void sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val)
5191 +{
5192 + writeb(val, hw->regs + reg);
5193 +}
5194 +
5195 +/* Yukon PHY related registers */
5196 +#define SK_GMAC_REG(port,reg) \
5197 + (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
5198 +#define GM_PHY_RETRIES 100
5199 +
5200 +static inline u16 gma_read16(const struct sky2_hw *hw, unsigned port, unsigned reg)
5201 +{
5202 + return sky2_read16(hw, SK_GMAC_REG(port,reg));
5203 +}
5204 +
5205 +static inline u32 gma_read32(struct sky2_hw *hw, unsigned port, unsigned reg)
5206 +{
5207 + unsigned base = SK_GMAC_REG(port, reg);
5208 + return (u32) sky2_read16(hw, base)
5209 + | (u32) sky2_read16(hw, base+4) << 16;
5210 +}
5211 +
5212 +static inline void gma_write16(const struct sky2_hw *hw, unsigned port, int r, u16 v)
5213 +{
5214 + sky2_write16(hw, SK_GMAC_REG(port,r), v);
5215 +}
5216 +
5217 +static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg,
5218 + const u8 *addr)
5219 +{
5220 + gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8));
5221 + gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
5222 + gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
5223 +}
5224 +#endif
5225 --- linux-2.6.15/include/linux/netdevice.h 2006-01-03 17:42:43.000000000 +0000
5226 +++ linux-dsd/include/linux/netdevice.h 2006-01-03 18:10:52.000000000 +0000
5227 @@ -801,12 +801,16 @@ static inline u32 netif_msg_init(int deb
5228 return (1 << debug_value) - 1;
5229 }
5230
5231 -/* Schedule rx intr now? */
5232 +/* Test if receive needs to be scheduled */
5233 +static inline int __netif_rx_schedule_prep(struct net_device *dev)
5234 +{
5235 + return !test_and_set_bit(__LINK_STATE_RX_SCHED, &dev->state);
5236 +}
5237
5238 +/* Test if receive needs to be scheduled but only if up */
5239 static inline int netif_rx_schedule_prep(struct net_device *dev)
5240 {
5241 - return netif_running(dev) &&
5242 - !test_and_set_bit(__LINK_STATE_RX_SCHED, &dev->state);
5243 + return netif_running(dev) && __netif_rx_schedule_prep(dev);
5244 }
5245
5246 /* Add interface to tail of rx poll list. This assumes that _prep has

  ViewVC Help
Powered by ViewVC 1.1.20