/[linux-patches]/genpatches-2.6/trunk/2.6.15/4100_sky2-0.13.patch
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Contents of /genpatches-2.6/trunk/2.6.15/4100_sky2-0.13.patch

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Revision 265 - (show annotations) (download) (as text)
Sat Jan 21 12:52:41 2006 UTC (14 years, 10 months ago) by dsd
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sky2 v0.13
1 sky2 v0.13
2
3 --- linux-2.6.15/drivers/net/sky2.c 1970-01-01 01:00:00.000000000 +0100
4 +++ linux-2.6.15-gentoo-r1/drivers/net/sky2.c 2006-01-21 12:48:16.000000000 +0000
5 @@ -0,0 +1,3315 @@
6 +/*
7 + * New driver for Marvell Yukon 2 chipset.
8 + * Based on earlier sk98lin, and skge driver.
9 + *
10 + * This driver intentionally does not support all the features
11 + * of the original driver such as link fail-over and link management because
12 + * those should be done at higher levels.
13 + *
14 + * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
15 + *
16 + * This program is free software; you can redistribute it and/or modify
17 + * it under the terms of the GNU General Public License as published by
18 + * the Free Software Foundation; either version 2 of the License, or
19 + * (at your option) any later version.
20 + *
21 + * This program is distributed in the hope that it will be useful,
22 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 + * GNU General Public License for more details.
25 + *
26 + * You should have received a copy of the GNU General Public License
27 + * along with this program; if not, write to the Free Software
28 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 + */
30 +
31 +/*
32 + * TOTEST
33 + * - speed setting
34 + * - suspend/resume
35 + */
36 +
37 +#include <linux/config.h>
38 +#include <linux/crc32.h>
39 +#include <linux/kernel.h>
40 +#include <linux/version.h>
41 +#include <linux/module.h>
42 +#include <linux/netdevice.h>
43 +#include <linux/dma-mapping.h>
44 +#include <linux/etherdevice.h>
45 +#include <linux/ethtool.h>
46 +#include <linux/pci.h>
47 +#include <linux/ip.h>
48 +#include <linux/tcp.h>
49 +#include <linux/in.h>
50 +#include <linux/delay.h>
51 +#include <linux/workqueue.h>
52 +#include <linux/if_vlan.h>
53 +#include <linux/prefetch.h>
54 +#include <linux/mii.h>
55 +
56 +#include <asm/irq.h>
57 +
58 +#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
59 +#define SKY2_VLAN_TAG_USED 1
60 +#endif
61 +
62 +#include "sky2.h"
63 +
64 +#define DRV_NAME "sky2"
65 +#define DRV_VERSION "0.13"
66 +#define PFX DRV_NAME " "
67 +
68 +/*
69 + * The Yukon II chipset takes 64 bit command blocks (called list elements)
70 + * that are organized into three (receive, transmit, status) different rings
71 + * similar to Tigon3. A transmit can require several elements;
72 + * a receive requires one (or two if using 64 bit dma).
73 + */
74 +
75 +#define is_ec_a1(hw) \
76 + unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
77 + (hw)->chip_rev == CHIP_REV_YU_EC_A1)
78 +
79 +#define RX_LE_SIZE 512
80 +#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
81 +#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
82 +#define RX_DEF_PENDING RX_MAX_PENDING
83 +#define RX_SKB_ALIGN 8
84 +
85 +#define TX_RING_SIZE 512
86 +#define TX_DEF_PENDING (TX_RING_SIZE - 1)
87 +#define TX_MIN_PENDING 64
88 +#define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
89 +
90 +#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
91 +#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
92 +#define ETH_JUMBO_MTU 9000
93 +#define TX_WATCHDOG (5 * HZ)
94 +#define NAPI_WEIGHT 64
95 +#define PHY_RETRIES 1000
96 +
97 +static const u32 default_msg =
98 + NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
99 + | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
100 + | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
101 +
102 +static int debug = -1; /* defaults above */
103 +module_param(debug, int, 0);
104 +MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
105 +
106 +static int copybreak __read_mostly = 256;
107 +module_param(copybreak, int, 0);
108 +MODULE_PARM_DESC(copybreak, "Receive copy threshold");
109 +
110 +static const struct pci_device_id sky2_id_table[] = {
111 + { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
112 + { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
113 + { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
114 + { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
115 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
116 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
117 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
118 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
119 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
120 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
121 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
122 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
123 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
124 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
125 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
126 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
127 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
128 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
129 + { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
130 + { 0 }
131 +};
132 +
133 +MODULE_DEVICE_TABLE(pci, sky2_id_table);
134 +
135 +/* Avoid conditionals by using array */
136 +static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
137 +static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
138 +
139 +/* This driver supports yukon2 chipset only */
140 +static const char *yukon2_name[] = {
141 + "XL", /* 0xb3 */
142 + "EC Ultra", /* 0xb4 */
143 + "UNKNOWN", /* 0xb5 */
144 + "EC", /* 0xb6 */
145 + "FE", /* 0xb7 */
146 +};
147 +
148 +/* Access to external PHY */
149 +static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
150 +{
151 + int i;
152 +
153 + gma_write16(hw, port, GM_SMI_DATA, val);
154 + gma_write16(hw, port, GM_SMI_CTRL,
155 + GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
156 +
157 + for (i = 0; i < PHY_RETRIES; i++) {
158 + if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
159 + return 0;
160 + udelay(1);
161 + }
162 +
163 + printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
164 + return -ETIMEDOUT;
165 +}
166 +
167 +static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
168 +{
169 + int i;
170 +
171 + gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
172 + | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
173 +
174 + for (i = 0; i < PHY_RETRIES; i++) {
175 + if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
176 + *val = gma_read16(hw, port, GM_SMI_DATA);
177 + return 0;
178 + }
179 +
180 + udelay(1);
181 + }
182 +
183 + return -ETIMEDOUT;
184 +}
185 +
186 +static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
187 +{
188 + u16 v;
189 +
190 + if (__gm_phy_read(hw, port, reg, &v) != 0)
191 + printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
192 + return v;
193 +}
194 +
195 +static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
196 +{
197 + u16 power_control;
198 + u32 reg1;
199 + int vaux;
200 + int ret = 0;
201 +
202 + pr_debug("sky2_set_power_state %d\n", state);
203 + sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
204 +
205 + pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control);
206 + vaux = (sky2_read8(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
207 + (power_control & PCI_PM_CAP_PME_D3cold);
208 +
209 + pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control);
210 +
211 + power_control |= PCI_PM_CTRL_PME_STATUS;
212 + power_control &= ~(PCI_PM_CTRL_STATE_MASK);
213 +
214 + switch (state) {
215 + case PCI_D0:
216 + /* switch power to VCC (WA for VAUX problem) */
217 + sky2_write8(hw, B0_POWER_CTRL,
218 + PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
219 +
220 + /* disable Core Clock Division, */
221 + sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
222 +
223 + if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
224 + /* enable bits are inverted */
225 + sky2_write8(hw, B2_Y2_CLK_GATE,
226 + Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
227 + Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
228 + Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
229 + else
230 + sky2_write8(hw, B2_Y2_CLK_GATE, 0);
231 +
232 + /* Turn off phy power saving */
233 + pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
234 + reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
235 +
236 + /* looks like this XL is back asswards .. */
237 + if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
238 + reg1 |= PCI_Y2_PHY1_COMA;
239 + if (hw->ports > 1)
240 + reg1 |= PCI_Y2_PHY2_COMA;
241 + }
242 + pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
243 + break;
244 +
245 + case PCI_D3hot:
246 + case PCI_D3cold:
247 + /* Turn on phy power saving */
248 + pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
249 + if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
250 + reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
251 + else
252 + reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
253 + pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
254 +
255 + if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
256 + sky2_write8(hw, B2_Y2_CLK_GATE, 0);
257 + else
258 + /* enable bits are inverted */
259 + sky2_write8(hw, B2_Y2_CLK_GATE,
260 + Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
261 + Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
262 + Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
263 +
264 + /* switch power to VAUX */
265 + if (vaux && state != PCI_D3cold)
266 + sky2_write8(hw, B0_POWER_CTRL,
267 + (PC_VAUX_ENA | PC_VCC_ENA |
268 + PC_VAUX_ON | PC_VCC_OFF));
269 + break;
270 + default:
271 + printk(KERN_ERR PFX "Unknown power state %d\n", state);
272 + ret = -1;
273 + }
274 +
275 + pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control);
276 + sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
277 + return ret;
278 +}
279 +
280 +static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
281 +{
282 + u16 reg;
283 +
284 + /* disable all GMAC IRQ's */
285 + sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
286 + /* disable PHY IRQs */
287 + gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
288 +
289 + gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
290 + gma_write16(hw, port, GM_MC_ADDR_H2, 0);
291 + gma_write16(hw, port, GM_MC_ADDR_H3, 0);
292 + gma_write16(hw, port, GM_MC_ADDR_H4, 0);
293 +
294 + reg = gma_read16(hw, port, GM_RX_CTRL);
295 + reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
296 + gma_write16(hw, port, GM_RX_CTRL, reg);
297 +}
298 +
299 +static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
300 +{
301 + struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
302 + u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
303 +
304 + if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
305 + u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
306 +
307 + ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
308 + PHY_M_EC_MAC_S_MSK);
309 + ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
310 +
311 + if (hw->chip_id == CHIP_ID_YUKON_EC)
312 + ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
313 + else
314 + ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
315 +
316 + gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
317 + }
318 +
319 + ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
320 + if (hw->copper) {
321 + if (hw->chip_id == CHIP_ID_YUKON_FE) {
322 + /* enable automatic crossover */
323 + ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
324 + } else {
325 + /* disable energy detect */
326 + ctrl &= ~PHY_M_PC_EN_DET_MSK;
327 +
328 + /* enable automatic crossover */
329 + ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
330 +
331 + if (sky2->autoneg == AUTONEG_ENABLE &&
332 + hw->chip_id == CHIP_ID_YUKON_XL) {
333 + ctrl &= ~PHY_M_PC_DSC_MSK;
334 + ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
335 + }
336 + }
337 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
338 + } else {
339 + /* workaround for deviation #4.88 (CRC errors) */
340 + /* disable Automatic Crossover */
341 +
342 + ctrl &= ~PHY_M_PC_MDIX_MSK;
343 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
344 +
345 + if (hw->chip_id == CHIP_ID_YUKON_XL) {
346 + /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
347 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
348 + ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
349 + ctrl &= ~PHY_M_MAC_MD_MSK;
350 + ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
351 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
352 +
353 + /* select page 1 to access Fiber registers */
354 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
355 + }
356 + }
357 +
358 + ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
359 + if (sky2->autoneg == AUTONEG_DISABLE)
360 + ctrl &= ~PHY_CT_ANE;
361 + else
362 + ctrl |= PHY_CT_ANE;
363 +
364 + ctrl |= PHY_CT_RESET;
365 + gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
366 +
367 + ctrl = 0;
368 + ct1000 = 0;
369 + adv = PHY_AN_CSMA;
370 +
371 + if (sky2->autoneg == AUTONEG_ENABLE) {
372 + if (hw->copper) {
373 + if (sky2->advertising & ADVERTISED_1000baseT_Full)
374 + ct1000 |= PHY_M_1000C_AFD;
375 + if (sky2->advertising & ADVERTISED_1000baseT_Half)
376 + ct1000 |= PHY_M_1000C_AHD;
377 + if (sky2->advertising & ADVERTISED_100baseT_Full)
378 + adv |= PHY_M_AN_100_FD;
379 + if (sky2->advertising & ADVERTISED_100baseT_Half)
380 + adv |= PHY_M_AN_100_HD;
381 + if (sky2->advertising & ADVERTISED_10baseT_Full)
382 + adv |= PHY_M_AN_10_FD;
383 + if (sky2->advertising & ADVERTISED_10baseT_Half)
384 + adv |= PHY_M_AN_10_HD;
385 + } else /* special defines for FIBER (88E1011S only) */
386 + adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
387 +
388 + /* Set Flow-control capabilities */
389 + if (sky2->tx_pause && sky2->rx_pause)
390 + adv |= PHY_AN_PAUSE_CAP; /* symmetric */
391 + else if (sky2->rx_pause && !sky2->tx_pause)
392 + adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
393 + else if (!sky2->rx_pause && sky2->tx_pause)
394 + adv |= PHY_AN_PAUSE_ASYM; /* local */
395 +
396 + /* Restart Auto-negotiation */
397 + ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
398 + } else {
399 + /* forced speed/duplex settings */
400 + ct1000 = PHY_M_1000C_MSE;
401 +
402 + if (sky2->duplex == DUPLEX_FULL)
403 + ctrl |= PHY_CT_DUP_MD;
404 +
405 + switch (sky2->speed) {
406 + case SPEED_1000:
407 + ctrl |= PHY_CT_SP1000;
408 + break;
409 + case SPEED_100:
410 + ctrl |= PHY_CT_SP100;
411 + break;
412 + }
413 +
414 + ctrl |= PHY_CT_RESET;
415 + }
416 +
417 + if (hw->chip_id != CHIP_ID_YUKON_FE)
418 + gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
419 +
420 + gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
421 + gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
422 +
423 + /* Setup Phy LED's */
424 + ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
425 + ledover = 0;
426 +
427 + switch (hw->chip_id) {
428 + case CHIP_ID_YUKON_FE:
429 + /* on 88E3082 these bits are at 11..9 (shifted left) */
430 + ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
431 +
432 + ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
433 +
434 + /* delete ACT LED control bits */
435 + ctrl &= ~PHY_M_FELP_LED1_MSK;
436 + /* change ACT LED control to blink mode */
437 + ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
438 + gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
439 + break;
440 +
441 + case CHIP_ID_YUKON_XL:
442 + pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
443 +
444 + /* select page 3 to access LED control register */
445 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
446 +
447 + /* set LED Function Control register */
448 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
449 + PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
450 + PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
451 + PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
452 +
453 + /* set Polarity Control register */
454 + gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
455 + (PHY_M_POLC_LS1_P_MIX(4) |
456 + PHY_M_POLC_IS0_P_MIX(4) |
457 + PHY_M_POLC_LOS_CTRL(2) |
458 + PHY_M_POLC_INIT_CTRL(2) |
459 + PHY_M_POLC_STA1_CTRL(2) |
460 + PHY_M_POLC_STA0_CTRL(2)));
461 +
462 + /* restore page register */
463 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
464 + break;
465 +
466 + default:
467 + /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
468 + ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
469 + /* turn off the Rx LED (LED_RX) */
470 + ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
471 + }
472 +
473 + gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
474 +
475 + if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
476 + /* turn on 100 Mbps LED (LED_LINK100) */
477 + ledover |= PHY_M_LED_MO_100(MO_LED_ON);
478 + }
479 +
480 + if (ledover)
481 + gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
482 +
483 + /* Enable phy interrupt on auto-negotiation complete (or link up) */
484 + if (sky2->autoneg == AUTONEG_ENABLE)
485 + gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
486 + else
487 + gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
488 +}
489 +
490 +/* Force a renegotiation */
491 +static void sky2_phy_reinit(struct sky2_port *sky2)
492 +{
493 + down(&sky2->phy_sema);
494 + sky2_phy_init(sky2->hw, sky2->port);
495 + up(&sky2->phy_sema);
496 +}
497 +
498 +static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
499 +{
500 + struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
501 + u16 reg;
502 + int i;
503 + const u8 *addr = hw->dev[port]->dev_addr;
504 +
505 + sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
506 + sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
507 +
508 + sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
509 +
510 + if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
511 + /* WA DEV_472 -- looks like crossed wires on port 2 */
512 + /* clear GMAC 1 Control reset */
513 + sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
514 + do {
515 + sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
516 + sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
517 + } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
518 + gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
519 + gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
520 + }
521 +
522 + if (sky2->autoneg == AUTONEG_DISABLE) {
523 + reg = gma_read16(hw, port, GM_GP_CTRL);
524 + reg |= GM_GPCR_AU_ALL_DIS;
525 + gma_write16(hw, port, GM_GP_CTRL, reg);
526 + gma_read16(hw, port, GM_GP_CTRL);
527 +
528 + switch (sky2->speed) {
529 + case SPEED_1000:
530 + reg |= GM_GPCR_SPEED_1000;
531 + /* fallthru */
532 + case SPEED_100:
533 + reg |= GM_GPCR_SPEED_100;
534 + }
535 +
536 + if (sky2->duplex == DUPLEX_FULL)
537 + reg |= GM_GPCR_DUP_FULL;
538 + } else
539 + reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
540 +
541 + if (!sky2->tx_pause && !sky2->rx_pause) {
542 + sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
543 + reg |=
544 + GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
545 + } else if (sky2->tx_pause && !sky2->rx_pause) {
546 + /* disable Rx flow-control */
547 + reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
548 + }
549 +
550 + gma_write16(hw, port, GM_GP_CTRL, reg);
551 +
552 + sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
553 +
554 + down(&sky2->phy_sema);
555 + sky2_phy_init(hw, port);
556 + up(&sky2->phy_sema);
557 +
558 + /* MIB clear */
559 + reg = gma_read16(hw, port, GM_PHY_ADDR);
560 + gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
561 +
562 + for (i = 0; i < GM_MIB_CNT_SIZE; i++)
563 + gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
564 + gma_write16(hw, port, GM_PHY_ADDR, reg);
565 +
566 + /* transmit control */
567 + gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
568 +
569 + /* receive control reg: unicast + multicast + no FCS */
570 + gma_write16(hw, port, GM_RX_CTRL,
571 + GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
572 +
573 + /* transmit flow control */
574 + gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
575 +
576 + /* transmit parameter */
577 + gma_write16(hw, port, GM_TX_PARAM,
578 + TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
579 + TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
580 + TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
581 + TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
582 +
583 + /* serial mode register */
584 + reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
585 + GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
586 +
587 + if (hw->dev[port]->mtu > ETH_DATA_LEN)
588 + reg |= GM_SMOD_JUMBO_ENA;
589 +
590 + gma_write16(hw, port, GM_SERIAL_MODE, reg);
591 +
592 + /* virtual address for data */
593 + gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
594 +
595 + /* physical address: used for pause frames */
596 + gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
597 +
598 + /* ignore counter overflows */
599 + gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
600 + gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
601 + gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
602 +
603 + /* Configure Rx MAC FIFO */
604 + sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
605 + sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
606 + GMF_RX_CTRL_DEF);
607 +
608 + /* Flush Rx MAC FIFO on any flow control or error */
609 + sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
610 +
611 + /* Set threshold to 0xa (64 bytes)
612 + * ASF disabled so no need to do WA dev #4.30
613 + */
614 + sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
615 +
616 + /* Configure Tx MAC FIFO */
617 + sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
618 + sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
619 +
620 + if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
621 + sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
622 + sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
623 + if (hw->dev[port]->mtu > ETH_DATA_LEN) {
624 + /* set Tx GMAC FIFO Almost Empty Threshold */
625 + sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
626 + /* Disable Store & Forward mode for TX */
627 + sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
628 + }
629 + }
630 +
631 +}
632 +
633 +/* Assign Ram Buffer allocation.
634 + * start and end are in units of 4k bytes
635 + * ram registers are in units of 64bit words
636 + */
637 +static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
638 +{
639 + u32 start, end;
640 +
641 + start = startk * 4096/8;
642 + end = (endk * 4096/8) - 1;
643 +
644 + sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
645 + sky2_write32(hw, RB_ADDR(q, RB_START), start);
646 + sky2_write32(hw, RB_ADDR(q, RB_END), end);
647 + sky2_write32(hw, RB_ADDR(q, RB_WP), start);
648 + sky2_write32(hw, RB_ADDR(q, RB_RP), start);
649 +
650 + if (q == Q_R1 || q == Q_R2) {
651 + u32 space = (endk - startk) * 4096/8;
652 + u32 tp = space - space/4;
653 +
654 + /* On receive queue's set the thresholds
655 + * give receiver priority when > 3/4 full
656 + * send pause when down to 2K
657 + */
658 + sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
659 + sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
660 +
661 + tp = space - 2048/8;
662 + sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
663 + sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
664 + } else {
665 + /* Enable store & forward on Tx queue's because
666 + * Tx FIFO is only 1K on Yukon
667 + */
668 + sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
669 + }
670 +
671 + sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
672 + sky2_read8(hw, RB_ADDR(q, RB_CTRL));
673 +}
674 +
675 +/* Setup Bus Memory Interface */
676 +static void sky2_qset(struct sky2_hw *hw, u16 q)
677 +{
678 + sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
679 + sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
680 + sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
681 + sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
682 +}
683 +
684 +/* Setup prefetch unit registers. This is the interface between
685 + * hardware and driver list elements
686 + */
687 +static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
688 + u64 addr, u32 last)
689 +{
690 + sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
691 + sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
692 + sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
693 + sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
694 + sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
695 + sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
696 +
697 + sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
698 +}
699 +
700 +static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
701 +{
702 + struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
703 +
704 + sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
705 + return le;
706 +}
707 +
708 +/*
709 + * This is a workaround code taken from SysKonnect sk98lin driver
710 + * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
711 + */
712 +static void sky2_put_idx(struct sky2_hw *hw, unsigned q,
713 + u16 idx, u16 *last, u16 size)
714 +{
715 + wmb();
716 + if (is_ec_a1(hw) && idx < *last) {
717 + u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
718 +
719 + if (hwget == 0) {
720 + /* Start prefetching again */
721 + sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
722 + goto setnew;
723 + }
724 +
725 + if (hwget == size - 1) {
726 + /* set watermark to one list element */
727 + sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
728 +
729 + /* set put index to first list element */
730 + sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
731 + } else /* have hardware go to end of list */
732 + sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
733 + size - 1);
734 + } else {
735 +setnew:
736 + sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
737 + }
738 + *last = idx;
739 + mmiowb();
740 +}
741 +
742 +
743 +static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
744 +{
745 + struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
746 + sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
747 + return le;
748 +}
749 +
750 +/* Return high part of DMA address (could be 32 or 64 bit) */
751 +static inline u32 high32(dma_addr_t a)
752 +{
753 + return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
754 +}
755 +
756 +/* Build description to hardware about buffer */
757 +static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
758 +{
759 + struct sky2_rx_le *le;
760 + u32 hi = high32(map);
761 + u16 len = sky2->rx_bufsize;
762 +
763 + if (sky2->rx_addr64 != hi) {
764 + le = sky2_next_rx(sky2);
765 + le->addr = cpu_to_le32(hi);
766 + le->ctrl = 0;
767 + le->opcode = OP_ADDR64 | HW_OWNER;
768 + sky2->rx_addr64 = high32(map + len);
769 + }
770 +
771 + le = sky2_next_rx(sky2);
772 + le->addr = cpu_to_le32((u32) map);
773 + le->length = cpu_to_le16(len);
774 + le->ctrl = 0;
775 + le->opcode = OP_PACKET | HW_OWNER;
776 +}
777 +
778 +
779 +/* Tell chip where to start receive checksum.
780 + * Actually has two checksums, but set both same to avoid possible byte
781 + * order problems.
782 + */
783 +static void rx_set_checksum(struct sky2_port *sky2)
784 +{
785 + struct sky2_rx_le *le;
786 +
787 + le = sky2_next_rx(sky2);
788 + le->addr = (ETH_HLEN << 16) | ETH_HLEN;
789 + le->ctrl = 0;
790 + le->opcode = OP_TCPSTART | HW_OWNER;
791 +
792 + sky2_write32(sky2->hw,
793 + Q_ADDR(rxqaddr[sky2->port], Q_CSR),
794 + sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
795 +
796 +}
797 +
798 +/*
799 + * The RX Stop command will not work for Yukon-2 if the BMU does not
800 + * reach the end of packet and since we can't make sure that we have
801 + * incoming data, we must reset the BMU while it is not doing a DMA
802 + * transfer. Since it is possible that the RX path is still active,
803 + * the RX RAM buffer will be stopped first, so any possible incoming
804 + * data will not trigger a DMA. After the RAM buffer is stopped, the
805 + * BMU is polled until any DMA in progress is ended and only then it
806 + * will be reset.
807 + */
808 +static void sky2_rx_stop(struct sky2_port *sky2)
809 +{
810 + struct sky2_hw *hw = sky2->hw;
811 + unsigned rxq = rxqaddr[sky2->port];
812 + int i;
813 +
814 + /* disable the RAM Buffer receive queue */
815 + sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
816 +
817 + for (i = 0; i < 0xffff; i++)
818 + if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
819 + == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
820 + goto stopped;
821 +
822 + printk(KERN_WARNING PFX "%s: receiver stop failed\n",
823 + sky2->netdev->name);
824 +stopped:
825 + sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
826 +
827 + /* reset the Rx prefetch unit */
828 + sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
829 +}
830 +
831 +/* Clean out receive buffer area, assumes receiver hardware stopped */
832 +static void sky2_rx_clean(struct sky2_port *sky2)
833 +{
834 + unsigned i;
835 +
836 + memset(sky2->rx_le, 0, RX_LE_BYTES);
837 + for (i = 0; i < sky2->rx_pending; i++) {
838 + struct ring_info *re = sky2->rx_ring + i;
839 +
840 + if (re->skb) {
841 + pci_unmap_single(sky2->hw->pdev,
842 + re->mapaddr, sky2->rx_bufsize,
843 + PCI_DMA_FROMDEVICE);
844 + kfree_skb(re->skb);
845 + re->skb = NULL;
846 + }
847 + }
848 +}
849 +
850 +/* Basic MII support */
851 +static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
852 +{
853 + struct mii_ioctl_data *data = if_mii(ifr);
854 + struct sky2_port *sky2 = netdev_priv(dev);
855 + struct sky2_hw *hw = sky2->hw;
856 + int err = -EOPNOTSUPP;
857 +
858 + if (!netif_running(dev))
859 + return -ENODEV; /* Phy still in reset */
860 +
861 + switch(cmd) {
862 + case SIOCGMIIPHY:
863 + data->phy_id = PHY_ADDR_MARV;
864 +
865 + /* fallthru */
866 + case SIOCGMIIREG: {
867 + u16 val = 0;
868 +
869 + down(&sky2->phy_sema);
870 + err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
871 + up(&sky2->phy_sema);
872 +
873 + data->val_out = val;
874 + break;
875 + }
876 +
877 + case SIOCSMIIREG:
878 + if (!capable(CAP_NET_ADMIN))
879 + return -EPERM;
880 +
881 + down(&sky2->phy_sema);
882 + err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
883 + data->val_in);
884 + up(&sky2->phy_sema);
885 + break;
886 + }
887 + return err;
888 +}
889 +
890 +#ifdef SKY2_VLAN_TAG_USED
891 +static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
892 +{
893 + struct sky2_port *sky2 = netdev_priv(dev);
894 + struct sky2_hw *hw = sky2->hw;
895 + u16 port = sky2->port;
896 +
897 + spin_lock_bh(&sky2->tx_lock);
898 +
899 + sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
900 + sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
901 + sky2->vlgrp = grp;
902 +
903 + spin_unlock_bh(&sky2->tx_lock);
904 +}
905 +
906 +static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
907 +{
908 + struct sky2_port *sky2 = netdev_priv(dev);
909 + struct sky2_hw *hw = sky2->hw;
910 + u16 port = sky2->port;
911 +
912 + spin_lock_bh(&sky2->tx_lock);
913 +
914 + sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
915 + sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
916 + if (sky2->vlgrp)
917 + sky2->vlgrp->vlan_devices[vid] = NULL;
918 +
919 + spin_unlock_bh(&sky2->tx_lock);
920 +}
921 +#endif
922 +
923 +/*
924 + * It appears the hardware has a bug in the FIFO logic that
925 + * cause it to hang if the FIFO gets overrun and the receive buffer
926 + * is not aligned. ALso alloc_skb() won't align properly if slab
927 + * debugging is enabled.
928 + */
929 +static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
930 +{
931 + struct sk_buff *skb;
932 +
933 + skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
934 + if (likely(skb)) {
935 + unsigned long p = (unsigned long) skb->data;
936 + skb_reserve(skb,
937 + ((p + RX_SKB_ALIGN - 1) & ~(RX_SKB_ALIGN - 1)) - p);
938 + }
939 +
940 + return skb;
941 +}
942 +
943 +/*
944 + * Allocate and setup receiver buffer pool.
945 + * In case of 64 bit dma, there are 2X as many list elements
946 + * available as ring entries
947 + * and need to reserve one list element so we don't wrap around.
948 + */
949 +static int sky2_rx_start(struct sky2_port *sky2)
950 +{
951 + struct sky2_hw *hw = sky2->hw;
952 + unsigned rxq = rxqaddr[sky2->port];
953 + int i;
954 +
955 + sky2->rx_put = sky2->rx_next = 0;
956 + sky2_qset(hw, rxq);
957 + sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
958 +
959 + rx_set_checksum(sky2);
960 + for (i = 0; i < sky2->rx_pending; i++) {
961 + struct ring_info *re = sky2->rx_ring + i;
962 +
963 + re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
964 + if (!re->skb)
965 + goto nomem;
966 +
967 + re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
968 + sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
969 + sky2_rx_add(sky2, re->mapaddr);
970 + }
971 +
972 + /* Tell chip about available buffers */
973 + sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
974 + sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
975 + return 0;
976 +nomem:
977 + sky2_rx_clean(sky2);
978 + return -ENOMEM;
979 +}
980 +
981 +/* Bring up network interface. */
982 +static int sky2_up(struct net_device *dev)
983 +{
984 + struct sky2_port *sky2 = netdev_priv(dev);
985 + struct sky2_hw *hw = sky2->hw;
986 + unsigned port = sky2->port;
987 + u32 ramsize, rxspace;
988 + int err = -ENOMEM;
989 +
990 + if (netif_msg_ifup(sky2))
991 + printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
992 +
993 + /* must be power of 2 */
994 + sky2->tx_le = pci_alloc_consistent(hw->pdev,
995 + TX_RING_SIZE *
996 + sizeof(struct sky2_tx_le),
997 + &sky2->tx_le_map);
998 + if (!sky2->tx_le)
999 + goto err_out;
1000 +
1001 + sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1002 + GFP_KERNEL);
1003 + if (!sky2->tx_ring)
1004 + goto err_out;
1005 + sky2->tx_prod = sky2->tx_cons = 0;
1006 +
1007 + sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1008 + &sky2->rx_le_map);
1009 + if (!sky2->rx_le)
1010 + goto err_out;
1011 + memset(sky2->rx_le, 0, RX_LE_BYTES);
1012 +
1013 + sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
1014 + GFP_KERNEL);
1015 + if (!sky2->rx_ring)
1016 + goto err_out;
1017 +
1018 + sky2_mac_init(hw, port);
1019 +
1020 + /* Determine available ram buffer space (in 4K blocks).
1021 + * Note: not sure about the FE setting below yet
1022 + */
1023 + if (hw->chip_id == CHIP_ID_YUKON_FE)
1024 + ramsize = 4;
1025 + else
1026 + ramsize = sky2_read8(hw, B2_E_0);
1027 +
1028 + /* Give transmitter one third (rounded up) */
1029 + rxspace = ramsize - (ramsize + 2) / 3;
1030 +
1031 + sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1032 + sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
1033 +
1034 + /* Make sure SyncQ is disabled */
1035 + sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1036 + RB_RST_SET);
1037 +
1038 + sky2_qset(hw, txqaddr[port]);
1039 + if (hw->chip_id == CHIP_ID_YUKON_EC_U)
1040 + sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1041 +
1042 +
1043 + sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1044 + TX_RING_SIZE - 1);
1045 +
1046 + err = sky2_rx_start(sky2);
1047 + if (err)
1048 + goto err_out;
1049 +
1050 + /* Enable interrupts from phy/mac for port */
1051 + hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1052 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
1053 + return 0;
1054 +
1055 +err_out:
1056 + if (sky2->rx_le) {
1057 + pci_free_consistent(hw->pdev, RX_LE_BYTES,
1058 + sky2->rx_le, sky2->rx_le_map);
1059 + sky2->rx_le = NULL;
1060 + }
1061 + if (sky2->tx_le) {
1062 + pci_free_consistent(hw->pdev,
1063 + TX_RING_SIZE * sizeof(struct sky2_tx_le),
1064 + sky2->tx_le, sky2->tx_le_map);
1065 + sky2->tx_le = NULL;
1066 + }
1067 + kfree(sky2->tx_ring);
1068 + kfree(sky2->rx_ring);
1069 +
1070 + sky2->tx_ring = NULL;
1071 + sky2->rx_ring = NULL;
1072 + return err;
1073 +}
1074 +
1075 +/* Modular subtraction in ring */
1076 +static inline int tx_dist(unsigned tail, unsigned head)
1077 +{
1078 + return (head - tail) % TX_RING_SIZE;
1079 +}
1080 +
1081 +/* Number of list elements available for next tx */
1082 +static inline int tx_avail(const struct sky2_port *sky2)
1083 +{
1084 + return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1085 +}
1086 +
1087 +/* Estimate of number of transmit list elements required */
1088 +static unsigned tx_le_req(const struct sk_buff *skb)
1089 +{
1090 + unsigned count;
1091 +
1092 + count = sizeof(dma_addr_t) / sizeof(u32);
1093 + count += skb_shinfo(skb)->nr_frags * count;
1094 +
1095 + if (skb_shinfo(skb)->tso_size)
1096 + ++count;
1097 +
1098 + if (skb->ip_summed == CHECKSUM_HW)
1099 + ++count;
1100 +
1101 + return count;
1102 +}
1103 +
1104 +/*
1105 + * Put one packet in ring for transmit.
1106 + * A single packet can generate multiple list elements, and
1107 + * the number of ring elements will probably be less than the number
1108 + * of list elements used.
1109 + *
1110 + * No BH disabling for tx_lock here (like tg3)
1111 + */
1112 +static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1113 +{
1114 + struct sky2_port *sky2 = netdev_priv(dev);
1115 + struct sky2_hw *hw = sky2->hw;
1116 + struct sky2_tx_le *le = NULL;
1117 + struct tx_ring_info *re;
1118 + unsigned i, len;
1119 + dma_addr_t mapping;
1120 + u32 addr64;
1121 + u16 mss;
1122 + u8 ctrl;
1123 +
1124 + /* No BH disabling for tx_lock here. We are running in BH disabled
1125 + * context and TX reclaim runs via poll inside of a software
1126 + * interrupt, and no related locks in IRQ processing.
1127 + */
1128 + if (!spin_trylock(&sky2->tx_lock))
1129 + return NETDEV_TX_LOCKED;
1130 +
1131 + if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1132 + /* There is a known but harmless race with lockless tx
1133 + * and netif_stop_queue.
1134 + */
1135 + if (!netif_queue_stopped(dev)) {
1136 + netif_stop_queue(dev);
1137 + if (net_ratelimit())
1138 + printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1139 + dev->name);
1140 + }
1141 + spin_unlock(&sky2->tx_lock);
1142 +
1143 + return NETDEV_TX_BUSY;
1144 + }
1145 +
1146 + if (unlikely(netif_msg_tx_queued(sky2)))
1147 + printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1148 + dev->name, sky2->tx_prod, skb->len);
1149 +
1150 + len = skb_headlen(skb);
1151 + mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1152 + addr64 = high32(mapping);
1153 +
1154 + re = sky2->tx_ring + sky2->tx_prod;
1155 +
1156 + /* Send high bits if changed or crosses boundary */
1157 + if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1158 + le = get_tx_le(sky2);
1159 + le->tx.addr = cpu_to_le32(addr64);
1160 + le->ctrl = 0;
1161 + le->opcode = OP_ADDR64 | HW_OWNER;
1162 + sky2->tx_addr64 = high32(mapping + len);
1163 + }
1164 +
1165 + /* Check for TCP Segmentation Offload */
1166 + mss = skb_shinfo(skb)->tso_size;
1167 + if (mss != 0) {
1168 + /* just drop the packet if non-linear expansion fails */
1169 + if (skb_header_cloned(skb) &&
1170 + pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
1171 + dev_kfree_skb_any(skb);
1172 + goto out_unlock;
1173 + }
1174 +
1175 + mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1176 + mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1177 + mss += ETH_HLEN;
1178 + }
1179 +
1180 + if (mss != sky2->tx_last_mss) {
1181 + le = get_tx_le(sky2);
1182 + le->tx.tso.size = cpu_to_le16(mss);
1183 + le->tx.tso.rsvd = 0;
1184 + le->opcode = OP_LRGLEN | HW_OWNER;
1185 + le->ctrl = 0;
1186 + sky2->tx_last_mss = mss;
1187 + }
1188 +
1189 + ctrl = 0;
1190 +#ifdef SKY2_VLAN_TAG_USED
1191 + /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1192 + if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1193 + if (!le) {
1194 + le = get_tx_le(sky2);
1195 + le->tx.addr = 0;
1196 + le->opcode = OP_VLAN|HW_OWNER;
1197 + le->ctrl = 0;
1198 + } else
1199 + le->opcode |= OP_VLAN;
1200 + le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1201 + ctrl |= INS_VLAN;
1202 + }
1203 +#endif
1204 +
1205 + /* Handle TCP checksum offload */
1206 + if (skb->ip_summed == CHECKSUM_HW) {
1207 + u16 hdr = skb->h.raw - skb->data;
1208 + u16 offset = hdr + skb->csum;
1209 +
1210 + ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1211 + if (skb->nh.iph->protocol == IPPROTO_UDP)
1212 + ctrl |= UDPTCP;
1213 +
1214 + le = get_tx_le(sky2);
1215 + le->tx.csum.start = cpu_to_le16(hdr);
1216 + le->tx.csum.offset = cpu_to_le16(offset);
1217 + le->length = 0; /* initial checksum value */
1218 + le->ctrl = 1; /* one packet */
1219 + le->opcode = OP_TCPLISW | HW_OWNER;
1220 + }
1221 +
1222 + le = get_tx_le(sky2);
1223 + le->tx.addr = cpu_to_le32((u32) mapping);
1224 + le->length = cpu_to_le16(len);
1225 + le->ctrl = ctrl;
1226 + le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1227 +
1228 + /* Record the transmit mapping info */
1229 + re->skb = skb;
1230 + pci_unmap_addr_set(re, mapaddr, mapping);
1231 +
1232 + for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1233 + skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1234 + struct tx_ring_info *fre;
1235 +
1236 + mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1237 + frag->size, PCI_DMA_TODEVICE);
1238 + addr64 = high32(mapping);
1239 + if (addr64 != sky2->tx_addr64) {
1240 + le = get_tx_le(sky2);
1241 + le->tx.addr = cpu_to_le32(addr64);
1242 + le->ctrl = 0;
1243 + le->opcode = OP_ADDR64 | HW_OWNER;
1244 + sky2->tx_addr64 = addr64;
1245 + }
1246 +
1247 + le = get_tx_le(sky2);
1248 + le->tx.addr = cpu_to_le32((u32) mapping);
1249 + le->length = cpu_to_le16(frag->size);
1250 + le->ctrl = ctrl;
1251 + le->opcode = OP_BUFFER | HW_OWNER;
1252 +
1253 + fre = sky2->tx_ring
1254 + + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
1255 + pci_unmap_addr_set(fre, mapaddr, mapping);
1256 + }
1257 +
1258 + re->idx = sky2->tx_prod;
1259 + le->ctrl |= EOP;
1260 +
1261 + sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
1262 + &sky2->tx_last_put, TX_RING_SIZE);
1263 +
1264 + if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1265 + netif_stop_queue(dev);
1266 +
1267 +out_unlock:
1268 + spin_unlock(&sky2->tx_lock);
1269 +
1270 + dev->trans_start = jiffies;
1271 + return NETDEV_TX_OK;
1272 +}
1273 +
1274 +/*
1275 + * Free ring elements from starting at tx_cons until "done"
1276 + *
1277 + * NB: the hardware will tell us about partial completion of multi-part
1278 + * buffers; these are deferred until completion.
1279 + */
1280 +static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1281 +{
1282 + struct net_device *dev = sky2->netdev;
1283 + struct pci_dev *pdev = sky2->hw->pdev;
1284 + u16 nxt, put;
1285 + unsigned i;
1286 +
1287 + BUG_ON(done >= TX_RING_SIZE);
1288 +
1289 + if (unlikely(netif_msg_tx_done(sky2)))
1290 + printk(KERN_DEBUG "%s: tx done, up to %u\n",
1291 + dev->name, done);
1292 +
1293 + for (put = sky2->tx_cons; put != done; put = nxt) {
1294 + struct tx_ring_info *re = sky2->tx_ring + put;
1295 + struct sk_buff *skb = re->skb;
1296 +
1297 + nxt = re->idx;
1298 + BUG_ON(nxt >= TX_RING_SIZE);
1299 + prefetch(sky2->tx_ring + nxt);
1300 +
1301 + /* Check for partial status */
1302 + if (tx_dist(put, done) < tx_dist(put, nxt))
1303 + break;
1304 +
1305 + skb = re->skb;
1306 + pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1307 + skb_headlen(skb), PCI_DMA_TODEVICE);
1308 +
1309 + for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1310 + struct tx_ring_info *fre;
1311 + fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE;
1312 + pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
1313 + skb_shinfo(skb)->frags[i].size,
1314 + PCI_DMA_TODEVICE);
1315 + }
1316 +
1317 + dev_kfree_skb_any(skb);
1318 + }
1319 +
1320 + sky2->tx_cons = put;
1321 + if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
1322 + netif_wake_queue(dev);
1323 +}
1324 +
1325 +/* Cleanup all untransmitted buffers, assume transmitter not running */
1326 +static void sky2_tx_clean(struct sky2_port *sky2)
1327 +{
1328 + spin_lock_bh(&sky2->tx_lock);
1329 + sky2_tx_complete(sky2, sky2->tx_prod);
1330 + spin_unlock_bh(&sky2->tx_lock);
1331 +}
1332 +
1333 +/* Network shutdown */
1334 +static int sky2_down(struct net_device *dev)
1335 +{
1336 + struct sky2_port *sky2 = netdev_priv(dev);
1337 + struct sky2_hw *hw = sky2->hw;
1338 + unsigned port = sky2->port;
1339 + u16 ctrl;
1340 +
1341 + /* Never really got started! */
1342 + if (!sky2->tx_le)
1343 + return 0;
1344 +
1345 + if (netif_msg_ifdown(sky2))
1346 + printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1347 +
1348 + /* Stop more packets from being queued */
1349 + netif_stop_queue(dev);
1350 +
1351 + /* Disable port IRQ */
1352 + local_irq_disable();
1353 + hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1354 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
1355 + local_irq_enable();
1356 +
1357 + flush_scheduled_work();
1358 +
1359 + sky2_phy_reset(hw, port);
1360 +
1361 + /* Stop transmitter */
1362 + sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1363 + sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1364 +
1365 + sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1366 + RB_RST_SET | RB_DIS_OP_MD);
1367 +
1368 + ctrl = gma_read16(hw, port, GM_GP_CTRL);
1369 + ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1370 + gma_write16(hw, port, GM_GP_CTRL, ctrl);
1371 +
1372 + sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1373 +
1374 + /* Workaround shared GMAC reset */
1375 + if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1376 + && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1377 + sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1378 +
1379 + /* Disable Force Sync bit and Enable Alloc bit */
1380 + sky2_write8(hw, SK_REG(port, TXA_CTRL),
1381 + TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1382 +
1383 + /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1384 + sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1385 + sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1386 +
1387 + /* Reset the PCI FIFO of the async Tx queue */
1388 + sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1389 + BMU_RST_SET | BMU_FIFO_RST);
1390 +
1391 + /* Reset the Tx prefetch units */
1392 + sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1393 + PREF_UNIT_RST_SET);
1394 +
1395 + sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1396 +
1397 + sky2_rx_stop(sky2);
1398 +
1399 + sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1400 + sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1401 +
1402 + /* turn off LED's */
1403 + sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1404 +
1405 + synchronize_irq(hw->pdev->irq);
1406 +
1407 + sky2_tx_clean(sky2);
1408 + sky2_rx_clean(sky2);
1409 +
1410 + pci_free_consistent(hw->pdev, RX_LE_BYTES,
1411 + sky2->rx_le, sky2->rx_le_map);
1412 + kfree(sky2->rx_ring);
1413 +
1414 + pci_free_consistent(hw->pdev,
1415 + TX_RING_SIZE * sizeof(struct sky2_tx_le),
1416 + sky2->tx_le, sky2->tx_le_map);
1417 + kfree(sky2->tx_ring);
1418 +
1419 + sky2->tx_le = NULL;
1420 + sky2->rx_le = NULL;
1421 +
1422 + sky2->rx_ring = NULL;
1423 + sky2->tx_ring = NULL;
1424 +
1425 + return 0;
1426 +}
1427 +
1428 +static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1429 +{
1430 + if (!hw->copper)
1431 + return SPEED_1000;
1432 +
1433 + if (hw->chip_id == CHIP_ID_YUKON_FE)
1434 + return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1435 +
1436 + switch (aux & PHY_M_PS_SPEED_MSK) {
1437 + case PHY_M_PS_SPEED_1000:
1438 + return SPEED_1000;
1439 + case PHY_M_PS_SPEED_100:
1440 + return SPEED_100;
1441 + default:
1442 + return SPEED_10;
1443 + }
1444 +}
1445 +
1446 +static void sky2_link_up(struct sky2_port *sky2)
1447 +{
1448 + struct sky2_hw *hw = sky2->hw;
1449 + unsigned port = sky2->port;
1450 + u16 reg;
1451 +
1452 + /* Enable Transmit FIFO Underrun */
1453 + sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1454 +
1455 + reg = gma_read16(hw, port, GM_GP_CTRL);
1456 + if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1457 + reg |= GM_GPCR_DUP_FULL;
1458 +
1459 + /* enable Rx/Tx */
1460 + reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1461 + gma_write16(hw, port, GM_GP_CTRL, reg);
1462 + gma_read16(hw, port, GM_GP_CTRL);
1463 +
1464 + gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1465 +
1466 + netif_carrier_on(sky2->netdev);
1467 + netif_wake_queue(sky2->netdev);
1468 +
1469 + /* Turn on link LED */
1470 + sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1471 + LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1472 +
1473 + if (hw->chip_id == CHIP_ID_YUKON_XL) {
1474 + u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1475 +
1476 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1477 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1478 + PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1479 + SPEED_10 ? 7 : 0) |
1480 + PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1481 + SPEED_100 ? 7 : 0) |
1482 + PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1483 + SPEED_1000 ? 7 : 0));
1484 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1485 + }
1486 +
1487 + if (netif_msg_link(sky2))
1488 + printk(KERN_INFO PFX
1489 + "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1490 + sky2->netdev->name, sky2->speed,
1491 + sky2->duplex == DUPLEX_FULL ? "full" : "half",
1492 + (sky2->tx_pause && sky2->rx_pause) ? "both" :
1493 + sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1494 +}
1495 +
1496 +static void sky2_link_down(struct sky2_port *sky2)
1497 +{
1498 + struct sky2_hw *hw = sky2->hw;
1499 + unsigned port = sky2->port;
1500 + u16 reg;
1501 +
1502 + gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1503 +
1504 + reg = gma_read16(hw, port, GM_GP_CTRL);
1505 + reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1506 + gma_write16(hw, port, GM_GP_CTRL, reg);
1507 + gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1508 +
1509 + if (sky2->rx_pause && !sky2->tx_pause) {
1510 + /* restore Asymmetric Pause bit */
1511 + gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1512 + gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1513 + | PHY_M_AN_ASP);
1514 + }
1515 +
1516 + netif_carrier_off(sky2->netdev);
1517 + netif_stop_queue(sky2->netdev);
1518 +
1519 + /* Turn on link LED */
1520 + sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1521 +
1522 + if (netif_msg_link(sky2))
1523 + printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1524 + sky2_phy_init(hw, port);
1525 +}
1526 +
1527 +static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1528 +{
1529 + struct sky2_hw *hw = sky2->hw;
1530 + unsigned port = sky2->port;
1531 + u16 lpa;
1532 +
1533 + lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1534 +
1535 + if (lpa & PHY_M_AN_RF) {
1536 + printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1537 + return -1;
1538 + }
1539 +
1540 + if (hw->chip_id != CHIP_ID_YUKON_FE &&
1541 + gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1542 + printk(KERN_ERR PFX "%s: master/slave fault",
1543 + sky2->netdev->name);
1544 + return -1;
1545 + }
1546 +
1547 + if (!(aux & PHY_M_PS_SPDUP_RES)) {
1548 + printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1549 + sky2->netdev->name);
1550 + return -1;
1551 + }
1552 +
1553 + sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1554 +
1555 + sky2->speed = sky2_phy_speed(hw, aux);
1556 +
1557 + /* Pause bits are offset (9..8) */
1558 + if (hw->chip_id == CHIP_ID_YUKON_XL)
1559 + aux >>= 6;
1560 +
1561 + sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1562 + sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1563 +
1564 + if ((sky2->tx_pause || sky2->rx_pause)
1565 + && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1566 + sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1567 + else
1568 + sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1569 +
1570 + return 0;
1571 +}
1572 +
1573 +/*
1574 + * Interrupt from PHY are handled outside of interrupt context
1575 + * because accessing phy registers requires spin wait which might
1576 + * cause excess interrupt latency.
1577 + */
1578 +static void sky2_phy_task(void *arg)
1579 +{
1580 + struct sky2_port *sky2 = arg;
1581 + struct sky2_hw *hw = sky2->hw;
1582 + u16 istatus, phystat;
1583 +
1584 + down(&sky2->phy_sema);
1585 + istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1586 + phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
1587 +
1588 + if (netif_msg_intr(sky2))
1589 + printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1590 + sky2->netdev->name, istatus, phystat);
1591 +
1592 + if (istatus & PHY_M_IS_AN_COMPL) {
1593 + if (sky2_autoneg_done(sky2, phystat) == 0)
1594 + sky2_link_up(sky2);
1595 + goto out;
1596 + }
1597 +
1598 + if (istatus & PHY_M_IS_LSP_CHANGE)
1599 + sky2->speed = sky2_phy_speed(hw, phystat);
1600 +
1601 + if (istatus & PHY_M_IS_DUP_CHANGE)
1602 + sky2->duplex =
1603 + (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1604 +
1605 + if (istatus & PHY_M_IS_LST_CHANGE) {
1606 + if (phystat & PHY_M_PS_LINK_UP)
1607 + sky2_link_up(sky2);
1608 + else
1609 + sky2_link_down(sky2);
1610 + }
1611 +out:
1612 + up(&sky2->phy_sema);
1613 +
1614 + local_irq_disable();
1615 + hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
1616 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
1617 + local_irq_enable();
1618 +}
1619 +
1620 +
1621 +/* Transmit timeout is only called if we are running, carries is up
1622 + * and tx queue is full (stopped).
1623 + */
1624 +static void sky2_tx_timeout(struct net_device *dev)
1625 +{
1626 + struct sky2_port *sky2 = netdev_priv(dev);
1627 + struct sky2_hw *hw = sky2->hw;
1628 + unsigned txq = txqaddr[sky2->port];
1629 + u16 ridx;
1630 +
1631 + /* Maybe we just missed an status interrupt */
1632 + spin_lock(&sky2->tx_lock);
1633 + ridx = sky2_read16(hw,
1634 + sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1635 + sky2_tx_complete(sky2, ridx);
1636 + spin_unlock(&sky2->tx_lock);
1637 +
1638 + if (!netif_queue_stopped(dev)) {
1639 + if (net_ratelimit())
1640 + pr_info(PFX "transmit interrupt missed? recovered\n");
1641 + return;
1642 + }
1643 +
1644 + if (netif_msg_timer(sky2))
1645 + printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1646 +
1647 + sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1648 + sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1649 +
1650 + sky2_tx_clean(sky2);
1651 +
1652 + sky2_qset(hw, txq);
1653 + sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1654 +}
1655 +
1656 +
1657 +#define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
1658 +/* Want receive buffer size to be multiple of 64 bits, and incl room for vlan */
1659 +static inline unsigned sky2_buf_size(int mtu)
1660 +{
1661 + return roundup(mtu + ETH_HLEN + 4, 8);
1662 +}
1663 +
1664 +static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1665 +{
1666 + struct sky2_port *sky2 = netdev_priv(dev);
1667 + struct sky2_hw *hw = sky2->hw;
1668 + int err;
1669 + u16 ctl, mode;
1670 +
1671 + if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1672 + return -EINVAL;
1673 +
1674 + if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1675 + return -EINVAL;
1676 +
1677 + if (!netif_running(dev)) {
1678 + dev->mtu = new_mtu;
1679 + return 0;
1680 + }
1681 +
1682 + sky2_write32(hw, B0_IMSK, 0);
1683 +
1684 + dev->trans_start = jiffies; /* prevent tx timeout */
1685 + netif_stop_queue(dev);
1686 + netif_poll_disable(hw->dev[0]);
1687 +
1688 + ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1689 + gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1690 + sky2_rx_stop(sky2);
1691 + sky2_rx_clean(sky2);
1692 +
1693 + dev->mtu = new_mtu;
1694 + sky2->rx_bufsize = sky2_buf_size(new_mtu);
1695 + mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1696 + GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1697 +
1698 + if (dev->mtu > ETH_DATA_LEN)
1699 + mode |= GM_SMOD_JUMBO_ENA;
1700 +
1701 + gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1702 +
1703 + sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1704 +
1705 + err = sky2_rx_start(sky2);
1706 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
1707 +
1708 + if (err)
1709 + dev_close(dev);
1710 + else {
1711 + gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1712 +
1713 + netif_poll_enable(hw->dev[0]);
1714 + netif_wake_queue(dev);
1715 + }
1716 +
1717 + return err;
1718 +}
1719 +
1720 +/*
1721 + * Receive one packet.
1722 + * For small packets or errors, just reuse existing skb.
1723 + * For larger packets, get new buffer.
1724 + */
1725 +static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1726 + u16 length, u32 status)
1727 +{
1728 + struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1729 + struct sk_buff *skb = NULL;
1730 +
1731 + if (unlikely(netif_msg_rx_status(sky2)))
1732 + printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1733 + sky2->netdev->name, sky2->rx_next, status, length);
1734 +
1735 + sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1736 + prefetch(sky2->rx_ring + sky2->rx_next);
1737 +
1738 + if (status & GMR_FS_ANY_ERR)
1739 + goto error;
1740 +
1741 + if (!(status & GMR_FS_RX_OK))
1742 + goto resubmit;
1743 +
1744 + if ((status >> 16) != length || length > sky2->rx_bufsize)
1745 + goto oversize;
1746 +
1747 + if (length < copybreak) {
1748 + skb = alloc_skb(length + 2, GFP_ATOMIC);
1749 + if (!skb)
1750 + goto resubmit;
1751 +
1752 + skb_reserve(skb, 2);
1753 + pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1754 + length, PCI_DMA_FROMDEVICE);
1755 + memcpy(skb->data, re->skb->data, length);
1756 + skb->ip_summed = re->skb->ip_summed;
1757 + skb->csum = re->skb->csum;
1758 + pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1759 + length, PCI_DMA_FROMDEVICE);
1760 + } else {
1761 + struct sk_buff *nskb;
1762 +
1763 + nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
1764 + if (!nskb)
1765 + goto resubmit;
1766 +
1767 + skb = re->skb;
1768 + re->skb = nskb;
1769 + pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1770 + sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1771 + prefetch(skb->data);
1772 +
1773 + re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1774 + sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1775 + }
1776 +
1777 + skb_put(skb, length);
1778 +resubmit:
1779 + re->skb->ip_summed = CHECKSUM_NONE;
1780 + sky2_rx_add(sky2, re->mapaddr);
1781 +
1782 + /* Tell receiver about new buffers. */
1783 + sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
1784 + &sky2->rx_last_put, RX_LE_SIZE);
1785 +
1786 + return skb;
1787 +
1788 +oversize:
1789 + ++sky2->net_stats.rx_over_errors;
1790 + goto resubmit;
1791 +
1792 +error:
1793 + ++sky2->net_stats.rx_errors;
1794 +
1795 + if (netif_msg_rx_err(sky2) && net_ratelimit())
1796 + printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1797 + sky2->netdev->name, status, length);
1798 +
1799 + if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1800 + sky2->net_stats.rx_length_errors++;
1801 + if (status & GMR_FS_FRAGMENT)
1802 + sky2->net_stats.rx_frame_errors++;
1803 + if (status & GMR_FS_CRC_ERR)
1804 + sky2->net_stats.rx_crc_errors++;
1805 + if (status & GMR_FS_RX_FF_OV)
1806 + sky2->net_stats.rx_fifo_errors++;
1807 +
1808 + goto resubmit;
1809 +}
1810 +
1811 +/*
1812 + * Check for transmit complete
1813 + */
1814 +#define TX_NO_STATUS 0xffff
1815 +
1816 +static void sky2_tx_check(struct sky2_hw *hw, int port, u16 last)
1817 +{
1818 + if (last != TX_NO_STATUS) {
1819 + struct net_device *dev = hw->dev[port];
1820 + if (dev && netif_running(dev)) {
1821 + struct sky2_port *sky2 = netdev_priv(dev);
1822 +
1823 + spin_lock(&sky2->tx_lock);
1824 + sky2_tx_complete(sky2, last);
1825 + spin_unlock(&sky2->tx_lock);
1826 + }
1827 + }
1828 +}
1829 +
1830 +/*
1831 + * Both ports share the same status interrupt, therefore there is only
1832 + * one poll routine.
1833 + */
1834 +static int sky2_poll(struct net_device *dev0, int *budget)
1835 +{
1836 + struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1837 + unsigned int to_do = min(dev0->quota, *budget);
1838 + unsigned int work_done = 0;
1839 + u16 hwidx;
1840 + u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS };
1841 +
1842 + hwidx = sky2_read16(hw, STAT_PUT_IDX);
1843 + BUG_ON(hwidx >= STATUS_RING_SIZE);
1844 + rmb();
1845 +
1846 + while (hwidx != hw->st_idx) {
1847 + struct sky2_status_le *le = hw->st_le + hw->st_idx;
1848 + struct net_device *dev;
1849 + struct sky2_port *sky2;
1850 + struct sk_buff *skb;
1851 + u32 status;
1852 + u16 length;
1853 +
1854 + le = hw->st_le + hw->st_idx;
1855 + hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
1856 + prefetch(hw->st_le + hw->st_idx);
1857 +
1858 + BUG_ON(le->link >= 2);
1859 + dev = hw->dev[le->link];
1860 + if (dev == NULL || !netif_running(dev))
1861 + continue;
1862 +
1863 + sky2 = netdev_priv(dev);
1864 + status = le32_to_cpu(le->status);
1865 + length = le16_to_cpu(le->length);
1866 +
1867 + switch (le->opcode & ~HW_OWNER) {
1868 + case OP_RXSTAT:
1869 + skb = sky2_receive(sky2, length, status);
1870 + if (!skb)
1871 + break;
1872 +
1873 + skb->dev = dev;
1874 + skb->protocol = eth_type_trans(skb, dev);
1875 + dev->last_rx = jiffies;
1876 +
1877 +#ifdef SKY2_VLAN_TAG_USED
1878 + if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1879 + vlan_hwaccel_receive_skb(skb,
1880 + sky2->vlgrp,
1881 + be16_to_cpu(sky2->rx_tag));
1882 + } else
1883 +#endif
1884 + netif_receive_skb(skb);
1885 +
1886 + if (++work_done >= to_do)
1887 + goto exit_loop;
1888 + break;
1889 +
1890 +#ifdef SKY2_VLAN_TAG_USED
1891 + case OP_RXVLAN:
1892 + sky2->rx_tag = length;
1893 + break;
1894 +
1895 + case OP_RXCHKSVLAN:
1896 + sky2->rx_tag = length;
1897 + /* fall through */
1898 +#endif
1899 + case OP_RXCHKS:
1900 + skb = sky2->rx_ring[sky2->rx_next].skb;
1901 + skb->ip_summed = CHECKSUM_HW;
1902 + skb->csum = le16_to_cpu(status);
1903 + break;
1904 +
1905 + case OP_TXINDEXLE:
1906 + /* TX index reports status for both ports */
1907 + tx_done[0] = status & 0xffff;
1908 + tx_done[1] = ((status >> 24) & 0xff)
1909 + | (u16)(length & 0xf) << 8;
1910 + break;
1911 +
1912 + default:
1913 + if (net_ratelimit())
1914 + printk(KERN_WARNING PFX
1915 + "unknown status opcode 0x%x\n", le->opcode);
1916 + break;
1917 + }
1918 + }
1919 +
1920 +exit_loop:
1921 + sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1922 +
1923 + sky2_tx_check(hw, 0, tx_done[0]);
1924 + sky2_tx_check(hw, 1, tx_done[1]);
1925 +
1926 + if (sky2_read16(hw, STAT_PUT_IDX) == hw->st_idx) {
1927 + /* need to restart TX timer */
1928 + if (is_ec_a1(hw)) {
1929 + sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1930 + sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1931 + }
1932 +
1933 + netif_rx_complete(dev0);
1934 + hw->intr_mask |= Y2_IS_STAT_BMU;
1935 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
1936 + return 0;
1937 + } else {
1938 + *budget -= work_done;
1939 + dev0->quota -= work_done;
1940 + return 1;
1941 + }
1942 +}
1943 +
1944 +static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1945 +{
1946 + struct net_device *dev = hw->dev[port];
1947 +
1948 + if (net_ratelimit())
1949 + printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1950 + dev->name, status);
1951 +
1952 + if (status & Y2_IS_PAR_RD1) {
1953 + if (net_ratelimit())
1954 + printk(KERN_ERR PFX "%s: ram data read parity error\n",
1955 + dev->name);
1956 + /* Clear IRQ */
1957 + sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1958 + }
1959 +
1960 + if (status & Y2_IS_PAR_WR1) {
1961 + if (net_ratelimit())
1962 + printk(KERN_ERR PFX "%s: ram data write parity error\n",
1963 + dev->name);
1964 +
1965 + sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1966 + }
1967 +
1968 + if (status & Y2_IS_PAR_MAC1) {
1969 + if (net_ratelimit())
1970 + printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
1971 + sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1972 + }
1973 +
1974 + if (status & Y2_IS_PAR_RX1) {
1975 + if (net_ratelimit())
1976 + printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
1977 + sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1978 + }
1979 +
1980 + if (status & Y2_IS_TCP_TXA1) {
1981 + if (net_ratelimit())
1982 + printk(KERN_ERR PFX "%s: TCP segmentation error\n",
1983 + dev->name);
1984 + sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1985 + }
1986 +}
1987 +
1988 +static void sky2_hw_intr(struct sky2_hw *hw)
1989 +{
1990 + u32 status = sky2_read32(hw, B0_HWE_ISRC);
1991 +
1992 + if (status & Y2_IS_TIST_OV)
1993 + sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1994 +
1995 + if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
1996 + u16 pci_err;
1997 +
1998 + pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
1999 + if (net_ratelimit())
2000 + printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2001 + pci_name(hw->pdev), pci_err);
2002 +
2003 + sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2004 + pci_write_config_word(hw->pdev, PCI_STATUS,
2005 + pci_err | PCI_STATUS_ERROR_BITS);
2006 + sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2007 + }
2008 +
2009 + if (status & Y2_IS_PCI_EXP) {
2010 + /* PCI-Express uncorrectable Error occurred */
2011 + u32 pex_err;
2012 +
2013 + pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
2014 +
2015 + if (net_ratelimit())
2016 + printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2017 + pci_name(hw->pdev), pex_err);
2018 +
2019 + /* clear the interrupt */
2020 + sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2021 + pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
2022 + 0xffffffffUL);
2023 + sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2024 +
2025 + if (pex_err & PEX_FATAL_ERRORS) {
2026 + u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2027 + hwmsk &= ~Y2_IS_PCI_EXP;
2028 + sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2029 + }
2030 + }
2031 +
2032 + if (status & Y2_HWE_L1_MASK)
2033 + sky2_hw_error(hw, 0, status);
2034 + status >>= 8;
2035 + if (status & Y2_HWE_L1_MASK)
2036 + sky2_hw_error(hw, 1, status);
2037 +}
2038 +
2039 +static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2040 +{
2041 + struct net_device *dev = hw->dev[port];
2042 + struct sky2_port *sky2 = netdev_priv(dev);
2043 + u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2044 +
2045 + if (netif_msg_intr(sky2))
2046 + printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2047 + dev->name, status);
2048 +
2049 + if (status & GM_IS_RX_FF_OR) {
2050 + ++sky2->net_stats.rx_fifo_errors;
2051 + sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2052 + }
2053 +
2054 + if (status & GM_IS_TX_FF_UR) {
2055 + ++sky2->net_stats.tx_fifo_errors;
2056 + sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2057 + }
2058 +}
2059 +
2060 +static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2061 +{
2062 + struct net_device *dev = hw->dev[port];
2063 + struct sky2_port *sky2 = netdev_priv(dev);
2064 +
2065 + hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
2066 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
2067 + schedule_work(&sky2->phy_task);
2068 +}
2069 +
2070 +static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2071 +{
2072 + struct sky2_hw *hw = dev_id;
2073 + struct net_device *dev0 = hw->dev[0];
2074 + u32 status;
2075 +
2076 + status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2077 + if (status == 0 || status == ~0)
2078 + return IRQ_NONE;
2079 +
2080 + if (status & Y2_IS_HW_ERR)
2081 + sky2_hw_intr(hw);
2082 +
2083 + /* Do NAPI for Rx and Tx status */
2084 + if (status & Y2_IS_STAT_BMU) {
2085 + hw->intr_mask &= ~Y2_IS_STAT_BMU;
2086 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
2087 +
2088 + if (likely(__netif_rx_schedule_prep(dev0))) {
2089 + prefetch(&hw->st_le[hw->st_idx]);
2090 + __netif_rx_schedule(dev0);
2091 + }
2092 + }
2093 +
2094 + if (status & Y2_IS_IRQ_PHY1)
2095 + sky2_phy_intr(hw, 0);
2096 +
2097 + if (status & Y2_IS_IRQ_PHY2)
2098 + sky2_phy_intr(hw, 1);
2099 +
2100 + if (status & Y2_IS_IRQ_MAC1)
2101 + sky2_mac_intr(hw, 0);
2102 +
2103 + if (status & Y2_IS_IRQ_MAC2)
2104 + sky2_mac_intr(hw, 1);
2105 +
2106 + sky2_write32(hw, B0_Y2_SP_ICR, 2);
2107 +
2108 + sky2_read32(hw, B0_IMSK);
2109 +
2110 + return IRQ_HANDLED;
2111 +}
2112 +
2113 +#ifdef CONFIG_NET_POLL_CONTROLLER
2114 +static void sky2_netpoll(struct net_device *dev)
2115 +{
2116 + struct sky2_port *sky2 = netdev_priv(dev);
2117 +
2118 + sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
2119 +}
2120 +#endif
2121 +
2122 +/* Chip internal frequency for clock calculations */
2123 +static inline u32 sky2_mhz(const struct sky2_hw *hw)
2124 +{
2125 + switch (hw->chip_id) {
2126 + case CHIP_ID_YUKON_EC:
2127 + case CHIP_ID_YUKON_EC_U:
2128 + return 125; /* 125 Mhz */
2129 + case CHIP_ID_YUKON_FE:
2130 + return 100; /* 100 Mhz */
2131 + default: /* YUKON_XL */
2132 + return 156; /* 156 Mhz */
2133 + }
2134 +}
2135 +
2136 +static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2137 +{
2138 + return sky2_mhz(hw) * us;
2139 +}
2140 +
2141 +static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2142 +{
2143 + return clk / sky2_mhz(hw);
2144 +}
2145 +
2146 +
2147 +static int sky2_reset(struct sky2_hw *hw)
2148 +{
2149 + u32 ctst;
2150 + u16 status;
2151 + u8 t8, pmd_type;
2152 + int i;
2153 +
2154 + ctst = sky2_read32(hw, B0_CTST);
2155 +
2156 + sky2_write8(hw, B0_CTST, CS_RST_CLR);
2157 + hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2158 + if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2159 + printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2160 + pci_name(hw->pdev), hw->chip_id);
2161 + return -EOPNOTSUPP;
2162 + }
2163 +
2164 + /* ring for status responses */
2165 + hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
2166 + &hw->st_dma);
2167 + if (!hw->st_le)
2168 + return -ENOMEM;
2169 +
2170 + /* disable ASF */
2171 + if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2172 + sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2173 + sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2174 + }
2175 +
2176 + /* do a SW reset */
2177 + sky2_write8(hw, B0_CTST, CS_RST_SET);
2178 + sky2_write8(hw, B0_CTST, CS_RST_CLR);
2179 +
2180 + /* clear PCI errors, if any */
2181 + pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2182 + sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2183 + pci_write_config_word(hw->pdev, PCI_STATUS,
2184 + status | PCI_STATUS_ERROR_BITS);
2185 +
2186 + sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2187 +
2188 + /* clear any PEX errors */
2189 + if (is_pciex(hw)) {
2190 + u16 lstat;
2191 + pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
2192 + 0xffffffffUL);
2193 + pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat);
2194 + }
2195 +
2196 + pmd_type = sky2_read8(hw, B2_PMD_TYP);
2197 + hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2198 +
2199 + hw->ports = 1;
2200 + t8 = sky2_read8(hw, B2_Y2_HW_RES);
2201 + if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2202 + if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2203 + ++hw->ports;
2204 + }
2205 + hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2206 +
2207 + sky2_set_power_state(hw, PCI_D0);
2208 +
2209 + for (i = 0; i < hw->ports; i++) {
2210 + sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2211 + sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2212 + }
2213 +
2214 + sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2215 +
2216 + /* Clear I2C IRQ noise */
2217 + sky2_write32(hw, B2_I2C_IRQ, 1);
2218 +
2219 + /* turn off hardware timer (unused) */
2220 + sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2221 + sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2222 +
2223 + sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2224 +
2225 + /* Turn off descriptor polling */
2226 + sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2227 +
2228 + /* Turn off receive timestamp */
2229 + sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2230 + sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2231 +
2232 + /* enable the Tx Arbiters */
2233 + for (i = 0; i < hw->ports; i++)
2234 + sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2235 +
2236 + /* Initialize ram interface */
2237 + for (i = 0; i < hw->ports; i++) {
2238 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2239 +
2240 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2241 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2242 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2243 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2244 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2245 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2246 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2247 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2248 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2249 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2250 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2251 + sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2252 + }
2253 +
2254 + sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2255 +
2256 + for (i = 0; i < hw->ports; i++)
2257 + sky2_phy_reset(hw, i);
2258 +
2259 + memset(hw->st_le, 0, STATUS_LE_BYTES);
2260 + hw->st_idx = 0;
2261 +
2262 + sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2263 + sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2264 +
2265 + sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2266 + sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2267 +
2268 + /* Set the list last index */
2269 + sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2270 +
2271 + /* These status setup values are copied from SysKonnect's driver */
2272 + if (is_ec_a1(hw)) {
2273 + /* WA for dev. #4.3 */
2274 + sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
2275 +
2276 + /* set Status-FIFO watermark */
2277 + sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
2278 +
2279 + /* set Status-FIFO ISR watermark */
2280 + sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
2281 + sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 10000));
2282 + } else {
2283 + sky2_write16(hw, STAT_TX_IDX_TH, 10);
2284 + sky2_write8(hw, STAT_FIFO_WM, 16);
2285 +
2286 + /* set Status-FIFO ISR watermark */
2287 + if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2288 + sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2289 + else
2290 + sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2291 +
2292 + sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2293 + sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2294 + sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2295 + }
2296 +
2297 + /* enable status unit */
2298 + sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2299 +
2300 + sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2301 + sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2302 + sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2303 +
2304 + return 0;
2305 +}
2306 +
2307 +static u32 sky2_supported_modes(const struct sky2_hw *hw)
2308 +{
2309 + u32 modes;
2310 + if (hw->copper) {
2311 + modes = SUPPORTED_10baseT_Half
2312 + | SUPPORTED_10baseT_Full
2313 + | SUPPORTED_100baseT_Half
2314 + | SUPPORTED_100baseT_Full
2315 + | SUPPORTED_Autoneg | SUPPORTED_TP;
2316 +
2317 + if (hw->chip_id != CHIP_ID_YUKON_FE)
2318 + modes |= SUPPORTED_1000baseT_Half
2319 + | SUPPORTED_1000baseT_Full;
2320 + } else
2321 + modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
2322 + | SUPPORTED_Autoneg;
2323 + return modes;
2324 +}
2325 +
2326 +static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2327 +{
2328 + struct sky2_port *sky2 = netdev_priv(dev);
2329 + struct sky2_hw *hw = sky2->hw;
2330 +
2331 + ecmd->transceiver = XCVR_INTERNAL;
2332 + ecmd->supported = sky2_supported_modes(hw);
2333 + ecmd->phy_address = PHY_ADDR_MARV;
2334 + if (hw->copper) {
2335 + ecmd->supported = SUPPORTED_10baseT_Half
2336 + | SUPPORTED_10baseT_Full
2337 + | SUPPORTED_100baseT_Half
2338 + | SUPPORTED_100baseT_Full
2339 + | SUPPORTED_1000baseT_Half
2340 + | SUPPORTED_1000baseT_Full
2341 + | SUPPORTED_Autoneg | SUPPORTED_TP;
2342 + ecmd->port = PORT_TP;
2343 + } else
2344 + ecmd->port = PORT_FIBRE;
2345 +
2346 + ecmd->advertising = sky2->advertising;
2347 + ecmd->autoneg = sky2->autoneg;
2348 + ecmd->speed = sky2->speed;
2349 + ecmd->duplex = sky2->duplex;
2350 + return 0;
2351 +}
2352 +
2353 +static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2354 +{
2355 + struct sky2_port *sky2 = netdev_priv(dev);
2356 + const struct sky2_hw *hw = sky2->hw;
2357 + u32 supported = sky2_supported_modes(hw);
2358 +
2359 + if (ecmd->autoneg == AUTONEG_ENABLE) {
2360 + ecmd->advertising = supported;
2361 + sky2->duplex = -1;
2362 + sky2->speed = -1;
2363 + } else {
2364 + u32 setting;
2365 +
2366 + switch (ecmd->speed) {
2367 + case SPEED_1000:
2368 + if (ecmd->duplex == DUPLEX_FULL)
2369 + setting = SUPPORTED_1000baseT_Full;
2370 + else if (ecmd->duplex == DUPLEX_HALF)
2371 + setting = SUPPORTED_1000baseT_Half;
2372 + else
2373 + return -EINVAL;
2374 + break;
2375 + case SPEED_100:
2376 + if (ecmd->duplex == DUPLEX_FULL)
2377 + setting = SUPPORTED_100baseT_Full;
2378 + else if (ecmd->duplex == DUPLEX_HALF)
2379 + setting = SUPPORTED_100baseT_Half;
2380 + else
2381 + return -EINVAL;
2382 + break;
2383 +
2384 + case SPEED_10:
2385 + if (ecmd->duplex == DUPLEX_FULL)
2386 + setting = SUPPORTED_10baseT_Full;
2387 + else if (ecmd->duplex == DUPLEX_HALF)
2388 + setting = SUPPORTED_10baseT_Half;
2389 + else
2390 + return -EINVAL;
2391 + break;
2392 + default:
2393 + return -EINVAL;
2394 + }
2395 +
2396 + if ((setting & supported) == 0)
2397 + return -EINVAL;
2398 +
2399 + sky2->speed = ecmd->speed;
2400 + sky2->duplex = ecmd->duplex;
2401 + }
2402 +
2403 + sky2->autoneg = ecmd->autoneg;
2404 + sky2->advertising = ecmd->advertising;
2405 +
2406 + if (netif_running(dev))
2407 + sky2_phy_reinit(sky2);
2408 +
2409 + return 0;
2410 +}
2411 +
2412 +static void sky2_get_drvinfo(struct net_device *dev,
2413 + struct ethtool_drvinfo *info)
2414 +{
2415 + struct sky2_port *sky2 = netdev_priv(dev);
2416 +
2417 + strcpy(info->driver, DRV_NAME);
2418 + strcpy(info->version, DRV_VERSION);
2419 + strcpy(info->fw_version, "N/A");
2420 + strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2421 +}
2422 +
2423 +static const struct sky2_stat {
2424 + char name[ETH_GSTRING_LEN];
2425 + u16 offset;
2426 +} sky2_stats[] = {
2427 + { "tx_bytes", GM_TXO_OK_HI },
2428 + { "rx_bytes", GM_RXO_OK_HI },
2429 + { "tx_broadcast", GM_TXF_BC_OK },
2430 + { "rx_broadcast", GM_RXF_BC_OK },
2431 + { "tx_multicast", GM_TXF_MC_OK },
2432 + { "rx_multicast", GM_RXF_MC_OK },
2433 + { "tx_unicast", GM_TXF_UC_OK },
2434 + { "rx_unicast", GM_RXF_UC_OK },
2435 + { "tx_mac_pause", GM_TXF_MPAUSE },
2436 + { "rx_mac_pause", GM_RXF_MPAUSE },
2437 + { "collisions", GM_TXF_SNG_COL },
2438 + { "late_collision",GM_TXF_LAT_COL },
2439 + { "aborted", GM_TXF_ABO_COL },
2440 + { "multi_collisions", GM_TXF_MUL_COL },
2441 + { "fifo_underrun", GM_TXE_FIFO_UR },
2442 + { "fifo_overflow", GM_RXE_FIFO_OV },
2443 + { "rx_toolong", GM_RXF_LNG_ERR },
2444 + { "rx_jabber", GM_RXF_JAB_PKT },
2445 + { "rx_runt", GM_RXE_FRAG },
2446 + { "rx_too_long", GM_RXF_LNG_ERR },
2447 + { "rx_fcs_error", GM_RXF_FCS_ERR },
2448 +};
2449 +
2450 +static u32 sky2_get_rx_csum(struct net_device *dev)
2451 +{
2452 + struct sky2_port *sky2 = netdev_priv(dev);
2453 +
2454 + return sky2->rx_csum;
2455 +}
2456 +
2457 +static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2458 +{
2459 + struct sky2_port *sky2 = netdev_priv(dev);
2460 +
2461 + sky2->rx_csum = data;
2462 +
2463 + sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2464 + data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2465 +
2466 + return 0;
2467 +}
2468 +
2469 +static u32 sky2_get_msglevel(struct net_device *netdev)
2470 +{
2471 + struct sky2_port *sky2 = netdev_priv(netdev);
2472 + return sky2->msg_enable;
2473 +}
2474 +
2475 +static int sky2_nway_reset(struct net_device *dev)
2476 +{
2477 + struct sky2_port *sky2 = netdev_priv(dev);
2478 +
2479 + if (sky2->autoneg != AUTONEG_ENABLE)
2480 + return -EINVAL;
2481 +
2482 + sky2_phy_reinit(sky2);
2483 +
2484 + return 0;
2485 +}
2486 +
2487 +static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2488 +{
2489 + struct sky2_hw *hw = sky2->hw;
2490 + unsigned port = sky2->port;
2491 + int i;
2492 +
2493 + data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2494 + | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2495 + data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2496 + | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2497 +
2498 + for (i = 2; i < count; i++)
2499 + data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2500 +}
2501 +
2502 +static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2503 +{
2504 + struct sky2_port *sky2 = netdev_priv(netdev);
2505 + sky2->msg_enable = value;
2506 +}
2507 +
2508 +static int sky2_get_stats_count(struct net_device *dev)
2509 +{
2510 + return ARRAY_SIZE(sky2_stats);
2511 +}
2512 +
2513 +static void sky2_get_ethtool_stats(struct net_device *dev,
2514 + struct ethtool_stats *stats, u64 * data)
2515 +{
2516 + struct sky2_port *sky2 = netdev_priv(dev);
2517 +
2518 + sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2519 +}
2520 +
2521 +static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2522 +{
2523 + int i;
2524 +
2525 + switch (stringset) {
2526 + case ETH_SS_STATS:
2527 + for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2528 + memcpy(data + i * ETH_GSTRING_LEN,
2529 + sky2_stats[i].name, ETH_GSTRING_LEN);
2530 + break;
2531 + }
2532 +}
2533 +
2534 +/* Use hardware MIB variables for critical path statistics and
2535 + * transmit feedback not reported at interrupt.
2536 + * Other errors are accounted for in interrupt handler.
2537 + */
2538 +static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2539 +{
2540 + struct sky2_port *sky2 = netdev_priv(dev);
2541 + u64 data[13];
2542 +
2543 + sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2544 +
2545 + sky2->net_stats.tx_bytes = data[0];
2546 + sky2->net_stats.rx_bytes = data[1];
2547 + sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2548 + sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2549 + sky2->net_stats.multicast = data[5] + data[7];
2550 + sky2->net_stats.collisions = data[10];
2551 + sky2->net_stats.tx_aborted_errors = data[12];
2552 +
2553 + return &sky2->net_stats;
2554 +}
2555 +
2556 +static int sky2_set_mac_address(struct net_device *dev, void *p)
2557 +{
2558 + struct sky2_port *sky2 = netdev_priv(dev);
2559 + struct sockaddr *addr = p;
2560 +
2561 + if (!is_valid_ether_addr(addr->sa_data))
2562 + return -EADDRNOTAVAIL;
2563 +
2564 + memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2565 + memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8,
2566 + dev->dev_addr, ETH_ALEN);
2567 + memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8,
2568 + dev->dev_addr, ETH_ALEN);
2569 +
2570 + if (netif_running(dev))
2571 + sky2_phy_reinit(sky2);
2572 +
2573 + return 0;
2574 +}
2575 +
2576 +static void sky2_set_multicast(struct net_device *dev)
2577 +{
2578 + struct sky2_port *sky2 = netdev_priv(dev);
2579 + struct sky2_hw *hw = sky2->hw;
2580 + unsigned port = sky2->port;
2581 + struct dev_mc_list *list = dev->mc_list;
2582 + u16 reg;
2583 + u8 filter[8];
2584 +
2585 + memset(filter, 0, sizeof(filter));
2586 +
2587 + reg = gma_read16(hw, port, GM_RX_CTRL);
2588 + reg |= GM_RXCR_UCF_ENA;
2589 +
2590 + if (dev->flags & IFF_PROMISC) /* promiscuous */
2591 + reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2592 + else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2593 + memset(filter, 0xff, sizeof(filter));
2594 + else if (dev->mc_count == 0) /* no multicast */
2595 + reg &= ~GM_RXCR_MCF_ENA;
2596 + else {
2597 + int i;
2598 + reg |= GM_RXCR_MCF_ENA;
2599 +
2600 + for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2601 + u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2602 + filter[bit / 8] |= 1 << (bit % 8);
2603 + }
2604 + }
2605 +
2606 + gma_write16(hw, port, GM_MC_ADDR_H1,
2607 + (u16) filter[0] | ((u16) filter[1] << 8));
2608 + gma_write16(hw, port, GM_MC_ADDR_H2,
2609 + (u16) filter[2] | ((u16) filter[3] << 8));
2610 + gma_write16(hw, port, GM_MC_ADDR_H3,
2611 + (u16) filter[4] | ((u16) filter[5] << 8));
2612 + gma_write16(hw, port, GM_MC_ADDR_H4,
2613 + (u16) filter[6] | ((u16) filter[7] << 8));
2614 +
2615 + gma_write16(hw, port, GM_RX_CTRL, reg);
2616 +}
2617 +
2618 +/* Can have one global because blinking is controlled by
2619 + * ethtool and that is always under RTNL mutex
2620 + */
2621 +static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2622 +{
2623 + u16 pg;
2624 +
2625 + switch (hw->chip_id) {
2626 + case CHIP_ID_YUKON_XL:
2627 + pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2628 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2629 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2630 + on ? (PHY_M_LEDC_LOS_CTRL(1) |
2631 + PHY_M_LEDC_INIT_CTRL(7) |
2632 + PHY_M_LEDC_STA1_CTRL(7) |
2633 + PHY_M_LEDC_STA0_CTRL(7))
2634 + : 0);
2635 +
2636 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2637 + break;
2638 +
2639 + default:
2640 + gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2641 + gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2642 + on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2643 + PHY_M_LED_MO_10(MO_LED_ON) |
2644 + PHY_M_LED_MO_100(MO_LED_ON) |
2645 + PHY_M_LED_MO_1000(MO_LED_ON) |
2646 + PHY_M_LED_MO_RX(MO_LED_ON)
2647 + : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2648 + PHY_M_LED_MO_10(MO_LED_OFF) |
2649 + PHY_M_LED_MO_100(MO_LED_OFF) |
2650 + PHY_M_LED_MO_1000(MO_LED_OFF) |
2651 + PHY_M_LED_MO_RX(MO_LED_OFF));
2652 +
2653 + }
2654 +}
2655 +
2656 +/* blink LED's for finding board */
2657 +static int sky2_phys_id(struct net_device *dev, u32 data)
2658 +{
2659 + struct sky2_port *sky2 = netdev_priv(dev);
2660 + struct sky2_hw *hw = sky2->hw;
2661 + unsigned port = sky2->port;
2662 + u16 ledctrl, ledover = 0;
2663 + long ms;
2664 + int interrupted;
2665 + int onoff = 1;
2666 +
2667 + if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2668 + ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2669 + else
2670 + ms = data * 1000;
2671 +
2672 + /* save initial values */
2673 + down(&sky2->phy_sema);
2674 + if (hw->chip_id == CHIP_ID_YUKON_XL) {
2675 + u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2676 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2677 + ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2678 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2679 + } else {
2680 + ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2681 + ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2682 + }
2683 +
2684 + interrupted = 0;
2685 + while (!interrupted && ms > 0) {
2686 + sky2_led(hw, port, onoff);
2687 + onoff = !onoff;
2688 +
2689 + up(&sky2->phy_sema);
2690 + interrupted = msleep_interruptible(250);
2691 + down(&sky2->phy_sema);
2692 +
2693 + ms -= 250;
2694 + }
2695 +
2696 + /* resume regularly scheduled programming */
2697 + if (hw->chip_id == CHIP_ID_YUKON_XL) {
2698 + u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2699 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2700 + gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2701 + gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2702 + } else {
2703 + gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2704 + gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2705 + }
2706 + up(&sky2->phy_sema);
2707 +
2708 + return 0;
2709 +}
2710 +
2711 +static void sky2_get_pauseparam(struct net_device *dev,
2712 + struct ethtool_pauseparam *ecmd)
2713 +{
2714 + struct sky2_port *sky2 = netdev_priv(dev);
2715 +
2716 + ecmd->tx_pause = sky2->tx_pause;
2717 + ecmd->rx_pause = sky2->rx_pause;
2718 + ecmd->autoneg = sky2->autoneg;
2719 +}
2720 +
2721 +static int sky2_set_pauseparam(struct net_device *dev,
2722 + struct ethtool_pauseparam *ecmd)
2723 +{
2724 + struct sky2_port *sky2 = netdev_priv(dev);
2725 + int err = 0;
2726 +
2727 + sky2->autoneg = ecmd->autoneg;
2728 + sky2->tx_pause = ecmd->tx_pause != 0;
2729 + sky2->rx_pause = ecmd->rx_pause != 0;
2730 +
2731 + sky2_phy_reinit(sky2);
2732 +
2733 + return err;
2734 +}
2735 +
2736 +#ifdef CONFIG_PM
2737 +static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2738 +{
2739 + struct sky2_port *sky2 = netdev_priv(dev);
2740 +
2741 + wol->supported = WAKE_MAGIC;
2742 + wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2743 +}
2744 +
2745 +static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2746 +{
2747 + struct sky2_port *sky2 = netdev_priv(dev);
2748 + struct sky2_hw *hw = sky2->hw;
2749 +
2750 + if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2751 + return -EOPNOTSUPP;
2752 +
2753 + sky2->wol = wol->wolopts == WAKE_MAGIC;
2754 +
2755 + if (sky2->wol) {
2756 + memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2757 +
2758 + sky2_write16(hw, WOL_CTRL_STAT,
2759 + WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2760 + WOL_CTL_ENA_MAGIC_PKT_UNIT);
2761 + } else
2762 + sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2763 +
2764 + return 0;
2765 +}
2766 +#endif
2767 +
2768 +static int sky2_get_coalesce(struct net_device *dev,
2769 + struct ethtool_coalesce *ecmd)
2770 +{
2771 + struct sky2_port *sky2 = netdev_priv(dev);
2772 + struct sky2_hw *hw = sky2->hw;
2773 +
2774 + if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2775 + ecmd->tx_coalesce_usecs = 0;
2776 + else {
2777 + u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2778 + ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2779 + }
2780 + ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2781 +
2782 + if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2783 + ecmd->rx_coalesce_usecs = 0;
2784 + else {
2785 + u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2786 + ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2787 + }
2788 + ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2789 +
2790 + if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2791 + ecmd->rx_coalesce_usecs_irq = 0;
2792 + else {
2793 + u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2794 + ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2795 + }
2796 +
2797 + ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2798 +
2799 + return 0;
2800 +}
2801 +
2802 +/* Note: this affect both ports */
2803 +static int sky2_set_coalesce(struct net_device *dev,
2804 + struct ethtool_coalesce *ecmd)
2805 +{
2806 + struct sky2_port *sky2 = netdev_priv(dev);
2807 + struct sky2_hw *hw = sky2->hw;
2808 + const u32 tmin = sky2_clk2us(hw, 1);
2809 + const u32 tmax = 5000;
2810 +
2811 + if (ecmd->tx_coalesce_usecs != 0 &&
2812 + (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax))
2813 + return -EINVAL;
2814 +
2815 + if (ecmd->rx_coalesce_usecs != 0 &&
2816 + (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax))
2817 + return -EINVAL;
2818 +
2819 + if (ecmd->rx_coalesce_usecs_irq != 0 &&
2820 + (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax))
2821 + return -EINVAL;
2822 +
2823 + if (ecmd->tx_max_coalesced_frames > 0xffff)
2824 + return -EINVAL;
2825 + if (ecmd->rx_max_coalesced_frames > 0xff)
2826 + return -EINVAL;
2827 + if (ecmd->rx_max_coalesced_frames_irq > 0xff)
2828 + return -EINVAL;
2829 +
2830 + if (ecmd->tx_coalesce_usecs == 0)
2831 + sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2832 + else {
2833 + sky2_write32(hw, STAT_TX_TIMER_INI,
2834 + sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2835 + sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2836 + }
2837 + sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2838 +
2839 + if (ecmd->rx_coalesce_usecs == 0)
2840 + sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2841 + else {
2842 + sky2_write32(hw, STAT_LEV_TIMER_INI,
2843 + sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2844 + sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2845 + }
2846 + sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2847 +
2848 + if (ecmd->rx_coalesce_usecs_irq == 0)
2849 + sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2850 + else {
2851 + sky2_write32(hw, STAT_TX_TIMER_INI,
2852 + sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2853 + sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2854 + }
2855 + sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2856 + return 0;
2857 +}
2858 +
2859 +static void sky2_get_ringparam(struct net_device *dev,
2860 + struct ethtool_ringparam *ering)
2861 +{
2862 + struct sky2_port *sky2 = netdev_priv(dev);
2863 +
2864 + ering->rx_max_pending = RX_MAX_PENDING;
2865 + ering->rx_mini_max_pending = 0;
2866 + ering->rx_jumbo_max_pending = 0;
2867 + ering->tx_max_pending = TX_RING_SIZE - 1;
2868 +
2869 + ering->rx_pending = sky2->rx_pending;
2870 + ering->rx_mini_pending = 0;
2871 + ering->rx_jumbo_pending = 0;
2872 + ering->tx_pending = sky2->tx_pending;
2873 +}
2874 +
2875 +static int sky2_set_ringparam(struct net_device *dev,
2876 + struct ethtool_ringparam *ering)
2877 +{
2878 + struct sky2_port *sky2 = netdev_priv(dev);
2879 + int err = 0;
2880 +
2881 + if (ering->rx_pending > RX_MAX_PENDING ||
2882 + ering->rx_pending < 8 ||
2883 + ering->tx_pending < MAX_SKB_TX_LE ||
2884 + ering->tx_pending > TX_RING_SIZE - 1)
2885 + return -EINVAL;
2886 +
2887 + if (netif_running(dev))
2888 + sky2_down(dev);
2889 +
2890 + sky2->rx_pending = ering->rx_pending;
2891 + sky2->tx_pending = ering->tx_pending;
2892 +
2893 + if (netif_running(dev)) {
2894 + err = sky2_up(dev);
2895 + if (err)
2896 + dev_close(dev);
2897 + else
2898 + sky2_set_multicast(dev);
2899 + }
2900 +
2901 + return err;
2902 +}
2903 +
2904 +static int sky2_get_regs_len(struct net_device *dev)
2905 +{
2906 + return 0x4000;
2907 +}
2908 +
2909 +/*
2910 + * Returns copy of control register region
2911 + * Note: access to the RAM address register set will cause timeouts.
2912 + */
2913 +static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2914 + void *p)
2915 +{
2916 + const struct sky2_port *sky2 = netdev_priv(dev);
2917 + const void __iomem *io = sky2->hw->regs;
2918 +
2919 + BUG_ON(regs->len < B3_RI_WTO_R1);
2920 + regs->version = 1;
2921 + memset(p, 0, regs->len);
2922 +
2923 + memcpy_fromio(p, io, B3_RAM_ADDR);
2924 +
2925 + memcpy_fromio(p + B3_RI_WTO_R1,
2926 + io + B3_RI_WTO_R1,
2927 + regs->len - B3_RI_WTO_R1);
2928 +}
2929 +
2930 +static struct ethtool_ops sky2_ethtool_ops = {
2931 + .get_settings = sky2_get_settings,
2932 + .set_settings = sky2_set_settings,
2933 + .get_drvinfo = sky2_get_drvinfo,
2934 + .get_msglevel = sky2_get_msglevel,
2935 + .set_msglevel = sky2_set_msglevel,
2936 + .nway_reset = sky2_nway_reset,
2937 + .get_regs_len = sky2_get_regs_len,
2938 + .get_regs = sky2_get_regs,
2939 + .get_link = ethtool_op_get_link,
2940 + .get_sg = ethtool_op_get_sg,
2941 + .set_sg = ethtool_op_set_sg,
2942 + .get_tx_csum = ethtool_op_get_tx_csum,
2943 + .set_tx_csum = ethtool_op_set_tx_csum,
2944 + .get_tso = ethtool_op_get_tso,
2945 + .set_tso = ethtool_op_set_tso,
2946 + .get_rx_csum = sky2_get_rx_csum,
2947 + .set_rx_csum = sky2_set_rx_csum,
2948 + .get_strings = sky2_get_strings,
2949 + .get_coalesce = sky2_get_coalesce,
2950 + .set_coalesce = sky2_set_coalesce,
2951 + .get_ringparam = sky2_get_ringparam,
2952 + .set_ringparam = sky2_set_ringparam,
2953 + .get_pauseparam = sky2_get_pauseparam,
2954 + .set_pauseparam = sky2_set_pauseparam,
2955 +#ifdef CONFIG_PM
2956 + .get_wol = sky2_get_wol,
2957 + .set_wol = sky2_set_wol,
2958 +#endif
2959 + .phys_id = sky2_phys_id,
2960 + .get_stats_count = sky2_get_stats_count,
2961 + .get_ethtool_stats = sky2_get_ethtool_stats,
2962 + .get_perm_addr = ethtool_op_get_perm_addr,
2963 +};
2964 +
2965 +/* Initialize network device */
2966 +static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2967 + unsigned port, int highmem)
2968 +{
2969 + struct sky2_port *sky2;
2970 + struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2971 +
2972 + if (!dev) {
2973 + printk(KERN_ERR "sky2 etherdev alloc failed");
2974 + return NULL;
2975 + }
2976 +
2977 + SET_MODULE_OWNER(dev);
2978 + SET_NETDEV_DEV(dev, &hw->pdev->dev);
2979 + dev->irq = hw->pdev->irq;
2980 + dev->open = sky2_up;
2981 + dev->stop = sky2_down;
2982 + dev->do_ioctl = sky2_ioctl;
2983 + dev->hard_start_xmit = sky2_xmit_frame;
2984 + dev->get_stats = sky2_get_stats;
2985 + dev->set_multicast_list = sky2_set_multicast;
2986 + dev->set_mac_address = sky2_set_mac_address;
2987 + dev->change_mtu = sky2_change_mtu;
2988 + SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
2989 + dev->tx_timeout = sky2_tx_timeout;
2990 + dev->watchdog_timeo = TX_WATCHDOG;
2991 + if (port == 0)
2992 + dev->poll = sky2_poll;
2993 + dev->weight = NAPI_WEIGHT;
2994 +#ifdef CONFIG_NET_POLL_CONTROLLER
2995 + dev->poll_controller = sky2_netpoll;
2996 +#endif
2997 +
2998 + sky2 = netdev_priv(dev);
2999 + sky2->netdev = dev;
3000 + sky2->hw = hw;
3001 + sky2->msg_enable = netif_msg_init(debug, default_msg);
3002 +
3003 + spin_lock_init(&sky2->tx_lock);
3004 + /* Auto speed and flow control */
3005 + sky2->autoneg = AUTONEG_ENABLE;
3006 + sky2->tx_pause = 1;
3007 + sky2->rx_pause = 1;
3008 + sky2->duplex = -1;
3009 + sky2->speed = -1;
3010 + sky2->advertising = sky2_supported_modes(hw);
3011 +
3012 + /* Receive checksum disabled for Yukon XL
3013 + * because of observed problems with incorrect
3014 + * values when multiple packets are received in one interrupt
3015 + */
3016 + sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
3017 +
3018 + INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2);
3019 + init_MUTEX(&sky2->phy_sema);
3020 + sky2->tx_pending = TX_DEF_PENDING;
3021 + sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
3022 + sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
3023 +
3024 + hw->dev[port] = dev;
3025 +
3026 + sky2->port = port;
3027 +
3028 + dev->features |= NETIF_F_LLTX;
3029 + if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3030 + dev->features |= NETIF_F_TSO;
3031 + if (highmem)
3032 + dev->features |= NETIF_F_HIGHDMA;
3033 + dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3034 +
3035 +#ifdef SKY2_VLAN_TAG_USED
3036 + dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3037 + dev->vlan_rx_register = sky2_vlan_rx_register;
3038 + dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3039 +#endif
3040 +
3041 + /* read the mac address */
3042 + memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3043 + memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3044 +
3045 + /* device is off until link detection */
3046 + netif_carrier_off(dev);
3047 + netif_stop_queue(dev);
3048 +
3049 + return dev;
3050 +}
3051 +
3052 +static void __devinit sky2_show_addr(struct net_device *dev)
3053 +{
3054 + const struct sky2_port *sky2 = netdev_priv(dev);
3055 +
3056 + if (netif_msg_probe(sky2))
3057 + printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3058 + dev->name,
3059 + dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3060 + dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3061 +}
3062 +
3063 +static int __devinit sky2_probe(struct pci_dev *pdev,
3064 + const struct pci_device_id *ent)
3065 +{
3066 + struct net_device *dev, *dev1 = NULL;
3067 + struct sky2_hw *hw;
3068 + int err, pm_cap, using_dac = 0;
3069 +
3070 + err = pci_enable_device(pdev);
3071 + if (err) {
3072 + printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3073 + pci_name(pdev));
3074 + goto err_out;
3075 + }
3076 +
3077 + err = pci_request_regions(pdev, DRV_NAME);
3078 + if (err) {
3079 + printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3080 + pci_name(pdev));
3081 + goto err_out;
3082 + }
3083 +
3084 + pci_set_master(pdev);
3085 +
3086 + /* Find power-management capability. */
3087 + pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3088 + if (pm_cap == 0) {
3089 + printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3090 + "aborting.\n");
3091 + err = -EIO;
3092 + goto err_out_free_regions;
3093 + }
3094 +
3095 + if (sizeof(dma_addr_t) > sizeof(u32) &&
3096 + !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3097 + using_dac = 1;
3098 + err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3099 + if (err < 0) {
3100 + printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3101 + "for consistent allocations\n", pci_name(pdev));
3102 + goto err_out_free_regions;
3103 + }
3104 +
3105 + } else {
3106 + err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3107 + if (err) {
3108 + printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3109 + pci_name(pdev));
3110 + goto err_out_free_regions;
3111 + }
3112 + }
3113 +
3114 +#ifdef __BIG_ENDIAN
3115 + /* byte swap descriptors in hardware */
3116 + {
3117 + u32 reg;
3118 +
3119 + pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3120 + reg |= PCI_REV_DESC;
3121 + pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3122 + }
3123 +#endif
3124 +
3125 + err = -ENOMEM;
3126 + hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3127 + if (!hw) {
3128 + printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3129 + pci_name(pdev));
3130 + goto err_out_free_regions;
3131 + }
3132 +
3133 + hw->pdev = pdev;
3134 +
3135 + hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3136 + if (!hw->regs) {
3137 + printk(KERN_ERR PFX "%s: cannot map device registers\n",
3138 + pci_name(pdev));
3139 + goto err_out_free_hw;
3140 + }
3141 + hw->pm_cap = pm_cap;
3142 +
3143 + err = sky2_reset(hw);
3144 + if (err)
3145 + goto err_out_iounmap;
3146 +
3147 + printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3148 + DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
3149 + yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3150 + hw->chip_id, hw->chip_rev);
3151 +
3152 + dev = sky2_init_netdev(hw, 0, using_dac);
3153 + if (!dev)
3154 + goto err_out_free_pci;
3155 +
3156 + err = register_netdev(dev);
3157 + if (err) {
3158 + printk(KERN_ERR PFX "%s: cannot register net device\n",
3159 + pci_name(pdev));
3160 + goto err_out_free_netdev;
3161 + }
3162 +
3163 + sky2_show_addr(dev);
3164 +
3165 + if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3166 + if (register_netdev(dev1) == 0)
3167 + sky2_show_addr(dev1);
3168 + else {
3169 + /* Failure to register second port need not be fatal */
3170 + printk(KERN_WARNING PFX
3171 + "register of second port failed\n");
3172 + hw->dev[1] = NULL;
3173 + free_netdev(dev1);
3174 + }
3175 + }
3176 +
3177 + err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
3178 + if (err) {
3179 + printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3180 + pci_name(pdev), pdev->irq);
3181 + goto err_out_unregister;
3182 + }
3183 +
3184 + hw->intr_mask = Y2_IS_BASE;
3185 + sky2_write32(hw, B0_IMSK, hw->intr_mask);
3186 +
3187 + pci_set_drvdata(pdev, hw);
3188 +
3189 + return 0;
3190 +
3191 +err_out_unregister:
3192 + if (dev1) {
3193 + unregister_netdev(dev1);
3194 + free_netdev(dev1);
3195 + }
3196 + unregister_netdev(dev);
3197 +err_out_free_netdev:
3198 + free_netdev(dev);
3199 +err_out_free_pci:
3200 + sky2_write8(hw, B0_CTST, CS_RST_SET);
3201 + pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3202 +err_out_iounmap:
3203 + iounmap(hw->regs);
3204 +err_out_free_hw:
3205 + kfree(hw);
3206 +err_out_free_regions:
3207 + pci_release_regions(pdev);
3208 + pci_disable_device(pdev);
3209 +err_out:
3210 + return err;
3211 +}
3212 +
3213 +static void __devexit sky2_remove(struct pci_dev *pdev)
3214 +{
3215 + struct sky2_hw *hw = pci_get_drvdata(pdev);
3216 + struct net_device *dev0, *dev1;
3217 +
3218 + if (!hw)
3219 + return;
3220 +
3221 + dev0 = hw->dev[0];
3222 + dev1 = hw->dev[1];
3223 + if (dev1)
3224 + unregister_netdev(dev1);
3225 + unregister_netdev(dev0);
3226 +
3227 + sky2_write32(hw, B0_IMSK, 0);
3228 + sky2_set_power_state(hw, PCI_D3hot);
3229 + sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3230 + sky2_write8(hw, B0_CTST, CS_RST_SET);
3231 + sky2_read8(hw, B0_CTST);
3232 +
3233 + free_irq(pdev->irq, hw);
3234 + pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3235 + pci_release_regions(pdev);
3236 + pci_disable_device(pdev);
3237 +
3238 + if (dev1)
3239 + free_netdev(dev1);
3240 + free_netdev(dev0);
3241 + iounmap(hw->regs);
3242 + kfree(hw);
3243 +
3244 + pci_set_drvdata(pdev, NULL);
3245 +}
3246 +
3247 +#ifdef CONFIG_PM
3248 +static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3249 +{
3250 + struct sky2_hw *hw = pci_get_drvdata(pdev);
3251 + int i;
3252 +
3253 + for (i = 0; i < 2; i++) {
3254 + struct net_device *dev = hw->dev[i];
3255 +
3256 + if (dev) {
3257 + if (!netif_running(dev))
3258 + continue;
3259 +
3260 + sky2_down(dev);
3261 + netif_device_detach(dev);
3262 + }
3263 + }
3264 +
3265 + return sky2_set_power_state(hw, pci_choose_state(pdev, state));
3266 +}
3267 +
3268 +static int sky2_resume(struct pci_dev *pdev)
3269 +{
3270 + struct sky2_hw *hw = pci_get_drvdata(pdev);
3271 + int i;
3272 +
3273 + pci_restore_state(pdev);
3274 + pci_enable_wake(pdev, PCI_D0, 0);
3275 + sky2_set_power_state(hw, PCI_D0);
3276 +
3277 + sky2_reset(hw);
3278 +
3279 + for (i = 0; i < 2; i++) {
3280 + struct net_device *dev = hw->dev[i];
3281 + if (dev) {
3282 + if (netif_running(dev)) {
3283 + netif_device_attach(dev);
3284 + if (sky2_up(dev))
3285 + dev_close(dev);
3286 + }
3287 + }
3288 + }
3289 + return 0;
3290 +}
3291 +#endif
3292 +
3293 +static struct pci_driver sky2_driver = {
3294 + .name = DRV_NAME,
3295 + .id_table = sky2_id_table,
3296 + .probe = sky2_probe,
3297 + .remove = __devexit_p(sky2_remove),
3298 +#ifdef CONFIG_PM
3299 + .suspend = sky2_suspend,
3300 + .resume = sky2_resume,
3301 +#endif
3302 +};
3303 +
3304 +static int __init sky2_init_module(void)
3305 +{
3306 + return pci_register_driver(&sky2_driver);
3307 +}
3308 +
3309 +static void __exit sky2_cleanup_module(void)
3310 +{
3311 + pci_unregister_driver(&sky2_driver);
3312 +}
3313 +
3314 +module_init(sky2_init_module);
3315 +module_exit(sky2_cleanup_module);
3316 +
3317 +MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3318 +MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3319 +MODULE_LICENSE("GPL");
3320 +MODULE_VERSION(DRV_VERSION);
3321 --- linux-2.6.15/drivers/net/sky2.h 1970-01-01 01:00:00.000000000 +0100
3322 +++ linux-2.6.15-gentoo-r1/drivers/net/sky2.h 2006-01-15 14:26:58.000000000 +0000
3323 @@ -0,0 +1,1922 @@
3324 +/*
3325 + * Definitions for the new Marvell Yukon 2 driver.
3326 + */
3327 +#ifndef _SKY2_H
3328 +#define _SKY2_H
3329 +
3330 +/* PCI config registers */
3331 +#define PCI_DEV_REG1 0x40
3332 +#define PCI_DEV_REG2 0x44
3333 +#define PCI_DEV_STATUS 0x7c
3334 +#define PCI_OS_PCI_X (1<<26)
3335 +
3336 +#define PEX_LNK_STAT 0xf2
3337 +#define PEX_UNC_ERR_STAT 0x104
3338 +#define PEX_DEV_CTRL 0xe8
3339 +
3340 +/* Yukon-2 */
3341 +enum pci_dev_reg_1 {
3342 + PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
3343 + PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
3344 + PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
3345 + PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
3346 + PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
3347 + PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
3348 +};
3349 +
3350 +enum pci_dev_reg_2 {
3351 + PCI_VPD_WR_THR = 0xffL<<24, /* Bit 31..24: VPD Write Threshold */
3352 + PCI_DEV_SEL = 0x7fL<<17, /* Bit 23..17: EEPROM Device Select */
3353 + PCI_VPD_ROM_SZ = 7L<<14, /* Bit 16..14: VPD ROM Size */
3354 +
3355 + PCI_PATCH_DIR = 0xfL<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */
3356 + PCI_EXT_PATCHS = 0xfL<<4, /* Bit 7.. 4: Extended Patches 3..0 */
3357 + PCI_EN_DUMMY_RD = 1<<3, /* Enable Dummy Read */
3358 + PCI_REV_DESC = 1<<2, /* Reverse Desc. Bytes */
3359 +
3360 + PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */
3361 +};
3362 +
3363 +
3364 +#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
3365 + PCI_STATUS_SIG_SYSTEM_ERROR | \
3366 + PCI_STATUS_REC_MASTER_ABORT | \
3367 + PCI_STATUS_REC_TARGET_ABORT | \
3368 + PCI_STATUS_PARITY)
3369 +
3370 +enum pex_dev_ctrl {
3371 + PEX_DC_MAX_RRS_MSK = 7<<12, /* Bit 14..12: Max. Read Request Size */
3372 + PEX_DC_EN_NO_SNOOP = 1<<11,/* Enable No Snoop */
3373 + PEX_DC_EN_AUX_POW = 1<<10,/* Enable AUX Power */
3374 + PEX_DC_EN_PHANTOM = 1<<9, /* Enable Phantom Functions */
3375 + PEX_DC_EN_EXT_TAG = 1<<8, /* Enable Extended Tag Field */
3376 + PEX_DC_MAX_PLS_MSK = 7<<5, /* Bit 7.. 5: Max. Payload Size Mask */
3377 + PEX_DC_EN_REL_ORD = 1<<4, /* Enable Relaxed Ordering */
3378 + PEX_DC_EN_UNS_RQ_RP = 1<<3, /* Enable Unsupported Request Reporting */
3379 + PEX_DC_EN_FAT_ER_RP = 1<<2, /* Enable Fatal Error Reporting */
3380 + PEX_DC_EN_NFA_ER_RP = 1<<1, /* Enable Non-Fatal Error Reporting */
3381 + PEX_DC_EN_COR_ER_RP = 1<<0, /* Enable Correctable Error Reporting */
3382 +};
3383 +#define PEX_DC_MAX_RD_RQ_SIZE(x) (((x)<<12) & PEX_DC_MAX_RRS_MSK)
3384 +
3385 +/* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */
3386 +enum pex_err {
3387 + PEX_UNSUP_REQ = 1<<20, /* Unsupported Request Error */
3388 +
3389 + PEX_MALFOR_TLP = 1<<18, /* Malformed TLP */
3390 +
3391 + PEX_UNEXP_COMP = 1<<16, /* Unexpected Completion */
3392 +
3393 + PEX_COMP_TO = 1<<14, /* Completion Timeout */
3394 + PEX_FLOW_CTRL_P = 1<<13, /* Flow Control Protocol Error */
3395 + PEX_POIS_TLP = 1<<12, /* Poisoned TLP */
3396 +
3397 + PEX_DATA_LINK_P = 1<<4, /* Data Link Protocol Error */
3398 + PEX_FATAL_ERRORS= (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P),
3399 +};
3400 +
3401 +
3402 +enum csr_regs {
3403 + B0_RAP = 0x0000,
3404 + B0_CTST = 0x0004,
3405 + B0_Y2LED = 0x0005,
3406 + B0_POWER_CTRL = 0x0007,
3407 + B0_ISRC = 0x0008,
3408 + B0_IMSK = 0x000c,
3409 + B0_HWE_ISRC = 0x0010,
3410 + B0_HWE_IMSK = 0x0014,
3411 +
3412 + /* Special ISR registers (Yukon-2 only) */
3413 + B0_Y2_SP_ISRC2 = 0x001c,
3414 + B0_Y2_SP_ISRC3 = 0x0020,
3415 + B0_Y2_SP_EISR = 0x0024,
3416 + B0_Y2_SP_LISR = 0x0028,
3417 + B0_Y2_SP_ICR = 0x002c,
3418 +
3419 + B2_MAC_1 = 0x0100,
3420 + B2_MAC_2 = 0x0108,
3421 + B2_MAC_3 = 0x0110,
3422 + B2_CONN_TYP = 0x0118,
3423 + B2_PMD_TYP = 0x0119,
3424 + B2_MAC_CFG = 0x011a,
3425 + B2_CHIP_ID = 0x011b,
3426 + B2_E_0 = 0x011c,
3427 +
3428 + B2_Y2_CLK_GATE = 0x011d,
3429 + B2_Y2_HW_RES = 0x011e,
3430 + B2_E_3 = 0x011f,
3431 + B2_Y2_CLK_CTRL = 0x0120,
3432 +
3433 + B2_TI_INI = 0x0130,
3434 + B2_TI_VAL = 0x0134,
3435 + B2_TI_CTRL = 0x0138,
3436 + B2_TI_TEST = 0x0139,
3437 +
3438 + B2_TST_CTRL1 = 0x0158,
3439 + B2_TST_CTRL2 = 0x0159,
3440 + B2_GP_IO = 0x015c,
3441 +
3442 + B2_I2C_CTRL = 0x0160,
3443 + B2_I2C_DATA = 0x0164,
3444 + B2_I2C_IRQ = 0x0168,
3445 + B2_I2C_SW = 0x016c,
3446 +
3447 + B3_RAM_ADDR = 0x0180,
3448 + B3_RAM_DATA_LO = 0x0184,
3449 + B3_RAM_DATA_HI = 0x0188,
3450 +
3451 +/* RAM Interface Registers */
3452 +/* Yukon-2: use RAM_BUFFER() to access the RAM buffer */
3453 +/*
3454 + * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
3455 + * not usable in SW. Please notice these are NOT real timeouts, these are
3456 + * the number of qWords transferred continuously.
3457 + */
3458 +#define RAM_BUFFER(port, reg) (reg | (port <<6))
3459 +
3460 + B3_RI_WTO_R1 = 0x0190,
3461 + B3_RI_WTO_XA1 = 0x0191,
3462 + B3_RI_WTO_XS1 = 0x0192,
3463 + B3_RI_RTO_R1 = 0x0193,
3464 + B3_RI_RTO_XA1 = 0x0194,
3465 + B3_RI_RTO_XS1 = 0x0195,
3466 + B3_RI_WTO_R2 = 0x0196,
3467 + B3_RI_WTO_XA2 = 0x0197,
3468 + B3_RI_WTO_XS2 = 0x0198,
3469 + B3_RI_RTO_R2 = 0x0199,
3470 + B3_RI_RTO_XA2 = 0x019a,
3471 + B3_RI_RTO_XS2 = 0x019b,
3472 + B3_RI_TO_VAL = 0x019c,
3473 + B3_RI_CTRL = 0x01a0,
3474 + B3_RI_TEST = 0x01a2,
3475 + B3_MA_TOINI_RX1 = 0x01b0,
3476 + B3_MA_TOINI_RX2 = 0x01b1,
3477 + B3_MA_TOINI_TX1 = 0x01b2,
3478 + B3_MA_TOINI_TX2 = 0x01b3,
3479 + B3_MA_TOVAL_RX1 = 0x01b4,
3480 + B3_MA_TOVAL_RX2 = 0x01b5,
3481 + B3_MA_TOVAL_TX1 = 0x01b6,
3482 + B3_MA_TOVAL_TX2 = 0x01b7,
3483 + B3_MA_TO_CTRL = 0x01b8,
3484 + B3_MA_TO_TEST = 0x01ba,
3485 + B3_MA_RCINI_RX1 = 0x01c0,
3486 + B3_MA_RCINI_RX2 = 0x01c1,
3487 + B3_MA_RCINI_TX1 = 0x01c2,
3488 + B3_MA_RCINI_TX2 = 0x01c3,
3489 + B3_MA_RCVAL_RX1 = 0x01c4,
3490 + B3_MA_RCVAL_RX2 = 0x01c5,
3491 + B3_MA_RCVAL_TX1 = 0x01c6,
3492 + B3_MA_RCVAL_TX2 = 0x01c7,
3493 + B3_MA_RC_CTRL = 0x01c8,
3494 + B3_MA_RC_TEST = 0x01ca,
3495 + B3_PA_TOINI_RX1 = 0x01d0,
3496 + B3_PA_TOINI_RX2 = 0x01d4,
3497 + B3_PA_TOINI_TX1 = 0x01d8,
3498 + B3_PA_TOINI_TX2 = 0x01dc,
3499 + B3_PA_TOVAL_RX1 = 0x01e0,
3500 + B3_PA_TOVAL_RX2 = 0x01e4,
3501 + B3_PA_TOVAL_TX1 = 0x01e8,
3502 + B3_PA_TOVAL_TX2 = 0x01ec,
3503 + B3_PA_CTRL = 0x01f0,
3504 + B3_PA_TEST = 0x01f2,
3505 +
3506 + Y2_CFG_SPC = 0x1c00,
3507 +};
3508 +
3509 +/* B0_CTST 16 bit Control/Status register */
3510 +enum {
3511 + Y2_VMAIN_AVAIL = 1<<17,/* VMAIN available (YUKON-2 only) */
3512 + Y2_VAUX_AVAIL = 1<<16,/* VAUX available (YUKON-2 only) */
3513 + Y2_ASF_ENABLE = 1<<13,/* ASF Unit Enable (YUKON-2 only) */
3514 + Y2_ASF_DISABLE = 1<<12,/* ASF Unit Disable (YUKON-2 only) */
3515 + Y2_CLK_RUN_ENA = 1<<11,/* CLK_RUN Enable (YUKON-2 only) */
3516 + Y2_CLK_RUN_DIS = 1<<10,/* CLK_RUN Disable (YUKON-2 only) */
3517 + Y2_LED_STAT_ON = 1<<9, /* Status LED On (YUKON-2 only) */
3518 + Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */
3519 +
3520 + CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
3521 + CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
3522 + CS_STOP_DONE = 1<<5, /* Stop Master is finished */
3523 + CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
3524 + CS_MRST_CLR = 1<<3, /* Clear Master reset */
3525 + CS_MRST_SET = 1<<2, /* Set Master reset */
3526 + CS_RST_CLR = 1<<1, /* Clear Software reset */
3527 + CS_RST_SET = 1, /* Set Software reset */
3528 +};
3529 +
3530 +/* B0_LED 8 Bit LED register */
3531 +enum {
3532 +/* Bit 7.. 2: reserved */
3533 + LED_STAT_ON = 1<<1, /* Status LED on */
3534 + LED_STAT_OFF = 1, /* Status LED off */
3535 +};
3536 +
3537 +/* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
3538 +enum {
3539 + PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
3540 + PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
3541 + PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
3542 + PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
3543 + PC_VAUX_ON = 1<<3, /* Switch VAUX On */
3544 + PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
3545 + PC_VCC_ON = 1<<1, /* Switch VCC On */
3546 + PC_VCC_OFF = 1<<0, /* Switch VCC Off */
3547 +};
3548 +
3549 +/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
3550 +
3551 +/* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */
3552 +/* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */
3553 +/* B0_Y2_SP_EISR 32 bit Enter ISR Reg */
3554 +/* B0_Y2_SP_LISR 32 bit Leave ISR Reg */
3555 +enum {
3556 + Y2_IS_HW_ERR = 1<<31, /* Interrupt HW Error */
3557 + Y2_IS_STAT_BMU = 1<<30, /* Status BMU Interrupt */
3558 + Y2_IS_ASF = 1<<29, /* ASF subsystem Interrupt */
3559 +
3560 + Y2_IS_POLL_CHK = 1<<27, /* Check IRQ from polling unit */
3561 + Y2_IS_TWSI_RDY = 1<<26, /* IRQ on end of TWSI Tx */
3562 + Y2_IS_IRQ_SW = 1<<25, /* SW forced IRQ */
3563 + Y2_IS_TIMINT = 1<<24, /* IRQ from Timer */
3564 +
3565 + Y2_IS_IRQ_PHY2 = 1<<12, /* Interrupt from PHY 2 */
3566 + Y2_IS_IRQ_MAC2 = 1<<11, /* Interrupt from MAC 2 */
3567 + Y2_IS_CHK_RX2 = 1<<10, /* Descriptor error Rx 2 */
3568 + Y2_IS_CHK_TXS2 = 1<<9, /* Descriptor error TXS 2 */
3569 + Y2_IS_CHK_TXA2 = 1<<8, /* Descriptor error TXA 2 */
3570 +
3571 + Y2_IS_IRQ_PHY1 = 1<<4, /* Interrupt from PHY 1 */
3572 + Y2_IS_IRQ_MAC1 = 1<<3, /* Interrupt from MAC 1 */
3573 + Y2_IS_CHK_RX1 = 1<<2, /* Descriptor error Rx 1 */
3574 + Y2_IS_CHK_TXS1 = 1<<1, /* Descriptor error TXS 1 */
3575 + Y2_IS_CHK_TXA1 = 1<<0, /* Descriptor error TXA 1 */
3576 +
3577 + Y2_IS_BASE = Y2_IS_HW_ERR | Y2_IS_STAT_BMU |
3578 + Y2_IS_POLL_CHK | Y2_IS_TWSI_RDY |
3579 + Y2_IS_IRQ_SW | Y2_IS_TIMINT,
3580 + Y2_IS_PORT_1 = Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1 |
3581 + Y2_IS_CHK_RX1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXS1,
3582 + Y2_IS_PORT_2 = Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 |
3583 + Y2_IS_CHK_RX2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_TXS2,
3584 +};
3585 +
3586 +/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
3587 +enum {
3588 + IS_ERR_MSK = 0x00003fff,/* All Error bits */
3589 +
3590 + IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
3591 + IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
3592 + IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
3593 + IS_IRQ_STAT = 1<<10, /* IRQ status exception */
3594 + IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
3595 + IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
3596 + IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
3597 + IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
3598 + IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
3599 + IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
3600 + IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
3601 + IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
3602 + IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
3603 + IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
3604 +};
3605 +
3606 +/* Hardware error interrupt mask for Yukon 2 */
3607 +enum {
3608 + Y2_IS_TIST_OV = 1<<29,/* Time Stamp Timer overflow interrupt */
3609 + Y2_IS_SENSOR = 1<<28, /* Sensor interrupt */
3610 + Y2_IS_MST_ERR = 1<<27, /* Master error interrupt */
3611 + Y2_IS_IRQ_STAT = 1<<26, /* Status exception interrupt */
3612 + Y2_IS_PCI_EXP = 1<<25, /* PCI-Express interrupt */
3613 + Y2_IS_PCI_NEXP = 1<<24, /* PCI-Express error similar to PCI error */
3614 + /* Link 2 */
3615 + Y2_IS_PAR_RD2 = 1<<13, /* Read RAM parity error interrupt */
3616 + Y2_IS_PAR_WR2 = 1<<12, /* Write RAM parity error interrupt */
3617 + Y2_IS_PAR_MAC2 = 1<<11, /* MAC hardware fault interrupt */
3618 + Y2_IS_PAR_RX2 = 1<<10, /* Parity Error Rx Queue 2 */
3619 + Y2_IS_TCP_TXS2 = 1<<9, /* TCP length mismatch sync Tx queue IRQ */
3620 + Y2_IS_TCP_TXA2 = 1<<8, /* TCP length mismatch async Tx queue IRQ */
3621 + /* Link 1 */
3622 + Y2_IS_PAR_RD1 = 1<<5, /* Read RAM parity error interrupt */
3623 + Y2_IS_PAR_WR1 = 1<<4, /* Write RAM parity error interrupt */
3624 + Y2_IS_PAR_MAC1 = 1<<3, /* MAC hardware fault interrupt */
3625 + Y2_IS_PAR_RX1 = 1<<2, /* Parity Error Rx Queue 1 */
3626 + Y2_IS_TCP_TXS1 = 1<<1, /* TCP length mismatch sync Tx queue IRQ */
3627 + Y2_IS_TCP_TXA1 = 1<<0, /* TCP length mismatch async Tx queue IRQ */
3628 +
3629 + Y2_HWE_L1_MASK = Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |
3630 + Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1,
3631 + Y2_HWE_L2_MASK = Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |
3632 + Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2,
3633 +
3634 + Y2_HWE_ALL_MASK = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT |
3635 + Y2_IS_PCI_EXP |
3636 + Y2_HWE_L1_MASK | Y2_HWE_L2_MASK,
3637 +};
3638 +
3639 +/* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
3640 +enum {
3641 + DPT_START = 1<<1,
3642 + DPT_STOP = 1<<0,
3643 +};
3644 +
3645 +/* B2_TST_CTRL1 8 bit Test Control Register 1 */
3646 +enum {
3647 + TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
3648 + TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
3649 + TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
3650 + TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
3651 + TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
3652 + TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
3653 + TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
3654 + TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
3655 +};
3656 +
3657 +/* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
3658 +enum {
3659 + CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
3660 + /* Bit 3.. 2: reserved */
3661 + CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
3662 + CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
3663 +};
3664 +
3665 +/* B2_CHIP_ID 8 bit Chip Identification Number */
3666 +enum {
3667 + CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */
3668 + CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */
3669 + CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
3670 + CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
3671 + CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
3672 + CHIP_ID_YUKON_EC_U = 0xb4, /* Chip ID for YUKON-2 EC Ultra */
3673 + CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
3674 + CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
3675 +
3676 + CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */
3677 + CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */
3678 + CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */
3679 +};
3680 +
3681 +/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
3682 +enum {
3683 + Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactive (0 = active) */
3684 + Y2_CLK_GAT_LNK2_DIS = 1<<6, /* Disable clock gating Link 2 */
3685 + Y2_COR_CLK_LNK2_DIS = 1<<5, /* Disable Core clock Link 2 */
3686 + Y2_PCI_CLK_LNK2_DIS = 1<<4, /* Disable PCI clock Link 2 */
3687 + Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactive (0 = active) */
3688 + Y2_CLK_GAT_LNK1_DIS = 1<<2, /* Disable clock gating Link 1 */
3689 + Y2_COR_CLK_LNK1_DIS = 1<<1, /* Disable Core clock Link 1 */
3690 + Y2_PCI_CLK_LNK1_DIS = 1<<0, /* Disable PCI clock Link 1 */
3691 +};
3692 +
3693 +/* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
3694 +enum {
3695 + CFG_LED_MODE_MSK = 7<<2, /* Bit 4.. 2: LED Mode Mask */
3696 + CFG_LINK_2_AVAIL = 1<<1, /* Link 2 available */
3697 + CFG_LINK_1_AVAIL = 1<<0, /* Link 1 available */
3698 +};
3699 +#define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2)
3700 +#define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)
3701 +
3702 +
3703 +/* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */
3704 +enum {
3705 + Y2_CLK_DIV_VAL_MSK = 0xff<<16,/* Bit 23..16: Clock Divisor Value */
3706 +#define Y2_CLK_DIV_VAL(x) (((x)<<16) & Y2_CLK_DIV_VAL_MSK)
3707 + Y2_CLK_DIV_VAL2_MSK = 7<<21, /* Bit 23..21: Clock Divisor Value */
3708 + Y2_CLK_SELECT2_MSK = 0x1f<<16,/* Bit 20..16: Clock Select */
3709 +#define Y2_CLK_DIV_VAL_2(x) (((x)<<21) & Y2_CLK_DIV_VAL2_MSK)
3710 +#define Y2_CLK_SEL_VAL_2(x) (((x)<<16) & Y2_CLK_SELECT2_MSK)
3711 + Y2_CLK_DIV_ENA = 1<<1, /* Enable Core Clock Division */
3712 + Y2_CLK_DIV_DIS = 1<<0, /* Disable Core Clock Division */
3713 +};
3714 +
3715 +/* B2_TI_CTRL 8 bit Timer control */
3716 +/* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
3717 +enum {
3718 + TIM_START = 1<<2, /* Start Timer */
3719 + TIM_STOP = 1<<1, /* Stop Timer */
3720 + TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
3721 +};
3722 +
3723 +/* B2_TI_TEST 8 Bit Timer Test */
3724 +/* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
3725 +/* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
3726 +enum {
3727 + TIM_T_ON = 1<<2, /* Test mode on */
3728 + TIM_T_OFF = 1<<1, /* Test mode off */
3729 + TIM_T_STEP = 1<<0, /* Test step */
3730 +};
3731 +
3732 +/* B3_RAM_ADDR 32 bit RAM Address, to read or write */
3733 + /* Bit 31..19: reserved */
3734 +#define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
3735 +/* RAM Interface Registers */
3736 +
3737 +/* B3_RI_CTRL 16 bit RAM Interface Control Register */
3738 +enum {
3739 + RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
3740 + RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
3741 +
3742 + RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
3743 + RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
3744 +};
3745 +
3746 +#define SK_RI_TO_53 36 /* RAM interface timeout */
3747 +
3748 +
3749 +/* Port related registers FIFO, and Arbiter */
3750 +#define SK_REG(port,reg) (((port)<<7)+(reg))
3751 +
3752 +/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
3753 +/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
3754 +/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
3755 +/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
3756 +/* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
3757 +
3758 +#define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
3759 +
3760 +/* TXA_CTRL 8 bit Tx Arbiter Control Register */
3761 +enum {
3762 + TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
3763 + TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
3764 + TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
3765 + TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
3766 + TXA_START_RC = 1<<3, /* Start sync Rate Control */
3767 + TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
3768 + TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
3769 + TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
3770 +};
3771 +
3772 +/*
3773 + * Bank 4 - 5
3774 + */
3775 +/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
3776 +enum {
3777 + TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
3778 + TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
3779 + TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
3780 + TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
3781 + TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
3782 + TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
3783 + TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
3784 +};
3785 +
3786 +
3787 +enum {
3788 + B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
3789 + B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
3790 + B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
3791 + B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
3792 + B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
3793 + B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
3794 + B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
3795 + B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
3796 + B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
3797 +};
3798 +
3799 +/* Queue Register Offsets, use Q_ADDR() to access */
3800 +enum {
3801 + B8_Q_REGS = 0x0400, /* base of Queue registers */
3802 + Q_D = 0x00, /* 8*32 bit Current Descriptor */
3803 + Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */
3804 + Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */
3805 + Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
3806 + Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
3807 + Q_BC = 0x30, /* 32 bit Current Byte Counter */
3808 + Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
3809 + Q_F = 0x38, /* 32 bit Flag Register */
3810 + Q_T1 = 0x3c, /* 32 bit Test Register 1 */
3811 + Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */
3812 + Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */
3813 + Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */
3814 + Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */
3815 + Q_T2 = 0x40, /* 32 bit Test Register 2 */
3816 + Q_T3 = 0x44, /* 32 bit Test Register 3 */
3817 +
3818 +/* Yukon-2 */
3819 + Q_DONE = 0x24, /* 16 bit Done Index (Yukon-2 only) */
3820 + Q_WM = 0x40, /* 16 bit FIFO Watermark */
3821 + Q_AL = 0x42, /* 8 bit FIFO Alignment */
3822 + Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */
3823 + Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */
3824 + Q_RP = 0x48, /* 8 bit FIFO Read Pointer */
3825 + Q_RL = 0x4a, /* 8 bit FIFO Read Level */
3826 + Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */
3827 + Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */
3828 + Q_WL = 0x4e, /* 8 bit FIFO Write Level */
3829 + Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */
3830 +};
3831 +#define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
3832 +
3833 +
3834 +/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
3835 +enum {
3836 + Y2_B8_PREF_REGS = 0x0450,
3837 +
3838 + PREF_UNIT_CTRL = 0x00, /* 32 bit Control register */
3839 + PREF_UNIT_LAST_IDX = 0x04, /* 16 bit Last Index */
3840 + PREF_UNIT_ADDR_LO = 0x08, /* 32 bit List start addr, low part */
3841 + PREF_UNIT_ADDR_HI = 0x0c, /* 32 bit List start addr, high part*/
3842 + PREF_UNIT_GET_IDX = 0x10, /* 16 bit Get Index */
3843 + PREF_UNIT_PUT_IDX = 0x14, /* 16 bit Put Index */
3844 + PREF_UNIT_FIFO_WP = 0x20, /* 8 bit FIFO write pointer */
3845 + PREF_UNIT_FIFO_RP = 0x24, /* 8 bit FIFO read pointer */
3846 + PREF_UNIT_FIFO_WM = 0x28, /* 8 bit FIFO watermark */
3847 + PREF_UNIT_FIFO_LEV = 0x2c, /* 8 bit FIFO level */
3848 +
3849 + PREF_UNIT_MASK_IDX = 0x0fff,
3850 +};
3851 +#define Y2_QADDR(q,reg) (Y2_B8_PREF_REGS + (q) + (reg))
3852 +
3853 +/* RAM Buffer Register Offsets */
3854 +enum {
3855 +
3856 + RB_START = 0x00,/* 32 bit RAM Buffer Start Address */
3857 + RB_END = 0x04,/* 32 bit RAM Buffer End Address */
3858 + RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
3859 + RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
3860 + RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
3861 + RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
3862 + RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */
3863 + RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
3864 + /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
3865 + RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
3866 + RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
3867 + RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
3868 + RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
3869 + RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
3870 +};
3871 +
3872 +/* Receive and Transmit Queues */
3873 +enum {
3874 + Q_R1 = 0x0000, /* Receive Queue 1 */
3875 + Q_R2 = 0x0080, /* Receive Queue 2 */
3876 + Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
3877 + Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
3878 + Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
3879 + Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
3880 +};
3881 +
3882 +/* Different PHY Types */
3883 +enum {
3884 + PHY_ADDR_MARV = 0,
3885 +};
3886 +
3887 +#define RB_ADDR(offs, queue) (B16_RAM_REGS + (queue) + (offs))
3888 +
3889 +
3890 +enum {
3891 + LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
3892 + LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
3893 + LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
3894 + LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
3895 +
3896 + LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
3897 +
3898 +/* Receive GMAC FIFO (YUKON and Yukon-2) */
3899 +
3900 + RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
3901 + RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
3902 + RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
3903 + RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
3904 + RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
3905 + RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
3906 + RX_GMF_UP_THR = 0x0c58,/* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */
3907 + RX_GMF_LP_THR = 0x0c5a,/* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */
3908 + RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
3909 + RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
3910 +
3911 + RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
3912 +
3913 + RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
3914 +
3915 + RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
3916 +};
3917 +
3918 +
3919 +/* Q_BC 32 bit Current Byte Counter */
3920 +
3921 +/* BMU Control Status Registers */
3922 +/* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
3923 +/* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
3924 +/* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
3925 +/* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
3926 +/* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
3927 +/* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
3928 +/* Q_CSR 32 bit BMU Control/Status Register */
3929 +
3930 +/* Rx BMU Control / Status Registers (Yukon-2) */
3931 +enum {
3932 + BMU_IDLE = 1<<31, /* BMU Idle State */
3933 + BMU_RX_TCP_PKT = 1<<30, /* Rx TCP Packet (when RSS Hash enabled) */
3934 + BMU_RX_IP_PKT = 1<<29, /* Rx IP Packet (when RSS Hash enabled) */
3935 +
3936 + BMU_ENA_RX_RSS_HASH = 1<<15, /* Enable Rx RSS Hash */
3937 + BMU_DIS_RX_RSS_HASH = 1<<14, /* Disable Rx RSS Hash */
3938 + BMU_ENA_RX_CHKSUM = 1<<13, /* Enable Rx TCP/IP Checksum Check */
3939 + BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */
3940 + BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */
3941 + BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment. error (Tx) */
3942 + BMU_CLR_IRQ_CHK = 1<<10, /* Clear IRQ Check */
3943 + BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */
3944 + BMU_START = 1<<8, /* Start Rx/Tx Queue */
3945 + BMU_FIFO_OP_ON = 1<<7, /* FIFO Operational On */
3946 + BMU_FIFO_OP_OFF = 1<<6, /* FIFO Operational Off */
3947 + BMU_FIFO_ENA = 1<<5, /* Enable FIFO */
3948 + BMU_FIFO_RST = 1<<4, /* Reset FIFO */
3949 + BMU_OP_ON = 1<<3, /* BMU Operational On */
3950 + BMU_OP_OFF = 1<<2, /* BMU Operational Off */
3951 + BMU_RST_CLR = 1<<1, /* Clear BMU Reset (Enable) */
3952 + BMU_RST_SET = 1<<0, /* Set BMU Reset */
3953 +
3954 + BMU_CLR_RESET = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR,
3955 + BMU_OPER_INIT = BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START |
3956 + BMU_FIFO_ENA | BMU_OP_ON,
3957 +
3958 + BMU_WM_DEFAULT = 0x600,
3959 +};
3960 +
3961 +/* Tx BMU Control / Status Registers (Yukon-2) */
3962 + /* Bit 31: same as for Rx */
3963 +enum {
3964 + BMU_TX_IPIDINCR_ON = 1<<13, /* Enable IP ID Increment */
3965 + BMU_TX_IPIDINCR_OFF = 1<<12, /* Disable IP ID Increment */
3966 + BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment length mismatch */
3967 +};
3968 +
3969 +/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
3970 +/* PREF_UNIT_CTRL 32 bit Prefetch Control register */
3971 +enum {
3972 + PREF_UNIT_OP_ON = 1<<3, /* prefetch unit operational */
3973 + PREF_UNIT_OP_OFF = 1<<2, /* prefetch unit not operational */
3974 + PREF_UNIT_RST_CLR = 1<<1, /* Clear Prefetch Unit Reset */
3975 + PREF_UNIT_RST_SET = 1<<0, /* Set Prefetch Unit Reset */
3976 +};
3977 +
3978 +/* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
3979 +/* RB_START 32 bit RAM Buffer Start Address */
3980 +/* RB_END 32 bit RAM Buffer End Address */
3981 +/* RB_WP 32 bit RAM Buffer Write Pointer */
3982 +/* RB_RP 32 bit RAM Buffer Read Pointer */
3983 +/* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
3984 +/* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
3985 +/* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
3986 +/* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
3987 +/* RB_PC 32 bit RAM Buffer Packet Counter */
3988 +/* RB_LEV 32 bit RAM Buffer Level Register */
3989 +
3990 +#define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
3991 +/* RB_TST2 8 bit RAM Buffer Test Register 2 */
3992 +/* RB_TST1 8 bit RAM Buffer Test Register 1 */
3993 +
3994 +/* RB_CTRL 8 bit RAM Buffer Control Register */
3995 +enum {
3996 + RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
3997 + RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
3998 + RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
3999 + RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
4000 + RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
4001 + RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
4002 +};
4003 +
4004 +
4005 +/* Transmit GMAC FIFO (YUKON only) */
4006 +enum {
4007 + TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
4008 + TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
4009 + TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
4010 +
4011 + TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
4012 + TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
4013 + TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
4014 +
4015 + TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
4016 + TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
4017 + TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
4018 +};
4019 +
4020 +/* Descriptor Poll Timer Registers */
4021 +enum {
4022 + B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
4023 + B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
4024 + B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
4025 +
4026 + B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
4027 +};
4028 +
4029 +/* Time Stamp Timer Registers (YUKON only) */
4030 +enum {
4031 + GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
4032 + GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
4033 + GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
4034 +};
4035 +
4036 +/* Polling Unit Registers (Yukon-2 only) */
4037 +enum {
4038 + POLL_CTRL = 0x0e20, /* 32 bit Polling Unit Control Reg */
4039 + POLL_LAST_IDX = 0x0e24,/* 16 bit Polling Unit List Last Index */
4040 +
4041 + POLL_LIST_ADDR_LO= 0x0e28,/* 32 bit Poll. List Start Addr (low) */
4042 + POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */
4043 +};
4044 +
4045 +/* ASF Subsystem Registers (Yukon-2 only) */
4046 +enum {
4047 + B28_Y2_SMB_CONFIG = 0x0e40,/* 32 bit ASF SMBus Config Register */
4048 + B28_Y2_SMB_CSD_REG = 0x0e44,/* 32 bit ASF SMB Control/Status/Data */
4049 + B28_Y2_ASF_IRQ_V_BASE=0x0e60,/* 32 bit ASF IRQ Vector Base */
4050 +
4051 + B28_Y2_ASF_STAT_CMD= 0x0e68,/* 32 bit ASF Status and Command Reg */
4052 + B28_Y2_ASF_HOST_COM= 0x0e6c,/* 32 bit ASF Host Communication Reg */
4053 + B28_Y2_DATA_REG_1 = 0x0e70,/* 32 bit ASF/Host Data Register 1 */
4054 + B28_Y2_DATA_REG_2 = 0x0e74,/* 32 bit ASF/Host Data Register 2 */
4055 + B28_Y2_DATA_REG_3 = 0x0e78,/* 32 bit ASF/Host Data Register 3 */
4056 + B28_Y2_DATA_REG_4 = 0x0e7c,/* 32 bit ASF/Host Data Register 4 */
4057 +};
4058 +
4059 +/* Status BMU Registers (Yukon-2 only)*/
4060 +enum {
4061 + STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */
4062 + STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */
4063 +
4064 + STAT_LIST_ADDR_LO= 0x0e88,/* 32 bit Status List Start Addr (low) */
4065 + STAT_LIST_ADDR_HI= 0x0e8c,/* 32 bit Status List Start Addr (high) */
4066 + STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */
4067 + STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */
4068 + STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */
4069 + STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */
4070 + STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */
4071 + STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */
4072 +
4073 +/* FIFO Control/Status Registers (Yukon-2 only)*/
4074 + STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */
4075 + STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */
4076 + STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */
4077 + STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */
4078 + STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */
4079 + STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */
4080 + STAT_FIFO_ISR_WM= 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */
4081 +
4082 +/* Level and ISR Timer Registers (Yukon-2 only)*/
4083 + STAT_LEV_TIMER_INI= 0x0eb0,/* 32 bit Level Timer Init. Value Reg */
4084 + STAT_LEV_TIMER_CNT= 0x0eb4,/* 32 bit Level Timer Counter Reg */
4085 + STAT_LEV_TIMER_CTRL= 0x0eb8,/* 8 bit Level Timer Control Reg */
4086 + STAT_LEV_TIMER_TEST= 0x0eb9,/* 8 bit Level Timer Test Reg */
4087 + STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */
4088 + STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */
4089 + STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */
4090 + STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */
4091 + STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */
4092 + STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */
4093 + STAT_ISR_TIMER_CTRL= 0x0ed8,/* 8 bit ISR Timer Control Reg */
4094 + STAT_ISR_TIMER_TEST= 0x0ed9,/* 8 bit ISR Timer Test Reg */
4095 +};
4096 +
4097 +enum {
4098 + LINKLED_OFF = 0x01,
4099 + LINKLED_ON = 0x02,
4100 + LINKLED_LINKSYNC_OFF = 0x04,
4101 + LINKLED_LINKSYNC_ON = 0x08,
4102 + LINKLED_BLINK_OFF = 0x10,
4103 + LINKLED_BLINK_ON = 0x20,
4104 +};
4105 +
4106 +/* GMAC and GPHY Control Registers (YUKON only) */
4107 +enum {
4108 + GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
4109 + GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
4110 + GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
4111 + GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
4112 + GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
4113 +
4114 +/* Wake-up Frame Pattern Match Control Registers (YUKON only) */
4115 +
4116 + WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
4117 +
4118 + WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
4119 + WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
4120 + WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
4121 + WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
4122 + WOL_PATT_PME = 0x0f2a,/* 8 bit WOL PME Match Enable (Yukon-2) */
4123 + WOL_PATT_ASFM = 0x0f2b,/* 8 bit WOL ASF Match Enable (Yukon-2) */
4124 + WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
4125 +
4126 +/* WOL Pattern Length Registers (YUKON only) */
4127 +
4128 + WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
4129 + WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
4130 +
4131 +/* WOL Pattern Counter Registers (YUKON only) */
4132 +
4133 +
4134 + WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
4135 + WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
4136 +};
4137 +
4138 +enum {
4139 + WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
4140 + WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
4141 +};
4142 +
4143 +enum {
4144 + BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
4145 + BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
4146 +};
4147 +
4148 +/*
4149 + * Marvel-PHY Registers, indirect addressed over GMAC
4150 + */
4151 +enum {
4152 + PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
4153 + PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
4154 + PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
4155 + PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
4156 + PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
4157 + PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
4158 + PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
4159 + PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
4160 + PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
4161 + /* Marvel-specific registers */
4162 + PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
4163 + PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
4164 + PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
4165 + PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
4166 + PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
4167 + PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
4168 + PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
4169 + PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
4170 + PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
4171 + PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
4172 + PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
4173 + PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
4174 + PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
4175 + PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
4176 + PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
4177 + PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
4178 + PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
4179 + PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
4180 +
4181 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
4182 + PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
4183 + PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
4184 + PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
4185 + PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
4186 + PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
4187 +};
4188 +
4189 +enum {
4190 + PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
4191 + PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
4192 + PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
4193 + PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
4194 + PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
4195 + PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
4196 + PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
4197 + PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
4198 + PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
4199 + PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
4200 +};
4201 +
4202 +enum {
4203 + PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
4204 + PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
4205 + PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
4206 +};
4207 +
4208 +enum {
4209 + PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
4210 +
4211 + PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
4212 + PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
4213 + PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */
4214 + PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
4215 + PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
4216 + PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
4217 + PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
4218 +};
4219 +
4220 +enum {
4221 + PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
4222 + PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
4223 + PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
4224 +};
4225 +
4226 +/* different Marvell PHY Ids */
4227 +enum {
4228 + PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
4229 +
4230 + PHY_BCOM_ID1_A1 = 0x6041,
4231 + PHY_BCOM_ID1_B2 = 0x6043,
4232 + PHY_BCOM_ID1_C0 = 0x6044,
4233 + PHY_BCOM_ID1_C5 = 0x6047,
4234 +
4235 + PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
4236 + PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
4237 + PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
4238 + PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
4239 +};
4240 +
4241 +/* Advertisement register bits */
4242 +enum {
4243 + PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
4244 + PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
4245 + PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */
4246 +
4247 + PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
4248 + PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */
4249 + PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */
4250 + PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
4251 + PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
4252 + PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
4253 + PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
4254 + PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
4255 + PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
4256 + PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
4257 + PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL |
4258 + PHY_AN_100HALF | PHY_AN_100FULL,
4259 +};
4260 +
4261 +/***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
4262 +/***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
4263 +enum {
4264 + PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
4265 + PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
4266 + PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
4267 + PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
4268 + PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
4269 + PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
4270 + /* Bit 9..8: reserved */
4271 + PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
4272 +};
4273 +
4274 +/** Marvell-Specific */
4275 +enum {
4276 + PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
4277 + PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */
4278 + PHY_M_AN_RF = 1<<13, /* Remote Fault */
4279 +
4280 + PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */
4281 + PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */
4282 + PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
4283 + PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
4284 + PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
4285 + PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
4286 + PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
4287 + PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
4288 +};
4289 +
4290 +/* special defines for FIBER (88E1011S only) */
4291 +enum {
4292 + PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
4293 + PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
4294 + PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
4295 + PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
4296 +};
4297 +
4298 +/* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
4299 +enum {
4300 + PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
4301 + PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
4302 + PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
4303 + PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
4304 +};
4305 +
4306 +/***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
4307 +enum {
4308 + PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
4309 + PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
4310 + PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
4311 + PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
4312 + PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
4313 + PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
4314 +};
4315 +
4316 +/***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
4317 +enum {
4318 + PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
4319 + PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
4320 + PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
4321 + PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */
4322 + PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
4323 + PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */
4324 + PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
4325 + PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */
4326 + PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */
4327 + PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */
4328 + PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */
4329 + PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */
4330 +};
4331 +
4332 +enum {
4333 + PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */
4334 + PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
4335 +};
4336 +
4337 +#define PHY_M_PC_MDI_XMODE(x) (((x)<<5) & PHY_M_PC_MDIX_MSK)
4338 +
4339 +enum {
4340 + PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
4341 + PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */
4342 + PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
4343 +};
4344 +
4345 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
4346 +enum {
4347 + PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
4348 + PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */
4349 + PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */
4350 + PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */
4351 + PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
4352 +
4353 + PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */
4354 + PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
4355 +
4356 + PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */
4357 + PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
4358 +};
4359 +
4360 +/***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
4361 +enum {
4362 + PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
4363 + PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */
4364 + PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */
4365 + PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */
4366 + PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */
4367 + PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */
4368 + PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */
4369 + PHY_M_PS_LINK_UP = 1<<10, /* Link Up */
4370 + PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
4371 + PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */
4372 + PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */
4373 + PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */
4374 + PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */
4375 + PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */
4376 + PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */
4377 + PHY_M_PS_JABBER = 1<<0, /* Jabber */
4378 +};
4379 +
4380 +#define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
4381 +
4382 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
4383 +enum {
4384 + PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */
4385 + PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
4386 +};
4387 +
4388 +enum {
4389 + PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
4390 + PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */
4391 + PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */
4392 + PHY_M_IS_AN_PR = 1<<12, /* Page Received */
4393 + PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
4394 + PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */
4395 + PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */
4396 + PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */
4397 + PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */
4398 + PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */
4399 + PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */
4400 + PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */
4401 +
4402 + PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */
4403 + PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */
4404 + PHY_M_IS_JABBER = 1<<0, /* Jabber */
4405 +
4406 + PHY_M_DEF_MSK = PHY_M_IS_LSP_CHANGE | PHY_M_IS_LST_CHANGE
4407 + | PHY_M_IS_FIFO_ERROR,
4408 + PHY_M_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
4409 +};
4410 +
4411 +
4412 +/***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
4413 +enum {
4414 + PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
4415 + PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
4416 +
4417 + PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
4418 + PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
4419 + /* (88E1011 only) */
4420 + PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */
4421 + /* (88E1011 only) */
4422 + PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */
4423 + /* (88E1111 only) */
4424 + PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
4425 + /* !!! Errata in spec. (1 = disable) */
4426 + PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
4427 + PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */
4428 + PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
4429 + PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
4430 + PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
4431 + PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};
4432 +
4433 +#define PHY_M_EC_M_DSC(x) ((x)<<10 & PHY_M_EC_M_DSC_MSK)
4434 + /* 00=1x; 01=2x; 10=3x; 11=4x */
4435 +#define PHY_M_EC_S_DSC(x) ((x)<<8 & PHY_M_EC_S_DSC_MSK)
4436 + /* 00=dis; 01=1x; 10=2x; 11=3x */
4437 +#define PHY_M_EC_DSC_2(x) ((x)<<9 & PHY_M_EC_M_DSC_MSK2)
4438 + /* 000=1x; 001=2x; 010=3x; 011=4x */
4439 +#define PHY_M_EC_MAC_S(x) ((x)<<4 & PHY_M_EC_MAC_S_MSK)
4440 + /* 01X=0; 110=2.5; 111=25 (MHz) */
4441 +
4442 +/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
4443 +enum {
4444 + PHY_M_PC_DIS_LINK_Pa = 1<<15,/* Disable Link Pulses */
4445 + PHY_M_PC_DSC_MSK = 7<<12,/* Bit 14..12: Downshift Counter */
4446 + PHY_M_PC_DOWN_S_ENA = 1<<11,/* Downshift Enable */
4447 +};
4448 +/* !!! Errata in spec. (1 = disable) */
4449 +
4450 +#define PHY_M_PC_DSC(x) (((x)<<12) & PHY_M_PC_DSC_MSK)
4451 + /* 100=5x; 101=6x; 110=7x; 111=8x */
4452 +enum {
4453 + MAC_TX_CLK_0_MHZ = 2,
4454 + MAC_TX_CLK_2_5_MHZ = 6,
4455 + MAC_TX_CLK_25_MHZ = 7,
4456 +};
4457 +
4458 +/***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
4459 +enum {
4460 + PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */
4461 + PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
4462 + PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
4463 + PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
4464 + PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
4465 + PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
4466 + PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
4467 + /* (88E1111 only) */
4468 +};
4469 +
4470 +enum {
4471 + PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */
4472 + /* (88E1011 only) */
4473 + PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
4474 + PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
4475 + PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
4476 + PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
4477 + PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
4478 +};
4479 +
4480 +#define PHY_M_LED_PULS_DUR(x) (((x)<<12) & PHY_M_LEDC_PULS_MSK)
4481 +
4482 +/***** PHY_MARV_PHY_STAT (page 3)16 bit r/w Polarity Control Reg. *****/
4483 +enum {
4484 + PHY_M_POLC_LS1M_MSK = 0xf<<12, /* Bit 15..12: LOS,STAT1 Mix % Mask */
4485 + PHY_M_POLC_IS0M_MSK = 0xf<<8, /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
4486 + PHY_M_POLC_LOS_MSK = 0x3<<6, /* Bit 7.. 6: LOS Pol. Ctrl. Mask */
4487 + PHY_M_POLC_INIT_MSK = 0x3<<4, /* Bit 5.. 4: INIT Pol. Ctrl. Mask */
4488 + PHY_M_POLC_STA1_MSK = 0x3<<2, /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */
4489 + PHY_M_POLC_STA0_MSK = 0x3, /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */
4490 +};
4491 +
4492 +#define PHY_M_POLC_LS1_P_MIX(x) (((x)<<12) & PHY_M_POLC_LS1M_MSK)
4493 +#define PHY_M_POLC_IS0_P_MIX(x) (((x)<<8) & PHY_M_POLC_IS0M_MSK)
4494 +#define PHY_M_POLC_LOS_CTRL(x) (((x)<<6) & PHY_M_POLC_LOS_MSK)
4495 +#define PHY_M_POLC_INIT_CTRL(x) (((x)<<4) & PHY_M_POLC_INIT_MSK)
4496 +#define PHY_M_POLC_STA1_CTRL(x) (((x)<<2) & PHY_M_POLC_STA1_MSK)
4497 +#define PHY_M_POLC_STA0_CTRL(x) (((x)<<0) & PHY_M_POLC_STA0_MSK)
4498 +
4499 +enum {
4500 + PULS_NO_STR = 0,/* no pulse stretching */
4501 + PULS_21MS = 1,/* 21 ms to 42 ms */
4502 + PULS_42MS = 2,/* 42 ms to 84 ms */
4503 + PULS_84MS = 3,/* 84 ms to 170 ms */
4504 + PULS_170MS = 4,/* 170 ms to 340 ms */
4505 + PULS_340MS = 5,/* 340 ms to 670 ms */
4506 + PULS_670MS = 6,/* 670 ms to 1.3 s */
4507 + PULS_1300MS = 7,/* 1.3 s to 2.7 s */
4508 +};
4509 +
4510 +#define PHY_M_LED_BLINK_RT(x) (((x)<<8) & PHY_M_LEDC_BL_R_MSK)
4511 +
4512 +enum {
4513 + BLINK_42MS = 0,/* 42 ms */
4514 + BLINK_84MS = 1,/* 84 ms */
4515 + BLINK_170MS = 2,/* 170 ms */
4516 + BLINK_340MS = 3,/* 340 ms */
4517 + BLINK_670MS = 4,/* 670 ms */
4518 +};
4519 +
4520 +/***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
4521 +#define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */
4522 + /* Bit 13..12: reserved */
4523 +#define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */
4524 +#define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */
4525 +#define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */
4526 +#define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */
4527 +#define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */
4528 +#define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */
4529 +
4530 +enum {
4531 + MO_LED_NORM = 0,
4532 + MO_LED_BLINK = 1,
4533 + MO_LED_OFF = 2,
4534 + MO_LED_ON = 3,
4535 +};
4536 +
4537 +/***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
4538 +enum {
4539 + PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */
4540 + PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */
4541 + PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
4542 + PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */
4543 + PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */
4544 +};
4545 +
4546 +/***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
4547 +enum {
4548 + PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
4549 + PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */
4550 + PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */
4551 + PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */
4552 + PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */
4553 + PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */
4554 + PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */
4555 + /* (88E1111 only) */
4556 +
4557 + PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
4558 + PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */
4559 + PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
4560 +};
4561 +
4562 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
4563 +/***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
4564 + /* Bit 15..12: reserved (used internally) */
4565 +enum {
4566 + PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
4567 + PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
4568 + PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
4569 +};
4570 +
4571 +#define PHY_M_FELP_LED2_CTRL(x) (((x)<<8) & PHY_M_FELP_LED2_MSK)
4572 +#define PHY_M_FELP_LED1_CTRL(x) (((x)<<4) & PHY_M_FELP_LED1_MSK)
4573 +#define PHY_M_FELP_LED0_CTRL(x) (((x)<<0) & PHY_M_FELP_LED0_MSK)
4574 +
4575 +enum {
4576 + LED_PAR_CTRL_COLX = 0x00,
4577 + LED_PAR_CTRL_ERROR = 0x01,
4578 + LED_PAR_CTRL_DUPLEX = 0x02,
4579 + LED_PAR_CTRL_DP_COL = 0x03,
4580 + LED_PAR_CTRL_SPEED = 0x04,
4581 + LED_PAR_CTRL_LINK = 0x05,
4582 + LED_PAR_CTRL_TX = 0x06,
4583 + LED_PAR_CTRL_RX = 0x07,
4584 + LED_PAR_CTRL_ACT = 0x08,
4585 + LED_PAR_CTRL_LNK_RX = 0x09,
4586 + LED_PAR_CTRL_LNK_AC = 0x0a,
4587 + LED_PAR_CTRL_ACT_BL = 0x0b,
4588 + LED_PAR_CTRL_TX_BL = 0x0c,
4589 + LED_PAR_CTRL_RX_BL = 0x0d,
4590 + LED_PAR_CTRL_COL_BL = 0x0e,
4591 + LED_PAR_CTRL_INACT = 0x0f
4592 +};
4593 +
4594 +/*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
4595 +enum {
4596 + PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */
4597 + PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
4598 + PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
4599 +};
4600 +
4601 +/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
4602 +/***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
4603 +enum {
4604 + PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */
4605 + PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */
4606 + PHY_M_MAC_MD_COPPER = 5,/* Copper only */
4607 + PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */
4608 +};
4609 +#define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK)
4610 +
4611 +/***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
4612 +enum {
4613 + PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */
4614 + PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
4615 + PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */
4616 + PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
4617 +};
4618 +
4619 +#define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK)
4620 +#define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK)
4621 +#define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK)
4622 +#define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK)
4623 +
4624 +/* GMAC registers */
4625 +/* Port Registers */
4626 +enum {
4627 + GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
4628 + GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
4629 + GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
4630 + GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
4631 + GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
4632 + GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
4633 + GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
4634 +/* Source Address Registers */
4635 + GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
4636 + GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
4637 + GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
4638 + GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
4639 + GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
4640 + GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
4641 +
4642 +/* Multicast Address Hash Registers */
4643 + GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
4644 + GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
4645 + GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
4646 + GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
4647 +
4648 +/* Interrupt Source Registers */
4649 + GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
4650 + GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
4651 + GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
4652 +
4653 +/* Interrupt Mask Registers */
4654 + GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
4655 + GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
4656 + GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
4657 +
4658 +/* Serial Management Interface (SMI) Registers */
4659 + GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
4660 + GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
4661 + GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
4662 +};
4663 +
4664 +/* MIB Counters */
4665 +#define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */
4666 +#define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */
4667 +
4668 +/*
4669 + * MIB Counters base address definitions (low word) -
4670 + * use offset 4 for access to high word (32 bit r/o)
4671 + */
4672 +enum {
4673 + GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */
4674 + GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */
4675 + GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
4676 + GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
4677 + GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
4678 + /* GM_MIB_CNT_BASE + 40: reserved */
4679 + GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
4680 + GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
4681 + GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
4682 + GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */
4683 + GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
4684 + GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
4685 + GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
4686 + GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */
4687 + GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */
4688 + GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */
4689 + GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */
4690 + GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */
4691 + GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */
4692 + GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152, /* Rx Frame too Long Error */
4693 + GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160, /* Rx Jabber Packet Frame */
4694 + /* GM_MIB_CNT_BASE + 168: reserved */
4695 + GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176, /* Rx FIFO overflow Event */
4696 + /* GM_MIB_CNT_BASE + 184: reserved */
4697 + GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192, /* Unicast Frames Xmitted OK */
4698 + GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200, /* Broadcast Frames Xmitted OK */
4699 + GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208, /* Pause MAC Ctrl Frames Xmitted */
4700 + GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216, /* Multicast Frames Xmitted OK */
4701 + GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224, /* Octets Transmitted OK Low */
4702 + GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232, /* Octets Transmitted OK High */
4703 + GM_TXF_64B = GM_MIB_CNT_BASE + 240, /* 64 Byte Tx Frame */
4704 + GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */
4705 + GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */
4706 + GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */
4707 + GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */
4708 + GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */
4709 + GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */
4710 +
4711 + GM_TXF_COL = GM_MIB_CNT_BASE + 304, /* Tx Collision */
4712 + GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312, /* Tx Late Collision */
4713 + GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320, /* Tx aborted due to Exces. Col. */
4714 + GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328, /* Tx Multiple Collision */
4715 + GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336, /* Tx Single Collision */
4716 + GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344, /* Tx FIFO Underrun Event */
4717 +};
4718 +
4719 +/* GMAC Bit Definitions */
4720 +/* GM_GP_STAT 16 bit r/o General Purpose Status Register */
4721 +enum {
4722 + GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */
4723 + GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
4724 + GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
4725 + GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
4726 + GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
4727 + GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
4728 + GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occured */
4729 + GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occured */
4730 +
4731 + GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
4732 + GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
4733 + GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */
4734 + GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
4735 + GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
4736 +};
4737 +
4738 +/* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
4739 +enum {
4740 + GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
4741 + GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
4742 + GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
4743 + GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
4744 + GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
4745 + GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
4746 + GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
4747 + GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */
4748 + GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */
4749 + GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
4750 + GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
4751 + GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */
4752 + GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
4753 + GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
4754 + GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
4755 +};
4756 +
4757 +#define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
4758 +#define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
4759 +
4760 +/* GM_TX_CTRL 16 bit r/w Transmit Control Register */
4761 +enum {
4762 + GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
4763 + GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
4764 + GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
4765 + GM_TXCR_COL_THR_MSK = 1<<10, /* Bit 12..10: Collision Threshold */
4766 +};
4767 +
4768 +#define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
4769 +#define TX_COL_DEF 0x04
4770 +
4771 +/* GM_RX_CTRL 16 bit r/w Receive Control Register */
4772 +enum {
4773 + GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
4774 + GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
4775 + GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
4776 + GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
4777 +};
4778 +
4779 +/* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
4780 +enum {
4781 + GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
4782 + GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */
4783 + GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */
4784 + GM_TXPA_BO_LIM_MSK = 0x0f, /* Bit 3.. 0: Backoff Limit Mask */
4785 +
4786 + TX_JAM_LEN_DEF = 0x03,
4787 + TX_JAM_IPG_DEF = 0x0b,
4788 + TX_IPG_JAM_DEF = 0x1c,
4789 + TX_BOF_LIM_DEF = 0x04,
4790 +};
4791 +
4792 +#define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK)
4793 +#define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK)
4794 +#define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK)
4795 +#define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK)
4796 +
4797 +
4798 +/* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
4799 +enum {
4800 + GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
4801 + GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */
4802 + GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */
4803 + GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
4804 + GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
4805 +};
4806 +
4807 +#define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
4808 +#define DATA_BLIND_DEF 0x04
4809 +
4810 +#define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
4811 +#define IPG_DATA_DEF 0x1e
4812 +
4813 +/* GM_SMI_CTRL 16 bit r/w SMI Control Register */
4814 +enum {
4815 + GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */
4816 + GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */
4817 + GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
4818 + GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
4819 + GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
4820 +};
4821 +
4822 +#define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
4823 +#define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK)
4824 +
4825 +/* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
4826 +enum {
4827 + GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
4828 + GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
4829 +};
4830 +
4831 +/* Receive Frame Status Encoding */
4832 +enum {
4833 + GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */
4834 + GMR_FS_VLAN = 1<<13, /* VLAN Packet */
4835 + GMR_FS_JABBER = 1<<12, /* Jabber Packet */
4836 + GMR_FS_UN_SIZE = 1<<11, /* Undersize Packet */
4837 + GMR_FS_MC = 1<<10, /* Multicast Packet */
4838 + GMR_FS_BC = 1<<9, /* Broadcast Packet */
4839 + GMR_FS_RX_OK = 1<<8, /* Receive OK (Good Packet) */
4840 + GMR_FS_GOOD_FC = 1<<7, /* Good Flow-Control Packet */
4841 + GMR_FS_BAD_FC = 1<<6, /* Bad Flow-Control Packet */
4842 + GMR_FS_MII_ERR = 1<<5, /* MII Error */
4843 + GMR_FS_LONG_ERR = 1<<4, /* Too Long Packet */
4844 + GMR_FS_FRAGMENT = 1<<3, /* Fragment */
4845 +
4846 + GMR_FS_CRC_ERR = 1<<1, /* CRC Error */
4847 + GMR_FS_RX_FF_OV = 1<<0, /* Rx FIFO Overflow */
4848 +
4849 + GMR_FS_ANY_ERR = GMR_FS_RX_FF_OV | GMR_FS_CRC_ERR |
4850 + GMR_FS_FRAGMENT | GMR_FS_LONG_ERR |
4851 + GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
4852 + GMR_FS_UN_SIZE | GMR_FS_JABBER,
4853 +};
4854 +
4855 +/* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
4856 +enum {
4857 + RX_TRUNC_ON = 1<<27, /* enable packet truncation */
4858 + RX_TRUNC_OFF = 1<<26, /* disable packet truncation */
4859 + RX_VLAN_STRIP_ON = 1<<25, /* enable VLAN stripping */
4860 + RX_VLAN_STRIP_OFF = 1<<24, /* disable VLAN stripping */
4861 +
4862 + GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */
4863 + GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */
4864 + GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */
4865 +
4866 + GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */
4867 + GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */
4868 + GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */
4869 + GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
4870 + GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
4871 + GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
4872 + GMF_CLI_RX_C = 1<<4, /* Clear IRQ Rx Frame Complete */
4873 +
4874 + GMF_OPER_ON = 1<<3, /* Operational Mode On */
4875 + GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
4876 + GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
4877 + GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */
4878 +
4879 + RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */
4880 +
4881 + GMF_RX_CTRL_DEF = GMF_OPER_ON | GMF_RX_F_FL_ON,
4882 +};
4883 +
4884 +
4885 +/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
4886 +enum {
4887 + TX_STFW_DIS = 1<<31,/* Disable Store & Forward (Yukon-EC Ultra) */
4888 + TX_STFW_ENA = 1<<30,/* Enable Store & Forward (Yukon-EC Ultra) */
4889 +
4890 + TX_VLAN_TAG_ON = 1<<25,/* enable VLAN tagging */
4891 + TX_VLAN_TAG_OFF = 1<<24,/* disable VLAN tagging */
4892 +
4893 + GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */
4894 + GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */
4895 + GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */
4896 +
4897 + GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */
4898 + GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
4899 + GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */
4900 +};
4901 +
4902 +/* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
4903 +enum {
4904 + GMT_ST_START = 1<<2, /* Start Time Stamp Timer */
4905 + GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */
4906 + GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */
4907 +};
4908 +
4909 +/* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */
4910 +enum {
4911 + Y2_ASF_OS_PRES = 1<<4, /* ASF operation system present */
4912 + Y2_ASF_RESET = 1<<3, /* ASF system in reset state */
4913 + Y2_ASF_RUNNING = 1<<2, /* ASF system operational */
4914 + Y2_ASF_CLR_HSTI = 1<<1, /* Clear ASF IRQ */
4915 + Y2_ASF_IRQ = 1<<0, /* Issue an IRQ to ASF system */
4916 +
4917 + Y2_ASF_UC_STATE = 3<<2, /* ASF uC State */
4918 + Y2_ASF_CLK_HALT = 0, /* ASF system clock stopped */
4919 +};
4920 +
4921 +/* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */
4922 +enum {
4923 + Y2_ASF_CLR_ASFI = 1<<1, /* Clear host IRQ */
4924 + Y2_ASF_HOST_IRQ = 1<<0, /* Issue an IRQ to HOST system */
4925 +};
4926 +
4927 +/* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
4928 +enum {
4929 + SC_STAT_CLR_IRQ = 1<<4, /* Status Burst IRQ clear */
4930 + SC_STAT_OP_ON = 1<<3, /* Operational Mode On */
4931 + SC_STAT_OP_OFF = 1<<2, /* Operational Mode Off */
4932 + SC_STAT_RST_CLR = 1<<1, /* Clear Status Unit Reset (Enable) */
4933 + SC_STAT_RST_SET = 1<<0, /* Set Status Unit Reset */
4934 +};
4935 +
4936 +/* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
4937 +enum {
4938 + GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */
4939 + GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
4940 + GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */
4941 + GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */
4942 + GMC_PAUSE_ON = 1<<3, /* Pause On */
4943 + GMC_PAUSE_OFF = 1<<2, /* Pause Off */
4944 + GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */
4945 + GMC_RST_SET = 1<<0, /* Set GMAC Reset */
4946 +};
4947 +
4948 +/* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
4949 +enum {
4950 + GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
4951 + GPC_INT_POL_HI = 1<<27, /* IRQ Polarity is Active HIGH */
4952 + GPC_75_OHM = 1<<26, /* Use 75 Ohm Termination instead of 50 */
4953 + GPC_DIS_FC = 1<<25, /* Disable Automatic Fiber/Copper Detection */
4954 + GPC_DIS_SLEEP = 1<<24, /* Disable Energy Detect */
4955 + GPC_HWCFG_M_3 = 1<<23, /* HWCFG_MODE[3] */
4956 + GPC_HWCFG_M_2 = 1<<22, /* HWCFG_MODE[2] */
4957 + GPC_HWCFG_M_1 = 1<<21, /* HWCFG_MODE[1] */
4958 + GPC_HWCFG_M_0 = 1<<20, /* HWCFG_MODE[0] */
4959 + GPC_ANEG_0 = 1<<19, /* ANEG[0] */
4960 + GPC_ENA_XC = 1<<18, /* Enable MDI crossover */
4961 + GPC_DIS_125 = 1<<17, /* Disable 125 MHz clock */
4962 + GPC_ANEG_3 = 1<<16, /* ANEG[3] */
4963 + GPC_ANEG_2 = 1<<15, /* ANEG[2] */
4964 + GPC_ANEG_1 = 1<<14, /* ANEG[1] */
4965 + GPC_ENA_PAUSE = 1<<13, /* Enable Pause (SYM_OR_REM) */
4966 + GPC_PHYADDR_4 = 1<<12, /* Bit 4 of Phy Addr */
4967 + GPC_PHYADDR_3 = 1<<11, /* Bit 3 of Phy Addr */
4968 + GPC_PHYADDR_2 = 1<<10, /* Bit 2 of Phy Addr */
4969 + GPC_PHYADDR_1 = 1<<9, /* Bit 1 of Phy Addr */
4970 + GPC_PHYADDR_0 = 1<<8, /* Bit 0 of Phy Addr */
4971 + /* Bits 7..2: reserved */
4972 + GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */
4973 + GPC_RST_SET = 1<<0, /* Set GPHY Reset */
4974 +};
4975 +
4976 +/* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
4977 +/* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
4978 +enum {
4979 + GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */
4980 + GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */
4981 + GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */
4982 + GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */
4983 + GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */
4984 + GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
4985 +
4986 +#define GMAC_DEF_MSK GM_IS_TX_FF_UR
4987 +
4988 +/* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
4989 + /* Bits 15.. 2: reserved */
4990 + GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */
4991 + GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */
4992 +
4993 +
4994 +/* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
4995 + WOL_CTL_LINK_CHG_OCC = 1<<15,
4996 + WOL_CTL_MAGIC_PKT_OCC = 1<<14,
4997 + WOL_CTL_PATTERN_OCC = 1<<13,
4998 + WOL_CTL_CLEAR_RESULT = 1<<12,
4999 + WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11,
5000 + WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10,
5001 + WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9,
5002 + WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8,
5003 + WOL_CTL_ENA_PME_ON_PATTERN = 1<<7,
5004 + WOL_CTL_DIS_PME_ON_PATTERN = 1<<6,
5005 + WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5,
5006 + WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4,
5007 + WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3,
5008 + WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2,
5009 + WOL_CTL_ENA_PATTERN_UNIT = 1<<1,
5010 + WOL_CTL_DIS_PATTERN_UNIT = 1<<0,
5011 +};
5012 +
5013 +#define WOL_CTL_DEFAULT \
5014 + (WOL_CTL_DIS_PME_ON_LINK_CHG | \
5015 + WOL_CTL_DIS_PME_ON_PATTERN | \
5016 + WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
5017 + WOL_CTL_DIS_LINK_CHG_UNIT | \
5018 + WOL_CTL_DIS_PATTERN_UNIT | \
5019 + WOL_CTL_DIS_MAGIC_PKT_UNIT)
5020 +
5021 +/* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
5022 +#define WOL_CTL_PATT_ENA(x) (1 << (x))
5023 +
5024 +
5025 +/* Control flags */
5026 +enum {
5027 + UDPTCP = 1<<0,
5028 + CALSUM = 1<<1,
5029 + WR_SUM = 1<<2,
5030 + INIT_SUM= 1<<3,
5031 + LOCK_SUM= 1<<4,
5032 + INS_VLAN= 1<<5,
5033 + FRC_STAT= 1<<6,
5034 + EOP = 1<<7,
5035 +};
5036 +
5037 +enum {
5038 + HW_OWNER = 1<<7,
5039 + OP_TCPWRITE = 0x11,
5040 + OP_TCPSTART = 0x12,
5041 + OP_TCPINIT = 0x14,
5042 + OP_TCPLCK = 0x18,
5043 + OP_TCPCHKSUM = OP_TCPSTART,
5044 + OP_TCPIS = OP_TCPINIT | OP_TCPSTART,
5045 + OP_TCPLW = OP_TCPLCK | OP_TCPWRITE,
5046 + OP_TCPLSW = OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE,
5047 + OP_TCPLISW = OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE,
5048 +
5049 + OP_ADDR64 = 0x21,
5050 + OP_VLAN = 0x22,
5051 + OP_ADDR64VLAN = OP_ADDR64 | OP_VLAN,
5052 + OP_LRGLEN = 0x24,
5053 + OP_LRGLENVLAN = OP_LRGLEN | OP_VLAN,
5054 + OP_BUFFER = 0x40,
5055 + OP_PACKET = 0x41,
5056 + OP_LARGESEND = 0x43,
5057 +
5058 +/* YUKON-2 STATUS opcodes defines */
5059 + OP_RXSTAT = 0x60,
5060 + OP_RXTIMESTAMP = 0x61,
5061 + OP_RXVLAN = 0x62,
5062 + OP_RXCHKS = 0x64,
5063 + OP_RXCHKSVLAN = OP_RXCHKS | OP_RXVLAN,
5064 + OP_RXTIMEVLAN = OP_RXTIMESTAMP | OP_RXVLAN,
5065 + OP_RSS_HASH = 0x65,
5066 + OP_TXINDEXLE = 0x68,
5067 +};
5068 +
5069 +/* Yukon 2 hardware interface
5070 + * Not tested on big endian
5071 + */
5072 +struct sky2_tx_le {
5073 + union {
5074 + __le32 addr;
5075 + struct {
5076 + __le16 offset;
5077 + __le16 start;
5078 + } csum __attribute((packed));
5079 + struct {
5080 + __le16 size;
5081 + __le16 rsvd;
5082 + } tso __attribute((packed));
5083 + } tx;
5084 + __le16 length; /* also vlan tag or checksum start */
5085 + u8 ctrl;
5086 + u8 opcode;
5087 +} __attribute((packed));
5088 +
5089 +struct sky2_rx_le {
5090 + __le32 addr;
5091 + __le16 length;
5092 + u8 ctrl;
5093 + u8 opcode;
5094 +} __attribute((packed));;
5095 +
5096 +struct sky2_status_le {
5097 + __le32 status; /* also checksum */
5098 + __le16 length; /* also vlan tag */
5099 + u8 link;
5100 + u8 opcode;
5101 +} __attribute((packed));
5102 +
5103 +struct tx_ring_info {
5104 + struct sk_buff *skb;
5105 + DECLARE_PCI_UNMAP_ADDR(mapaddr);
5106 + u16 idx;
5107 +};
5108 +
5109 +struct ring_info {
5110 + struct sk_buff *skb;
5111 + dma_addr_t mapaddr;
5112 +};
5113 +
5114 +struct sky2_port {
5115 + struct sky2_hw *hw;
5116 + struct net_device *netdev;
5117 + unsigned port;
5118 + u32 msg_enable;
5119 +
5120 + spinlock_t tx_lock ____cacheline_aligned_in_smp;
5121 + struct tx_ring_info *tx_ring;
5122 + struct sky2_tx_le *tx_le;
5123 + u16 tx_cons; /* next le to check */
5124 + u16 tx_prod; /* next le to use */
5125 + u32 tx_addr64;
5126 + u16 tx_pending;
5127 + u16 tx_last_put;
5128 + u16 tx_last_mss;
5129 +
5130 + struct ring_info *rx_ring ____cacheline_aligned_in_smp;
5131 + struct sky2_rx_le *rx_le;
5132 + u32 rx_addr64;
5133 + u16 rx_next; /* next re to check */
5134 + u16 rx_put; /* next le index to use */
5135 + u16 rx_pending;
5136 + u16 rx_last_put;
5137 + u16 rx_bufsize;
5138 +#ifdef SKY2_VLAN_TAG_USED
5139 + u16 rx_tag;
5140 + struct vlan_group *vlgrp;
5141 +#endif
5142 +
5143 + dma_addr_t rx_le_map;
5144 + dma_addr_t tx_le_map;
5145 + u32 advertising; /* ADVERTISED_ bits */
5146 + u16 speed; /* SPEED_1000, SPEED_100, ... */
5147 + u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */
5148 + u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */
5149 + u8 rx_pause;
5150 + u8 tx_pause;
5151 + u8 rx_csum;
5152 + u8 wol;
5153 +
5154 + struct net_device_stats net_stats;
5155 +
5156 + struct work_struct phy_task;
5157 + struct semaphore phy_sema;
5158 +};
5159 +
5160 +struct sky2_hw {
5161 + void __iomem *regs;
5162 + struct pci_dev *pdev;
5163 + u32 intr_mask;
5164 + struct net_device *dev[2];
5165 +
5166 + int pm_cap;
5167 + u8 chip_id;
5168 + u8 chip_rev;
5169 + u8 copper;
5170 + u8 ports;
5171 +
5172 + struct sky2_status_le *st_le;
5173 + u32 st_idx;
5174 + dma_addr_t st_dma;
5175 +};
5176 +
5177 +/* Register accessor for memory mapped device */
5178 +static inline u32 sky2_read32(const struct sky2_hw *hw, unsigned reg)
5179 +{
5180 + return readl(hw->regs + reg);
5181 +}
5182 +
5183 +static inline u16 sky2_read16(const struct sky2_hw *hw, unsigned reg)
5184 +{
5185 + return readw(hw->regs + reg);
5186 +}
5187 +
5188 +static inline u8 sky2_read8(const struct sky2_hw *hw, unsigned reg)
5189 +{
5190 + return readb(hw->regs + reg);
5191 +}
5192 +
5193 +/* This should probably go away, bus based tweeks suck */
5194 +static inline int is_pciex(const struct sky2_hw *hw)
5195 +{
5196 + u32 status;
5197 + pci_read_config_dword(hw->pdev, PCI_DEV_STATUS, &status);
5198 + return (status & PCI_OS_PCI_X) == 0;
5199 +}
5200 +
5201 +static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val)
5202 +{
5203 + writel(val, hw->regs + reg);
5204 +}
5205 +
5206 +static inline void sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val)
5207 +{
5208 + writew(val, hw->regs + reg);
5209 +}
5210 +
5211 +static inline void sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val)
5212 +{
5213 + writeb(val, hw->regs + reg);
5214 +}
5215 +
5216 +/* Yukon PHY related registers */
5217 +#define SK_GMAC_REG(port,reg) \
5218 + (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
5219 +#define GM_PHY_RETRIES 100
5220 +
5221 +static inline u16 gma_read16(const struct sky2_hw *hw, unsigned port, unsigned reg)
5222 +{
5223 + return sky2_read16(hw, SK_GMAC_REG(port,reg));
5224 +}
5225 +
5226 +static inline u32 gma_read32(struct sky2_hw *hw, unsigned port, unsigned reg)
5227 +{
5228 + unsigned base = SK_GMAC_REG(port, reg);
5229 + return (u32) sky2_read16(hw, base)
5230 + | (u32) sky2_read16(hw, base+4) << 16;
5231 +}
5232 +
5233 +static inline void gma_write16(const struct sky2_hw *hw, unsigned port, int r, u16 v)
5234 +{
5235 + sky2_write16(hw, SK_GMAC_REG(port,r), v);
5236 +}
5237 +
5238 +static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg,
5239 + const u8 *addr)
5240 +{
5241 + gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8));
5242 + gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
5243 + gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
5244 +}
5245 +#endif
5246 --- linux-2.6.15/drivers/net/Makefile 2006-01-03 03:21:10.000000000 +0000
5247 +++ linux-2.6.15-gentoo-r1/drivers/net/Makefile 2006-01-15 14:26:58.000000000 +0000
5248 @@ -59,6 +59,7 @@ spidernet-y += spider_net.o spider_net_e
5249 obj-$(CONFIG_SPIDER_NET) += spidernet.o
5250 obj-$(CONFIG_TC35815) += tc35815.o
5251 obj-$(CONFIG_SKGE) += skge.o
5252 +obj-$(CONFIG_SKY2) += sky2.o
5253 obj-$(CONFIG_SK98LIN) += sk98lin/
5254 obj-$(CONFIG_SKFP) += skfp/
5255 obj-$(CONFIG_VIA_RHINE) += via-rhine.o
5256 --- linux-2.6.15/drivers/net/Kconfig 2006-01-03 03:21:10.000000000 +0000
5257 +++ linux-2.6.15-gentoo-r1/drivers/net/Kconfig 2006-01-21 12:49:51.000000000 +0000
5258 @@ -2008,7 +2008,17 @@ config SKGE
5259
5260 It does not support the link failover and network management
5261 features that "portable" vendor supplied sk98lin driver does.
5262 -
5263 +
5264 +config SKY2
5265 + tristate "SysKonnect Yukon2 support (EXPERIMENTAL)"
5266 + depends on PCI && EXPERIMENTAL
5267 + select CRC32
5268 + ---help---
5269 + This driver support the Marvell Yukon 2 Gigabit Ethernet adapter.
5270 +
5271 + To compile this driver as a module, choose M here: the module
5272 + will be called sky2. This is recommended.
5273 +
5274 config SK98LIN
5275 tristate "Marvell Yukon Chipset / SysKonnect SK-98xx Support"
5276 depends on PCI
5277 --- linux-2.6.15/include/linux/netdevice.h 2006-01-03 03:21:10.000000000 +0000
5278 +++ linux-2.6.15-gentoo-r1/include/linux/netdevice.h 2006-01-15 14:26:58.000000000 +0000
5279 @@ -801,12 +801,16 @@ static inline u32 netif_msg_init(int deb
5280 return (1 << debug_value) - 1;
5281 }
5282
5283 -/* Schedule rx intr now? */
5284 +/* Test if receive needs to be scheduled */
5285 +static inline int __netif_rx_schedule_prep(struct net_device *dev)
5286 +{
5287 + return !test_and_set_bit(__LINK_STATE_RX_SCHED, &dev->state);
5288 +}
5289
5290 +/* Test if receive needs to be scheduled but only if up */
5291 static inline int netif_rx_schedule_prep(struct net_device *dev)
5292 {
5293 - return netif_running(dev) &&
5294 - !test_and_set_bit(__LINK_STATE_RX_SCHED, &dev->state);
5295 + return netif_running(dev) && __netif_rx_schedule_prep(dev);
5296 }
5297
5298 /* Add interface to tail of rx poll list. This assumes that _prep has

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