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authorPaul Brook <paul@codesourcery.com>2009-07-30 13:33:47 +0100
committerPaul Brook <paul@codesourcery.com>2009-07-31 13:19:39 +0100
commitffe47d331d4f725567e83375ffc19a36dbdce7f5 (patch)
treee8f147778f62896926392d424fa476d06ff6e8bd
parentesp: fix interrupt register read (diff)
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Save/restore ARMv6 MMU state
Correctly save/restore ARMV6 MMU state. Signed-off-by: Paul Brook <paul@codesourcery.com>
-rw-r--r--target-arm/cpu.h2
-rw-r--r--target-arm/machine.c22
2 files changed, 22 insertions, 2 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 194f16cc7..afc2bfebb 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -405,7 +405,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define cpu_signal_handler cpu_arm_signal_handler
#define cpu_list arm_cpu_list
-#define CPU_SAVE_VERSION 1
+#define CPU_SAVE_VERSION 2
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
diff --git a/target-arm/machine.c b/target-arm/machine.c
index b1deacb8f..3925d3a2d 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -22,12 +22,15 @@ void cpu_save(QEMUFile *f, void *opaque)
}
qemu_put_be32(f, env->cp15.c0_cpuid);
qemu_put_be32(f, env->cp15.c0_cachetype);
+ qemu_put_be32(f, env->cp15.c0_cssel);
qemu_put_be32(f, env->cp15.c1_sys);
qemu_put_be32(f, env->cp15.c1_coproc);
qemu_put_be32(f, env->cp15.c1_xscaleauxcr);
qemu_put_be32(f, env->cp15.c2_base0);
qemu_put_be32(f, env->cp15.c2_base1);
+ qemu_put_be32(f, env->cp15.c2_control);
qemu_put_be32(f, env->cp15.c2_mask);
+ qemu_put_be32(f, env->cp15.c2_base_mask);
qemu_put_be32(f, env->cp15.c2_data);
qemu_put_be32(f, env->cp15.c2_insn);
qemu_put_be32(f, env->cp15.c3);
@@ -91,12 +94,18 @@ void cpu_save(QEMUFile *f, void *opaque)
qemu_put_be32(f, env->v7m.current_sp);
qemu_put_be32(f, env->v7m.exception);
}
+
+ if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
+ qemu_put_be32(f, env->teecr);
+ qemu_put_be32(f, env->teehbr);
+ }
}
int cpu_load(QEMUFile *f, void *opaque, int version_id)
{
CPUARMState *env = (CPUARMState *)opaque;
int i;
+ uint32_t val;
if (version_id != CPU_SAVE_VERSION)
return -EINVAL;
@@ -104,7 +113,10 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
for (i = 0; i < 16; i++) {
env->regs[i] = qemu_get_be32(f);
}
- cpsr_write(env, qemu_get_be32(f), 0xffffffff);
+ val = qemu_get_be32(f);
+ /* Avoid mode switch when restoring CPSR. */
+ env->uncached_cpsr = val & CPSR_M;
+ cpsr_write(env, val, 0xffffffff);
env->spsr = qemu_get_be32(f);
for (i = 0; i < 6; i++) {
env->banked_spsr[i] = qemu_get_be32(f);
@@ -117,12 +129,15 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
}
env->cp15.c0_cpuid = qemu_get_be32(f);
env->cp15.c0_cachetype = qemu_get_be32(f);
+ env->cp15.c0_cssel = qemu_get_be32(f);
env->cp15.c1_sys = qemu_get_be32(f);
env->cp15.c1_coproc = qemu_get_be32(f);
env->cp15.c1_xscaleauxcr = qemu_get_be32(f);
env->cp15.c2_base0 = qemu_get_be32(f);
env->cp15.c2_base1 = qemu_get_be32(f);
+ env->cp15.c2_control = qemu_get_be32(f);
env->cp15.c2_mask = qemu_get_be32(f);
+ env->cp15.c2_base_mask = qemu_get_be32(f);
env->cp15.c2_data = qemu_get_be32(f);
env->cp15.c2_insn = qemu_get_be32(f);
env->cp15.c3 = qemu_get_be32(f);
@@ -187,5 +202,10 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
env->v7m.exception = qemu_get_be32(f);
}
+ if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
+ env->teecr = qemu_get_be32(f);
+ env->teehbr = qemu_get_be32(f);
+ }
+
return 0;
}