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authorAurelien Jarno <aurelien@aurel32.net>2010-12-27 19:54:49 +0100
committerDoug Goldstein <cardoe@cardoe.com>2011-05-27 13:02:02 -0500
commite485959b33e1abdfa16f05e800de9edaad924b09 (patch)
treeeccb99fcbc865a49b1e23deea251da9af104ce37
parentAdd missing dependency. (diff)
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target-arm: fix bug in translation of REVSH
The translation of REVSH shifted the low byte 8 steps left before performing an 8-bit sign extend, causing this part of the expression to alwas be 0. Reported-by: Johan Bengtsson <teofrastius@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> (cherry picked from commit 1a855029af40df40144a322bba0e1e61c68eed2a) Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
-rw-r--r--target-arm/translate.c10
1 files changed, 3 insertions, 7 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 6fcdd7e54..cb19dd7b7 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -250,13 +250,9 @@ static void gen_rev16(TCGv var)
/* Byteswap low halfword and sign extend. */
static void gen_revsh(TCGv var)
{
- TCGv tmp = new_tmp();
- tcg_gen_shri_i32(tmp, var, 8);
- tcg_gen_andi_i32(tmp, tmp, 0x00ff);
- tcg_gen_shli_i32(var, var, 8);
- tcg_gen_ext8s_i32(var, var);
- tcg_gen_or_i32(var, var, tmp);
- dead_tmp(tmp);
+ tcg_gen_ext16u_i32(var, var);
+ tcg_gen_bswap16_i32(var, var);
+ tcg_gen_ext16s_i32(var, var);
}
/* Unsigned bitfield extract. */