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authorAurelien Jarno <aurelien@aurel32.net>2012-11-14 15:04:42 +0100
committerDoug Goldstein <cardoe@cardoe.com>2012-12-13 15:31:59 -0600
commit0fae4d874bbdd6a503eb60cf8769e24b62e2a29e (patch)
treebdbe56925c27a8c2ab94068a80838a14c22ac88c
parentnbd: fixes to read-only handling (diff)
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mips/malta: fix CBUS UART interrupt pin
According to the MIPS Malta Developement Platform User's Manual, the i8259 interrupt controller is supposed to be connected to the hardware IRQ0, and the CBUS UART to the hardware interrupt 2. In QEMU they are both connected to hardware interrupt 0, the CBUS UART interrupt being wrong. This patch fixes that. It should be noted that the irq array in QEMU includes the software interrupts, hence env->irq[2] is the first hardware interrupt. Cc: Ralf Baechle <ralf@linux-mips.org> Reviewed-by: Eric Johnson <ericj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> (cherry picked from commit 68d001928b151a0c50f367c0bdca645b3d5e9ed3) Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com> (cherry picked from commit f6b803df744f3b8fafd69fa8e8e0588ffd75f4ac)
-rw-r--r--hw/mips_malta.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index ad23f26e5..9289a28f7 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -860,7 +860,8 @@ void mips_malta_init (ram_addr_t ram_size,
be = 0;
#endif
/* FPGA */
- malta_fpga_init(system_memory, FPGA_ADDRESS, env->irq[2], serial_hds[2]);
+ /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */
+ malta_fpga_init(system_memory, FPGA_ADDRESS, env->irq[4], serial_hds[2]);
/* Load firmware in flash / BIOS. */
dinfo = drive_get(IF_PFLASH, 0, fl_idx);