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authorJes Sorensen <jes@sgi.com>2009-05-25 15:12:49 +0200
committerAvi Kivity <avi@redhat.com>2009-06-07 09:28:11 +0300
commitaaf630a4dd27f8d6e7b4b4c3e44d537a310624f6 (patch)
tree33277ed9dbb9c135ba3e9ec0089275b7a781b26d /cache-utils.h
parentMake qemu-kvm build and run again on ia64 (diff)
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Flush icache after dma operations for ia64
ia64 system depends on that platform issues snoop cycle to flush icache for memory touched by DMA write operations, but virtual DMA operations is emulated by memcpy, so use explict instrustions to flush the related icache, otherwise, guest may use obsolete icache. Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com> Signed-off-by: Jes Sorensen <jes@sgi.com> Signed-off-by: Avi Kivity <avi@redhat.com>
Diffstat (limited to 'cache-utils.h')
-rw-r--r--cache-utils.h21
1 files changed, 21 insertions, 0 deletions
diff --git a/cache-utils.h b/cache-utils.h
index b45fde44e..e4f27ef51 100644
--- a/cache-utils.h
+++ b/cache-utils.h
@@ -34,7 +34,28 @@ static inline void flush_icache_range(unsigned long start, unsigned long stop)
asm volatile ("isync" : : : "memory");
}
+/*
+ * Is this correct for PPC?
+ */
+static inline void dma_flush_range(unsigned long start, unsigned long stop)
+{
+}
+
+#elif defined(__ia64__)
+static inline void flush_icache_range(unsigned long start, unsigned long stop)
+{
+ while (start < stop) {
+ asm volatile ("fc %0" :: "r"(start));
+ start += 32;
+ }
+ asm volatile (";;sync.i;;srlz.i;;");
+}
+#define dma_flush_range(start, end) flush_icache_range(start, end)
+#define qemu_cache_utils_init(envp) do { (void) (envp); } while (0)
#else
+static inline void dma_flush_range(unsigned long start, unsigned long stop)
+{
+}
#define qemu_cache_utils_init(envp) do { (void) (envp); } while (0)
#endif