diff options
authorAurelien Jarno <>2012-11-14 15:04:42 +0100
committerDoug Goldstein <>2012-11-21 15:30:28 -0600
commit41caa4d34851af8efa998399b1349bd73cb610b8 (patch)
tree916113488e15574f6415c3755f8bf6c3066ea771 /hw/mips_malta.c
parentnbd: fixes to read-only handling (diff)
mips/malta: fix CBUS UART interrupt pin
According to the MIPS Malta Developement Platform User's Manual, the i8259 interrupt controller is supposed to be connected to the hardware IRQ0, and the CBUS UART to the hardware interrupt 2. In QEMU they are both connected to hardware interrupt 0, the CBUS UART interrupt being wrong. This patch fixes that. It should be noted that the irq array in QEMU includes the software interrupts, hence env->irq[2] is the first hardware interrupt. Cc: Ralf Baechle <> Reviewed-by: Eric Johnson <> Signed-off-by: Aurelien Jarno <> (cherry picked from commit 68d001928b151a0c50f367c0bdca645b3d5e9ed3) Signed-off-by: Michael Tokarev <> (cherry picked from commit 3e2880465fd07832bc1e26a39d80cad6242b6cf0)
Diffstat (limited to 'hw/mips_malta.c')
1 files changed, 2 insertions, 1 deletions
diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index 4752bb286..337a2b4f7 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -854,7 +854,8 @@ void mips_malta_init (ram_addr_t ram_size,
be = 0;
/* FPGA */
- malta_fpga_init(system_memory, FPGA_ADDRESS, env->irq[2], serial_hds[2]);
+ /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */
+ malta_fpga_init(system_memory, FPGA_ADDRESS, env->irq[4], serial_hds[2]);
/* Load firmware in flash / BIOS. */
dinfo = drive_get(IF_PFLASH, 0, fl_idx);