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authorj_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162>2007-11-17 01:37:44 +0000
committerj_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162>2007-11-17 01:37:44 +0000
commitb172c56a6d849554f7e43adc95983a9d6c042689 (patch)
tree7a1043042fcad843192b301a7cbcd1aa774a8e43 /target-ppc
parentFix NaN handling for MIPS and HPPA. (diff)
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Always make all PowerPC exception definitions visible.
Always make the hypervisor timers available. Remove all TARGET_PPC64H checks, keeping a few if (0) tests for cases that cannot be properly handled with the current PowerPC CPU definition. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3656 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc')
-rw-r--r--target-ppc/cpu.h8
-rw-r--r--target-ppc/helper.c92
-rw-r--r--target-ppc/helper_regs.h7
-rw-r--r--target-ppc/translate_init.c2
4 files changed, 58 insertions, 51 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index d40bb4070..7705ca20c 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -180,20 +180,14 @@ enum {
/* Vectors 38 to 63 are reserved */
/* Exceptions defined in the PowerPC server specification */
POWERPC_EXCP_RESET = 64, /* System reset exception */
-#if defined(TARGET_PPC64) /* PowerPC 64 */
POWERPC_EXCP_DSEG = 65, /* Data segment exception */
POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
-#endif /* defined(TARGET_PPC64) */
-#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
-#endif /* defined(TARGET_PPC64H) */
POWERPC_EXCP_TRACE = 68, /* Trace exception */
-#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
-#endif /* defined(TARGET_PPC64H) */
POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
/* 40x specific exceptions */
POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
@@ -736,12 +730,10 @@ void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
uint32_t cpu_ppc_load_decr (CPUPPCState *env);
void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
-#if defined(TARGET_PPC64H)
uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
uint64_t cpu_ppc_load_purr (CPUPPCState *env);
void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
-#endif
uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
#if !defined(CONFIG_USER_ONLY)
diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index 268703cd4..8c187c7de 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -2134,13 +2134,21 @@ static always_inline void powerpc_excp (CPUState *env,
{
target_ulong msr, new_msr, vector;
int srr0, srr1, asrr0, asrr1;
-#if defined(TARGET_PPC64H)
- int lpes0, lpes1, lev;
-
- lpes0 = (env->spr[SPR_LPCR] >> 1) & 1;
- lpes1 = (env->spr[SPR_LPCR] >> 2) & 1;
+ int lpes0, lpes1;
+#if defined(TARGET_PPC64)
+ int lev;
#endif
+ if (0) {
+ /* XXX: find a suitable condition to enable the hypervisor mode */
+ lpes0 = (env->spr[SPR_LPCR] >> 1) & 1;
+ lpes1 = (env->spr[SPR_LPCR] >> 2) & 1;
+ } else {
+ /* Those values ensure we won't enter the hypervisor mode */
+ lpes0 = 0;
+ lpes1 = 1;
+ }
+
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n",
env->nip, excp, env->error_code);
@@ -2190,8 +2198,11 @@ static always_inline void powerpc_excp (CPUState *env,
}
new_msr &= ~((target_ulong)1 << MSR_RI);
new_msr &= ~((target_ulong)1 << MSR_ME);
-#if defined(TARGET_PPC64H)
- new_msr |= (target_ulong)1 << MSR_HV;
+#if defined(TARGET_PPC64)
+ if (0) {
+ /* XXX: find a suitable condition to enable the hypervisor mode */
+ new_msr |= (target_ulong)1 << MSR_HV;
+ }
#endif
/* XXX: should also have something loaded in DAR / DSISR */
switch (excp_model) {
@@ -2217,7 +2228,7 @@ static always_inline void powerpc_excp (CPUState *env,
}
#endif
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
+#if defined(TARGET_PPC64)
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
@@ -2230,7 +2241,7 @@ static always_inline void powerpc_excp (CPUState *env,
}
#endif
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
+#if defined(TARGET_PPC64)
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
@@ -2238,14 +2249,14 @@ static always_inline void powerpc_excp (CPUState *env,
goto store_next;
case POWERPC_EXCP_EXTERNAL: /* External input */
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
+#if defined(TARGET_PPC64)
if (lpes0 == 1)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
goto store_next;
case POWERPC_EXCP_ALIGN: /* Alignment exception */
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
+#if defined(TARGET_PPC64)
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
@@ -2267,7 +2278,7 @@ static always_inline void powerpc_excp (CPUState *env,
return;
}
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
+#if defined(TARGET_PPC64)
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
@@ -2284,7 +2295,7 @@ static always_inline void powerpc_excp (CPUState *env,
}
#endif
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
+#if defined(TARGET_PPC64)
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
@@ -2292,7 +2303,7 @@ static always_inline void powerpc_excp (CPUState *env,
break;
case POWERPC_EXCP_PRIV:
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
+#if defined(TARGET_PPC64)
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
@@ -2300,7 +2311,7 @@ static always_inline void powerpc_excp (CPUState *env,
break;
case POWERPC_EXCP_TRAP:
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
+#if defined(TARGET_PPC64)
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
@@ -2315,7 +2326,7 @@ static always_inline void powerpc_excp (CPUState *env,
goto store_current;
case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
+#if defined(TARGET_PPC64)
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
@@ -2336,7 +2347,7 @@ static always_inline void powerpc_excp (CPUState *env,
dump_syscall(env);
}
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
+#if defined(TARGET_PPC64)
lev = env->error_code;
if (lev == 1 || (lpes0 == 0 && lpes1 == 0))
new_msr |= (target_ulong)1 << MSR_HV;
@@ -2347,7 +2358,7 @@ static always_inline void powerpc_excp (CPUState *env,
goto store_current;
case POWERPC_EXCP_DECR: /* Decrementer exception */
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
+#if defined(TARGET_PPC64)
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
@@ -2434,65 +2445,69 @@ static always_inline void powerpc_excp (CPUState *env,
goto store_next;
case POWERPC_EXCP_RESET: /* System reset exception */
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
+#if defined(TARGET_PPC64)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
goto store_next;
-#if defined(TARGET_PPC64)
case POWERPC_EXCP_DSEG: /* Data segment exception */
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
+#if defined(TARGET_PPC64)
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
goto store_next;
case POWERPC_EXCP_ISEG: /* Instruction segment exception */
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
+#if defined(TARGET_PPC64)
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
goto store_next;
-#endif /* defined(TARGET_PPC64) */
-#if defined(TARGET_PPC64H)
case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
srr0 = SPR_HSRR0;
srr1 = SPR_HSRR1;
+#if defined(TARGET_PPC64)
new_msr |= (target_ulong)1 << MSR_HV;
- goto store_next;
#endif
+ goto store_next;
case POWERPC_EXCP_TRACE: /* Trace exception */
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
+#if defined(TARGET_PPC64)
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
goto store_next;
-#if defined(TARGET_PPC64H)
case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
srr0 = SPR_HSRR0;
srr1 = SPR_HSRR1;
+#if defined(TARGET_PPC64)
new_msr |= (target_ulong)1 << MSR_HV;
+#endif
goto store_next;
case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
srr0 = SPR_HSRR0;
srr1 = SPR_HSRR1;
+#if defined(TARGET_PPC64)
new_msr |= (target_ulong)1 << MSR_HV;
+#endif
goto store_next;
case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
srr0 = SPR_HSRR0;
srr1 = SPR_HSRR1;
+#if defined(TARGET_PPC64)
new_msr |= (target_ulong)1 << MSR_HV;
+#endif
goto store_next;
case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
srr0 = SPR_HSRR0;
srr1 = SPR_HSRR1;
+#if defined(TARGET_PPC64)
new_msr |= (target_ulong)1 << MSR_HV;
+#endif
goto store_next;
-#endif /* defined(TARGET_PPC64H) */
case POWERPC_EXCP_VPU: /* Vector unavailable exception */
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
+#if defined(TARGET_PPC64)
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
@@ -2519,7 +2534,7 @@ static always_inline void powerpc_excp (CPUState *env,
goto store_next;
case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
-#if defined(TARGET_PPC64H) /* XXX: check this */
+#if defined(TARGET_PPC64) /* XXX: check this */
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
@@ -2540,7 +2555,7 @@ static always_inline void powerpc_excp (CPUState *env,
break;
case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
-#if defined(TARGET_PPC64H) /* XXX: check this */
+#if defined(TARGET_PPC64) /* XXX: check this */
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
@@ -2561,7 +2576,7 @@ static always_inline void powerpc_excp (CPUState *env,
break;
case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
-#if defined(TARGET_PPC64H) /* XXX: check this */
+#if defined(TARGET_PPC64) /* XXX: check this */
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
@@ -2663,7 +2678,7 @@ static always_inline void powerpc_excp (CPUState *env,
goto store_next;
case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
new_msr &= ~((target_ulong)1 << MSR_RI);
-#if defined(TARGET_PPC64H)
+#if defined(TARGET_PPC64)
if (lpes1 == 0)
new_msr |= (target_ulong)1 << MSR_HV;
#endif
@@ -2769,7 +2784,7 @@ void do_interrupt (CPUState *env)
void ppc_hw_interrupt (CPUPPCState *env)
{
-#if defined(TARGET_PPC64H)
+#if defined(TARGET_PPC64)
int hdice;
#endif
@@ -2800,8 +2815,13 @@ void ppc_hw_interrupt (CPUPPCState *env)
return;
}
#endif
-#if defined(TARGET_PPC64H)
- hdice = env->spr[SPR_LPCR] & 1;
+#if defined(TARGET_PPC64)
+ if (0) {
+ /* XXX: find a suitable condition to enable the hypervisor mode */
+ hdice = env->spr[SPR_LPCR] & 1;
+ } else {
+ hdice = 0;
+ }
if ((msr_ee != 0 || msr_hv == 0 || msr_pr != 0) && hdice != 0) {
/* Hypervisor decrementer exception */
if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h
index c52ae9ebc..03c21c77f 100644
--- a/target-ppc/helper_regs.h
+++ b/target-ppc/helper_regs.h
@@ -60,7 +60,7 @@ static always_inline void hreg_swap_gpr_tgpr (CPUPPCState *env)
static always_inline void hreg_compute_mem_idx (CPUPPCState *env)
{
-#if defined (TARGET_PPC64H)
+#if defined (TARGET_PPC64)
/* Precompute MMU index */
if (msr_pr == 0 && msr_hv != 0)
env->mmu_idx = 2;
@@ -78,10 +78,7 @@ static always_inline void hreg_compute_hflags (CPUPPCState *env)
(1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) |
(1 << MSR_LE);
#if defined (TARGET_PPC64)
- hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF);
-#if defined (TARGET_PPC64H)
- hflags_mask |= 1ULL << MSR_HV;
-#endif
+ hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | (1ULL << MSR_HV);
#endif
hreg_compute_mem_idx(env);
env->hflags = env->msr & hflags_mask;
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index c6b744698..1a0890920 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -2609,9 +2609,7 @@ static void init_excp_970 (CPUPPCState *env)
env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
-#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
-#endif
env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;