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-rw-r--r--Makefile5
-rw-r--r--Makefile.target2
-rw-r--r--cpu-exec.c3
-rw-r--r--darwin-user/main.c4
-rw-r--r--def-helper.h4
-rw-r--r--hw/ac97.c67
-rw-r--r--hw/bitbang_i2c.c179
-rw-r--r--hw/es1370.c37
-rw-r--r--hw/esp.c16
-rw-r--r--hw/ide.c205
-rw-r--r--hw/marvell_88w8618_audio.c274
-rw-r--r--hw/musicpal.c734
-rw-r--r--hw/pc.c48
-rw-r--r--hw/pci-hotplug.c9
-rw-r--r--hw/ppc.c56
-rw-r--r--hw/ppc405_boards.c12
-rw-r--r--hw/ppc405_uc.c70
-rw-r--r--hw/ppc4xx_devs.c13
-rw-r--r--hw/ppc_oldworld.c6
-rw-r--r--hw/ppc_prep.c43
-rw-r--r--hw/slavio_intctl.c14
-rw-r--r--hw/sun4m.c15
-rw-r--r--hw/sun4m.h4
-rw-r--r--hw/vga.c90
-rw-r--r--hw/zaurus.c2
-rw-r--r--linux-user/main.c6
-rw-r--r--migration-exec.c5
-rw-r--r--monitor.c3
-rw-r--r--net.c2
-rw-r--r--osdep.h7
-rw-r--r--sdl.c3
-rw-r--r--sysemu.h15
-rw-r--r--target-alpha/exec.h9
-rw-r--r--target-alpha/op_helper.c20
-rw-r--r--target-alpha/translate.c90
-rw-r--r--target-ppc/cpu.h6
-rw-r--r--target-ppc/exec.h8
-rw-r--r--target-ppc/helper.c361
-rw-r--r--target-ppc/helper_regs.h10
-rw-r--r--target-ppc/op_helper.c150
-rw-r--r--target-ppc/translate.c378
-rw-r--r--target-ppc/translate_init.c4
-rw-r--r--target-sparc/cpu.h65
-rw-r--r--target-sparc/helper.c2
-rw-r--r--target-sparc/translate.c2
-rw-r--r--tcg/arm/tcg-target.c42
-rw-r--r--tcg/arm/tcg-target.h1
-rw-r--r--vl.c18
-rw-r--r--vnc.c9
49 files changed, 1791 insertions, 1337 deletions
diff --git a/Makefile b/Makefile
index 2b2288763..0ec377845 100644
--- a/Makefile
+++ b/Makefile
@@ -89,7 +89,7 @@ endif
# CPUs and machines.
obj-y = $(block-obj-y)
-obj-y += readline.o console.o
+obj-y += readline.o console.o host-utils.o
obj-y += irq.o ptimer.o
obj-y += i2c.o smbus.o smbus_eeprom.o max7310.o max111x.o wm8750.o
@@ -266,8 +266,9 @@ endif
test speed: all
$(MAKE) -C tests $@
+.PHONY: TAGS
TAGS:
- etags *.[ch] tests/*.[ch] block/*.[ch] hw/*.[ch]
+ find "$(SRC_PATH)" -name '*.[hc]' -print0 | xargs -0 etags
cscope:
rm -f ./cscope.*
diff --git a/Makefile.target b/Makefile.target
index 6c682fab2..c6e6de839 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -314,7 +314,7 @@ obj-arm-y += omap2.o omap_dss.o soc_dma.o
obj-arm-y += omap_sx1.o palm.o tsc210x.o
obj-arm-y += nseries.o blizzard.o onenand.o vga.o cbus.o tusb6010.o usb-musb.o
obj-arm-y += mst_fpga.o mainstone.o
-obj-arm-y += musicpal.o pflash_cfi02.o
+obj-arm-y += musicpal.o pflash_cfi02.o bitbang_i2c.o marvell_88w8618_audio.o
obj-arm-y += framebuffer.o
obj-arm-y += syborg.o syborg_fb.o syborg_interrupt.o syborg_keyboard.o
obj-arm-y += syborg_serial.o syborg_timer.o syborg_pointer.o syborg_rtc.o
diff --git a/cpu-exec.c b/cpu-exec.c
index 8f3f84c12..7275fd194 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -492,9 +492,6 @@ int cpu_exec(CPUState *env1)
env->exception_index = env->interrupt_index;
do_interrupt(env);
env->interrupt_index = 0;
-#if !defined(CONFIG_USER_ONLY)
- cpu_check_irqs(env);
-#endif
next_tb = 0;
}
} else if (interrupt_request & CPU_INTERRUPT_TIMER) {
diff --git a/darwin-user/main.c b/darwin-user/main.c
index 8e993da37..9f0e0149f 100644
--- a/darwin-user/main.c
+++ b/darwin-user/main.c
@@ -156,7 +156,7 @@ void cpu_loop(CPUPPCState *env)
/* To deal with multiple qemu header version as host for the darwin-user code */
# define DAR SPR_DAR
#endif
- EXCP_DUMP(env, "Invalid data memory access: 0x" ADDRX "\n",
+ EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
env->spr[SPR_DAR]);
/* Handle this via the gdb */
gdb_handlesig (env, SIGSEGV);
@@ -165,7 +165,7 @@ void cpu_loop(CPUPPCState *env)
queue_signal(info.si_signo, &info);
break;
case POWERPC_EXCP_ISI: /* Instruction storage exception */
- EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" ADDRX "\n",
+ EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx "\n",
env->spr[SPR_DAR]);
/* Handle this via the gdb */
gdb_handlesig (env, SIGSEGV);
diff --git a/def-helper.h b/def-helper.h
index d57ea4d5a..8a88c5ba7 100644
--- a/def-helper.h
+++ b/def-helper.h
@@ -60,13 +60,13 @@
#define dh_retvar_decl0_void void
#define dh_retvar_decl0_i32 TCGv_i32 retval
#define dh_retvar_decl0_i64 TCGv_i64 retval
-#define dh_retvar_decl0_ptr TCGv_iptr retval
+#define dh_retvar_decl0_ptr TCGv_ptr retval
#define dh_retvar_decl0(t) glue(dh_retvar_decl0_, dh_alias(t))
#define dh_retvar_decl_void
#define dh_retvar_decl_i32 TCGv_i32 retval,
#define dh_retvar_decl_i64 TCGv_i64 retval,
-#define dh_retvar_decl_ptr TCGv_iptr retval,
+#define dh_retvar_decl_ptr TCGv_ptr retval,
#define dh_retvar_decl(t) glue(dh_retvar_decl_, dh_alias(t))
#define dh_retvar_void TCG_CALL_DUMMY_ARG
diff --git a/hw/ac97.c b/hw/ac97.c
index 6c818c9cc..3c70d8c18 100644
--- a/hw/ac97.c
+++ b/hw/ac97.c
@@ -147,7 +147,7 @@ typedef struct AC97BusMasterRegs {
} AC97BusMasterRegs;
typedef struct AC97LinkState {
- PCIDevice *pci_dev;
+ PCIDevice dev;
QEMUSoundCard card;
uint32_t glob_cnt;
uint32_t glob_sta;
@@ -175,11 +175,6 @@ enum {
#define dolog(...)
#endif
-typedef struct PCIAC97LinkState {
- PCIDevice dev;
- AC97LinkState ac97;
-} PCIAC97LinkState;
-
#define MKREGS(prefix, start) \
enum { \
prefix ## _BDBAR = start, \
@@ -278,12 +273,12 @@ static void update_sr (AC97LinkState *s, AC97BusMasterRegs *r, uint32_t new_sr)
if (level) {
s->glob_sta |= masks[r - s->bm_regs];
dolog ("set irq level=1\n");
- qemu_set_irq (s->pci_dev->irq[0], 1);
+ qemu_set_irq (s->dev.irq[0], 1);
}
else {
s->glob_sta &= ~masks[r - s->bm_regs];
dolog ("set irq level=0\n");
- qemu_set_irq (s->pci_dev->irq[0], 0);
+ qemu_set_irq (s->dev.irq[0], 0);
}
}
@@ -578,8 +573,7 @@ static void mixer_reset (AC97LinkState *s)
*/
static uint32_t nam_readb (void *opaque, uint32_t addr)
{
- PCIAC97LinkState *d = opaque;
- AC97LinkState *s = &d->ac97;
+ AC97LinkState *s = opaque;
dolog ("U nam readb %#x\n", addr);
s->cas = 0;
return ~0U;
@@ -587,8 +581,7 @@ static uint32_t nam_readb (void *opaque, uint32_t addr)
static uint32_t nam_readw (void *opaque, uint32_t addr)
{
- PCIAC97LinkState *d = opaque;
- AC97LinkState *s = &d->ac97;
+ AC97LinkState *s = opaque;
uint32_t val = ~0U;
uint32_t index = addr - s->base[0];
s->cas = 0;
@@ -598,8 +591,7 @@ static uint32_t nam_readw (void *opaque, uint32_t addr)
static uint32_t nam_readl (void *opaque, uint32_t addr)
{
- PCIAC97LinkState *d = opaque;
- AC97LinkState *s = &d->ac97;
+ AC97LinkState *s = opaque;
dolog ("U nam readl %#x\n", addr);
s->cas = 0;
return ~0U;
@@ -611,16 +603,14 @@ static uint32_t nam_readl (void *opaque, uint32_t addr)
*/
static void nam_writeb (void *opaque, uint32_t addr, uint32_t val)
{
- PCIAC97LinkState *d = opaque;
- AC97LinkState *s = &d->ac97;
+ AC97LinkState *s = opaque;
dolog ("U nam writeb %#x <- %#x\n", addr, val);
s->cas = 0;
}
static void nam_writew (void *opaque, uint32_t addr, uint32_t val)
{
- PCIAC97LinkState *d = opaque;
- AC97LinkState *s = &d->ac97;
+ AC97LinkState *s = opaque;
uint32_t index = addr - s->base[0];
s->cas = 0;
switch (index) {
@@ -711,8 +701,7 @@ static void nam_writew (void *opaque, uint32_t addr, uint32_t val)
static void nam_writel (void *opaque, uint32_t addr, uint32_t val)
{
- PCIAC97LinkState *d = opaque;
- AC97LinkState *s = &d->ac97;
+ AC97LinkState *s = opaque;
dolog ("U nam writel %#x <- %#x\n", addr, val);
s->cas = 0;
}
@@ -723,8 +712,7 @@ static void nam_writel (void *opaque, uint32_t addr, uint32_t val)
*/
static uint32_t nabm_readb (void *opaque, uint32_t addr)
{
- PCIAC97LinkState *d = opaque;
- AC97LinkState *s = &d->ac97;
+ AC97LinkState *s = opaque;
AC97BusMasterRegs *r = NULL;
uint32_t index = addr - s->base[1];
uint32_t val = ~0U;
@@ -779,8 +767,7 @@ static uint32_t nabm_readb (void *opaque, uint32_t addr)
static uint32_t nabm_readw (void *opaque, uint32_t addr)
{
- PCIAC97LinkState *d = opaque;
- AC97LinkState *s = &d->ac97;
+ AC97LinkState *s = opaque;
AC97BusMasterRegs *r = NULL;
uint32_t index = addr - s->base[1];
uint32_t val = ~0U;
@@ -809,8 +796,7 @@ static uint32_t nabm_readw (void *opaque, uint32_t addr)
static uint32_t nabm_readl (void *opaque, uint32_t addr)
{
- PCIAC97LinkState *d = opaque;
- AC97LinkState *s = &d->ac97;
+ AC97LinkState *s = opaque;
AC97BusMasterRegs *r = NULL;
uint32_t index = addr - s->base[1];
uint32_t val = ~0U;
@@ -860,8 +846,7 @@ static uint32_t nabm_readl (void *opaque, uint32_t addr)
*/
static void nabm_writeb (void *opaque, uint32_t addr, uint32_t val)
{
- PCIAC97LinkState *d = opaque;
- AC97LinkState *s = &d->ac97;
+ AC97LinkState *s = opaque;
AC97BusMasterRegs *r = NULL;
uint32_t index = addr - s->base[1];
switch (index) {
@@ -917,8 +902,7 @@ static void nabm_writeb (void *opaque, uint32_t addr, uint32_t val)
static void nabm_writew (void *opaque, uint32_t addr, uint32_t val)
{
- PCIAC97LinkState *d = opaque;
- AC97LinkState *s = &d->ac97;
+ AC97LinkState *s = opaque;
AC97BusMasterRegs *r = NULL;
uint32_t index = addr - s->base[1];
switch (index) {
@@ -938,8 +922,7 @@ static void nabm_writew (void *opaque, uint32_t addr, uint32_t val)
static void nabm_writel (void *opaque, uint32_t addr, uint32_t val)
{
- PCIAC97LinkState *d = opaque;
- AC97LinkState *s = &d->ac97;
+ AC97LinkState *s = opaque;
AC97BusMasterRegs *r = NULL;
uint32_t index = addr - s->base[1];
switch (index) {
@@ -1190,7 +1173,7 @@ static void ac97_save (QEMUFile *f, void *opaque)
uint8_t active[LAST_INDEX];
AC97LinkState *s = opaque;
- pci_device_save (s->pci_dev, f);
+ pci_device_save (&s->dev, f);
qemu_put_be32s (f, &s->glob_cnt);
qemu_put_be32s (f, &s->glob_sta);
@@ -1227,7 +1210,7 @@ static int ac97_load (QEMUFile *f, void *opaque, int version_id)
if (version_id != 2)
return -EINVAL;
- ret = pci_device_load (s->pci_dev, f);
+ ret = pci_device_load (&s->dev, f);
if (ret)
return ret;
@@ -1269,8 +1252,8 @@ static int ac97_load (QEMUFile *f, void *opaque, int version_id)
static void ac97_map (PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
{
- PCIAC97LinkState *d = (PCIAC97LinkState *) pci_dev;
- AC97LinkState *s = &d->ac97;
+ AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, pci_dev);
+ PCIDevice *d = &s->dev;
if (!region_num) {
s->base[0] = addr;
@@ -1310,11 +1293,9 @@ static void ac97_on_reset (void *opaque)
static void ac97_initfn (PCIDevice *dev)
{
- PCIAC97LinkState *d = DO_UPCAST (PCIAC97LinkState, dev, dev);
- AC97LinkState *s = &d->ac97;
- uint8_t *c = d->dev.config;
+ AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, dev);
+ uint8_t *c = s->dev.config;
- s->pci_dev = &d->dev;
pci_config_set_vendor_id (c, PCI_VENDOR_ID_INTEL); /* ro */
pci_config_set_device_id (c, PCI_DEVICE_ID_INTEL_82801AA_5); /* ro */
@@ -1350,8 +1331,8 @@ static void ac97_initfn (PCIDevice *dev)
c[0x3c] = 0x00; /* intr_ln interrupt line rw */
c[0x3d] = 0x01; /* intr_pn interrupt pin ro */
- pci_register_bar (&d->dev, 0, 256 * 4, PCI_ADDRESS_SPACE_IO, ac97_map);
- pci_register_bar (&d->dev, 1, 64 * 4, PCI_ADDRESS_SPACE_IO, ac97_map);
+ pci_register_bar (&s->dev, 0, 256 * 4, PCI_ADDRESS_SPACE_IO, ac97_map);
+ pci_register_bar (&s->dev, 1, 64 * 4, PCI_ADDRESS_SPACE_IO, ac97_map);
register_savevm ("ac97", 0, 2, ac97_save, ac97_load, s);
qemu_register_reset (ac97_on_reset, s);
AUD_register_card ("ac97", &s->card);
@@ -1367,7 +1348,7 @@ int ac97_init (PCIBus *bus)
static PCIDeviceInfo ac97_info = {
.qdev.name = "AC97",
.qdev.desc = "Intel 82801AA AC97 Audio",
- .qdev.size = sizeof (PCIAC97LinkState),
+ .qdev.size = sizeof (AC97LinkState),
.init = ac97_initfn,
};
diff --git a/hw/bitbang_i2c.c b/hw/bitbang_i2c.c
new file mode 100644
index 000000000..9ab04cc42
--- /dev/null
+++ b/hw/bitbang_i2c.c
@@ -0,0 +1,179 @@
+/*
+ * Bit-Bang i2c emulation extracted from
+ * Marvell MV88W8618 / Freecom MusicPal emulation.
+ *
+ * Copyright (c) 2008 Jan Kiszka
+ *
+ * This code is licenced under the GNU GPL v2.
+ */
+#include "hw.h"
+#include "i2c.h"
+#include "sysbus.h"
+
+typedef enum bitbang_i2c_state {
+ STOPPED = 0,
+ INITIALIZING,
+ SENDING_BIT7,
+ SENDING_BIT6,
+ SENDING_BIT5,
+ SENDING_BIT4,
+ SENDING_BIT3,
+ SENDING_BIT2,
+ SENDING_BIT1,
+ SENDING_BIT0,
+ WAITING_FOR_ACK,
+ RECEIVING_BIT7,
+ RECEIVING_BIT6,
+ RECEIVING_BIT5,
+ RECEIVING_BIT4,
+ RECEIVING_BIT3,
+ RECEIVING_BIT2,
+ RECEIVING_BIT1,
+ RECEIVING_BIT0,
+ SENDING_ACK
+} bitbang_i2c_state;
+
+typedef struct bitbang_i2c_interface {
+ SysBusDevice busdev;
+ i2c_bus *bus;
+ bitbang_i2c_state state;
+ int last_data;
+ int last_clock;
+ uint8_t buffer;
+ int current_addr;
+ qemu_irq out;
+} bitbang_i2c_interface;
+
+static void bitbang_i2c_enter_stop(bitbang_i2c_interface *i2c)
+{
+ if (i2c->current_addr >= 0)
+ i2c_end_transfer(i2c->bus);
+ i2c->current_addr = -1;
+ i2c->state = STOPPED;
+}
+
+static void bitbang_i2c_gpio_set(void *opaque, int irq, int level)
+{
+ bitbang_i2c_interface *i2c = opaque;
+ int data;
+ int clock;
+ int data_goes_up;
+ int data_goes_down;
+ int clock_goes_up;
+ int clock_goes_down;
+
+ /* get pins states */
+ data = i2c->last_data;
+ clock = i2c->last_clock;
+
+ if (irq == 0)
+ data = level;
+ if (irq == 1)
+ clock = level;
+
+ /* compute pins changes */
+ data_goes_up = data == 1 && i2c->last_data == 0;
+ data_goes_down = data == 0 && i2c->last_data == 1;
+ clock_goes_up = clock == 1 && i2c->last_clock == 0;
+ clock_goes_down = clock == 0 && i2c->last_clock == 1;
+
+ if (data_goes_up == 0 && data_goes_down == 0 &&
+ clock_goes_up == 0 && clock_goes_down == 0)
+ return;
+
+ if (!i2c)
+ return;
+
+ if ((RECEIVING_BIT7 > i2c->state && i2c->state > RECEIVING_BIT0)
+ || i2c->state == WAITING_FOR_ACK)
+ qemu_set_irq(i2c->out, 0);
+
+ switch (i2c->state) {
+ case STOPPED:
+ if (data_goes_down && clock == 1)
+ i2c->state = INITIALIZING;
+ break;
+
+ case INITIALIZING:
+ if (clock_goes_down && data == 0)
+ i2c->state = SENDING_BIT7;
+ else
+ bitbang_i2c_enter_stop(i2c);
+ break;
+
+ case SENDING_BIT7 ... SENDING_BIT0:
+ if (clock_goes_down) {
+ i2c->buffer = (i2c->buffer << 1) | data;
+ /* will end up in WAITING_FOR_ACK */
+ i2c->state++;
+ } else if (data_goes_up && clock == 1)
+ bitbang_i2c_enter_stop(i2c);
+ break;
+
+ case WAITING_FOR_ACK:
+ if (clock_goes_down) {
+ if (i2c->current_addr < 0) {
+ i2c->current_addr = i2c->buffer;
+ i2c_start_transfer(i2c->bus, (i2c->current_addr & 0xfe) / 2,
+ i2c->buffer & 1);
+ } else
+ i2c_send(i2c->bus, i2c->buffer);
+ if (i2c->current_addr & 1) {
+ i2c->state = RECEIVING_BIT7;
+ i2c->buffer = i2c_recv(i2c->bus);
+ } else
+ i2c->state = SENDING_BIT7;
+ } else if (data_goes_up && clock == 1)
+ bitbang_i2c_enter_stop(i2c);
+ break;
+
+ case RECEIVING_BIT7 ... RECEIVING_BIT0:
+ qemu_set_irq(i2c->out, i2c->buffer >> 7);
+ if (clock_goes_down) {
+ /* will end up in SENDING_ACK */
+ i2c->state++;
+ i2c->buffer <<= 1;
+ } else if (data_goes_up && clock == 1)
+ bitbang_i2c_enter_stop(i2c);
+ break;
+
+ case SENDING_ACK:
+ if (clock_goes_down) {
+ i2c->state = RECEIVING_BIT7;
+ if (data == 0)
+ i2c->buffer = i2c_recv(i2c->bus);
+ else
+ i2c_nack(i2c->bus);
+ } else if (data_goes_up && clock == 1)
+ bitbang_i2c_enter_stop(i2c);
+ break;
+ }
+
+ i2c->last_data = data;
+ i2c->last_clock = clock;
+}
+
+static void bitbang_i2c_init(SysBusDevice *dev)
+{
+ bitbang_i2c_interface *s = FROM_SYSBUS(bitbang_i2c_interface, dev);
+ i2c_bus *bus;
+
+ sysbus_init_mmio(dev, 0x0, 0);
+
+ bus = i2c_init_bus(&dev->qdev, "i2c");
+ s->bus = bus;
+
+ s->last_data = 1;
+ s->last_clock = 1;
+
+ qdev_init_gpio_in(&dev->qdev, bitbang_i2c_gpio_set, 2);
+ qdev_init_gpio_out(&dev->qdev, &s->out, 1);
+}
+
+static void bitbang_i2c_register(void)
+{
+ sysbus_register_dev("bitbang_i2c",
+ sizeof(bitbang_i2c_interface), bitbang_i2c_init);
+}
+
+device_init(bitbang_i2c_register)
diff --git a/hw/es1370.c b/hw/es1370.c
index 5c9af0e8e..305b6e738 100644
--- a/hw/es1370.c
+++ b/hw/es1370.c
@@ -266,8 +266,7 @@ struct chan {
};
typedef struct ES1370State {
- PCIDevice *pci_dev;
-
+ PCIDevice dev;
QEMUSoundCard card;
struct chan chan[NB_CHANNELS];
SWVoiceOut *dac_voice[2];
@@ -280,11 +279,6 @@ typedef struct ES1370State {
uint32_t sctl;
} ES1370State;
-typedef struct PCIES1370State {
- PCIDevice dev;
- ES1370State es1370;
-} PCIES1370State;
-
struct chan_bits {
uint32_t ctl_en;
uint32_t stat_int;
@@ -327,7 +321,7 @@ static void es1370_update_status (ES1370State *s, uint32_t new_status)
else {
s->status = new_status & ~STAT_INTR;
}
- qemu_set_irq (s->pci_dev->irq[0], !!level);
+ qemu_set_irq (s->dev.irq[0], !!level);
}
static void es1370_reset (ES1370State *s)
@@ -353,7 +347,7 @@ static void es1370_reset (ES1370State *s)
s->dac_voice[i] = NULL;
}
}
- qemu_irq_lower (s->pci_dev->irq[0]);
+ qemu_irq_lower (s->dev.irq[0]);
}
static void es1370_maybe_lower_irq (ES1370State *s, uint32_t sctl)
@@ -915,8 +909,7 @@ static void es1370_adc_callback (void *opaque, int avail)
static void es1370_map (PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
{
- PCIES1370State *d = (PCIES1370State *) pci_dev;
- ES1370State *s = &d->es1370;
+ ES1370State *s = DO_UPCAST (ES1370State, dev, pci_dev);
(void) region_num;
(void) size;
@@ -936,7 +929,7 @@ static void es1370_save (QEMUFile *f, void *opaque)
ES1370State *s = opaque;
size_t i;
- pci_device_save (s->pci_dev, f);
+ pci_device_save (&s->dev, f);
for (i = 0; i < NB_CHANNELS; ++i) {
struct chan *d = &s->chan[i];
qemu_put_be32s (f, &d->shift);
@@ -962,7 +955,7 @@ static int es1370_load (QEMUFile *f, void *opaque, int version_id)
if (version_id != 2)
return -EINVAL;
- ret = pci_device_load (s->pci_dev, f);
+ ret = pci_device_load (&s->dev, f);
if (ret)
return ret;
@@ -1005,11 +998,10 @@ static void es1370_on_reset (void *opaque)
es1370_reset (s);
}
-static void es1370_initfn(PCIDevice *dev)
+static void es1370_initfn (PCIDevice *dev)
{
- PCIES1370State *d = DO_UPCAST(PCIES1370State, dev, dev);
- ES1370State *s = &d->es1370;
- uint8_t *c = d->dev.config;
+ ES1370State *s = DO_UPCAST (ES1370State, dev, dev);
+ uint8_t *c = s->dev.config;
pci_config_set_vendor_id (c, PCI_VENDOR_ID_ENSONIQ);
pci_config_set_device_id (c, PCI_DEVICE_ID_ENSONIQ_ES1370);
@@ -1035,10 +1027,7 @@ static void es1370_initfn(PCIDevice *dev)
c[0x3e] = 0x0c;
c[0x3f] = 0x80;
- s = &d->es1370;
- s->pci_dev = &d->dev;
-
- pci_register_bar (&d->dev, 0, 256, PCI_ADDRESS_SPACE_IO, es1370_map);
+ pci_register_bar (&s->dev, 0, 256, PCI_ADDRESS_SPACE_IO, es1370_map);
register_savevm ("es1370", 0, 2, es1370_save, es1370_load, s);
qemu_register_reset (es1370_on_reset, s);
@@ -1048,18 +1037,18 @@ static void es1370_initfn(PCIDevice *dev)
int es1370_init (PCIBus *bus)
{
- pci_create_simple(bus, -1, "ES1370");
+ pci_create_simple (bus, -1, "ES1370");
return 0;
}
static PCIDeviceInfo es1370_info = {
.qdev.name = "ES1370",
.qdev.desc = "ENSONIQ AudioPCI ES1370",
- .qdev.size = sizeof (PCIES1370State),
+ .qdev.size = sizeof (ES1370State),
.init = es1370_initfn,
};
-static void es1370_register(void)
+static void es1370_register (void)
{
pci_qdev_register (&es1370_info);
}
diff --git a/hw/esp.c b/hw/esp.c
index 146a73a0e..53310224f 100644
--- a/hw/esp.c
+++ b/hw/esp.c
@@ -115,7 +115,9 @@ struct ESPState {
#define CMD_TI 0x10
#define CMD_ICCS 0x11
#define CMD_MSGACC 0x12
+#define CMD_PAD 0x18
#define CMD_SATN 0x1a
+#define CMD_SEL 0x41
#define CMD_SELATN 0x42
#define CMD_SELATNS 0x43
#define CMD_ENSEL 0x44
@@ -530,15 +532,25 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
s->rregs[ESP_RINTR] = INTR_DC;
s->rregs[ESP_RSEQ] = 0;
break;
+ case CMD_PAD:
+ DPRINTF("Transfer padding (%2.2x)\n", val);
+ s->rregs[ESP_RSTAT] = STAT_TC;
+ s->rregs[ESP_RINTR] = INTR_FC;
+ s->rregs[ESP_RSEQ] = 0;
+ break;
case CMD_SATN:
DPRINTF("Set ATN (%2.2x)\n", val);
break;
+ case CMD_SEL:
+ DPRINTF("Select without ATN (%2.2x)\n", val);
+ handle_satn(s);
+ break;
case CMD_SELATN:
- DPRINTF("Set ATN (%2.2x)\n", val);
+ DPRINTF("Select with ATN (%2.2x)\n", val);
handle_satn(s);
break;
case CMD_SELATNS:
- DPRINTF("Set ATN & stop (%2.2x)\n", val);
+ DPRINTF("Select with ATN & stop (%2.2x)\n", val);
handle_satn_stop(s);
break;
case CMD_ENSEL:
diff --git a/hw/ide.c b/hw/ide.c
index 1e38ae3ea..637b0821a 100644
--- a/hw/ide.c
+++ b/hw/ide.c
@@ -372,6 +372,28 @@
#define SENSE_ILLEGAL_REQUEST 5
#define SENSE_UNIT_ATTENTION 6
+#define SMART_READ_DATA 0xd0
+#define SMART_READ_THRESH 0xd1
+#define SMART_ATTR_AUTOSAVE 0xd2
+#define SMART_SAVE_ATTR 0xd3
+#define SMART_EXECUTE_OFFLINE 0xd4
+#define SMART_READ_LOG 0xd5
+#define SMART_WRITE_LOG 0xd6
+#define SMART_ENABLE 0xd8
+#define SMART_DISABLE 0xd9
+#define SMART_STATUS 0xda
+
+static int smart_attributes[][5] = {
+ /* id, flags, val, wrst, thrsh */
+ { 0x01, 0x03, 0x64, 0x64, 0x06}, /* raw read */
+ { 0x03, 0x03, 0x64, 0x64, 0x46}, /* spin up */
+ { 0x04, 0x02, 0x64, 0x64, 0x14}, /* start stop count */
+ { 0x05, 0x03, 0x64, 0x64, 0x36}, /* remapped sectors */
+ { 0x00, 0x00, 0x00, 0x00, 0x00}
+};
+
+
+
struct IDEState;
typedef void EndTransferFunc(struct IDEState *);
@@ -444,6 +466,13 @@ typedef struct IDEState {
int media_changed;
/* for pmac */
int is_read;
+ /* SMART */
+ uint8_t smart_enabled;
+ uint8_t smart_autosave;
+ int smart_errors;
+ uint8_t smart_selftest_count;
+ uint8_t *smart_selftest_data;
+
} IDEState;
/* XXX: DVDs that could fit on a CD will be reported as a CD */
@@ -594,14 +623,18 @@ static void ide_identify(IDEState *s)
put_le16(p + 68, 120);
put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
put_le16(p + 81, 0x16); /* conforms to ata5 */
- put_le16(p + 82, (1 << 14));
+ /* 14=NOP supported, 0=SMART supported */
+ put_le16(p + 82, (1 << 14) | 1);
/* 13=flush_cache_ext,12=flush_cache,10=lba48 */
put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
- put_le16(p + 84, (1 << 14));
- put_le16(p + 85, (1 << 14));
+ /* 14=set to 1, 1=SMART self test, 0=SMART error logging */
+ put_le16(p + 84, (1 << 14) | 0);
+ /* 14 = NOP supported, 0=SMART feature set enabled */
+ put_le16(p + 85, (1 << 14) | 1);
/* 13=flush_cache_ext,12=flush_cache,10=lba48 */
put_le16(p + 86, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
- put_le16(p + 87, (1 << 14));
+ /* 14=set to 1, 1=smart self test, 0=smart error logging */
+ put_le16(p + 87, (1 << 14) | 0);
put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
put_le16(p + 93, 1 | (1 << 14) | 0x2000);
put_le16(p + 100, s->nb_sectors);
@@ -2567,6 +2600,162 @@ static void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s);
break;
+
+ case WIN_SMART:
+ if (s->is_cdrom)
+ goto abort_cmd;
+ if (s->hcyl != 0xc2 || s->lcyl != 0x4f)
+ goto abort_cmd;
+ if (!s->smart_enabled && s->feature != SMART_ENABLE)
+ goto abort_cmd;
+ switch (s->feature) {
+ case SMART_DISABLE:
+ s->smart_enabled = 0;
+ s->status = READY_STAT | SEEK_STAT;
+ ide_set_irq(s);
+ break;
+ case SMART_ENABLE:
+ s->smart_enabled = 1;
+ s->status = READY_STAT | SEEK_STAT;
+ ide_set_irq(s);
+ break;
+ case SMART_ATTR_AUTOSAVE:
+ switch (s->sector) {
+ case 0x00:
+ s->smart_autosave = 0;
+ break;
+ case 0xf1:
+ s->smart_autosave = 1;
+ break;
+ default:
+ goto abort_cmd;
+ }
+ s->status = READY_STAT | SEEK_STAT;
+ ide_set_irq(s);
+ break;
+ case SMART_STATUS:
+ if (!s->smart_errors) {
+ s->hcyl = 0xc2;
+ s->lcyl = 0x4f;
+ } else {
+ s->hcyl = 0x2c;
+ s->lcyl = 0xf4;
+ }
+ s->status = READY_STAT | SEEK_STAT;
+ ide_set_irq(s);
+ break;
+ case SMART_READ_THRESH:
+ memset(s->io_buffer, 0, 0x200);
+ s->io_buffer[0] = 0x01; /* smart struct version */
+ for (n=0; n<30; n++) {
+ if (smart_attributes[n][0] == 0)
+ break;
+ s->io_buffer[2+0+(n*12)] = smart_attributes[n][0];
+ s->io_buffer[2+1+(n*12)] = smart_attributes[n][4];
+ }
+ for (n=0; n<511; n++) /* checksum */
+ s->io_buffer[511] += s->io_buffer[n];
+ s->io_buffer[511] = 0x100 - s->io_buffer[511];
+ s->status = READY_STAT | SEEK_STAT;
+ ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
+ ide_set_irq(s);
+ break;
+ case SMART_READ_DATA:
+ memset(s->io_buffer, 0, 0x200);
+ s->io_buffer[0] = 0x01; /* smart struct version */
+ for (n=0; n<30; n++) {
+ if (smart_attributes[n][0] == 0)
+ break;
+ s->io_buffer[2+0+(n*12)] = smart_attributes[n][0];
+ s->io_buffer[2+1+(n*12)] = smart_attributes[n][1];
+ s->io_buffer[2+3+(n*12)] = smart_attributes[n][2];
+ s->io_buffer[2+4+(n*12)] = smart_attributes[n][3];
+ }
+ s->io_buffer[362] = 0x02 | (s->smart_autosave?0x80:0x00);
+ if (s->smart_selftest_count == 0) {
+ s->io_buffer[363] = 0;
+ } else {
+ s->io_buffer[363] =
+ s->smart_selftest_data[3 +
+ (s->smart_selftest_count - 1) *
+ 24];
+ }
+ s->io_buffer[364] = 0x20;
+ s->io_buffer[365] = 0x01;
+ /* offline data collection capacity: execute + self-test*/
+ s->io_buffer[367] = (1<<4 | 1<<3 | 1);
+ s->io_buffer[368] = 0x03; /* smart capability (1) */
+ s->io_buffer[369] = 0x00; /* smart capability (2) */
+ s->io_buffer[370] = 0x01; /* error logging supported */
+ s->io_buffer[372] = 0x02; /* minutes for poll short test */
+ s->io_buffer[373] = 0x36; /* minutes for poll ext test */
+ s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
+
+ for (n=0; n<511; n++)
+ s->io_buffer[511] += s->io_buffer[n];
+ s->io_buffer[511] = 0x100 - s->io_buffer[511];
+ s->status = READY_STAT | SEEK_STAT;
+ ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
+ ide_set_irq(s);
+ break;
+ case SMART_READ_LOG:
+ switch (s->sector) {
+ case 0x01: /* summary smart error log */
+ memset(s->io_buffer, 0, 0x200);
+ s->io_buffer[0] = 0x01;
+ s->io_buffer[1] = 0x00; /* no error entries */
+ s->io_buffer[452] = s->smart_errors & 0xff;
+ s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
+
+ for (n=0; n<511; n++)
+ s->io_buffer[511] += s->io_buffer[n];
+ s->io_buffer[511] = 0x100 - s->io_buffer[511];
+ break;
+ case 0x06: /* smart self test log */
+ memset(s->io_buffer, 0, 0x200);
+ s->io_buffer[0] = 0x01;
+ if (s->smart_selftest_count == 0) {
+ s->io_buffer[508] = 0;
+ } else {
+ s->io_buffer[508] = s->smart_selftest_count;
+ for (n=2; n<506; n++)
+ s->io_buffer[n] = s->smart_selftest_data[n];
+ }
+ for (n=0; n<511; n++)
+ s->io_buffer[511] += s->io_buffer[n];
+ s->io_buffer[511] = 0x100 - s->io_buffer[511];
+ break;
+ default:
+ goto abort_cmd;
+ }
+ s->status = READY_STAT | SEEK_STAT;
+ ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
+ ide_set_irq(s);
+ break;
+ case SMART_EXECUTE_OFFLINE:
+ switch (s->sector) {
+ case 0: /* off-line routine */
+ case 1: /* short self test */
+ case 2: /* extended self test */
+ s->smart_selftest_count++;
+ if(s->smart_selftest_count > 21)
+ s->smart_selftest_count = 0;
+ n = 2 + (s->smart_selftest_count - 1) * 24;
+ s->smart_selftest_data[n] = s->sector;
+ s->smart_selftest_data[n+1] = 0x00; /* OK and finished */
+ s->smart_selftest_data[n+2] = 0x34; /* hour count lsb */
+ s->smart_selftest_data[n+3] = 0x12; /* hour count msb */
+ s->status = READY_STAT | SEEK_STAT;
+ ide_set_irq(s);
+ break;
+ default:
+ goto abort_cmd;
+ }
+ break;
+ default:
+ goto abort_cmd;
+ }
+ break;
default:
abort_cmd:
ide_abort_command(s);
@@ -2828,7 +3017,13 @@ static void ide_init2(IDEState *ide_state,
s->heads = heads;
s->sectors = secs;
s->nb_sectors = nb_sectors;
-
+ /* The SMART values should be preserved across power cycles
+ but they aren't. */
+ s->smart_enabled = 1;
+ s->smart_autosave = 1;
+ s->smart_errors = 0;
+ s->smart_selftest_count = 0;
+ s->smart_selftest_data = qemu_blockalign(s->bs, 512);
if (bdrv_get_type_hint(s->bs) == BDRV_TYPE_CDROM) {
s->is_cdrom = 1;
bdrv_set_change_cb(s->bs, cdrom_change_cb, s);
diff --git a/hw/marvell_88w8618_audio.c b/hw/marvell_88w8618_audio.c
new file mode 100644
index 000000000..5c6d3a595
--- /dev/null
+++ b/hw/marvell_88w8618_audio.c
@@ -0,0 +1,274 @@
+/*
+ * Marvell 88w8618 audio emulation extracted from
+ * Marvell MV88w8618 / Freecom MusicPal emulation.
+ *
+ * Copyright (c) 2008 Jan Kiszka
+ *
+ * This code is licenced under the GNU GPL v2.
+ */
+#include "sysbus.h"
+#include "hw.h"
+#include "i2c.h"
+#include "sysbus.h"
+#include "audio/audio.h"
+
+#define MP_AUDIO_SIZE 0x00001000
+
+/* Audio register offsets */
+#define MP_AUDIO_PLAYBACK_MODE 0x00
+#define MP_AUDIO_CLOCK_DIV 0x18
+#define MP_AUDIO_IRQ_STATUS 0x20
+#define MP_AUDIO_IRQ_ENABLE 0x24
+#define MP_AUDIO_TX_START_LO 0x28
+#define MP_AUDIO_TX_THRESHOLD 0x2C
+#define MP_AUDIO_TX_STATUS 0x38
+#define MP_AUDIO_TX_START_HI 0x40
+
+/* Status register and IRQ enable bits */
+#define MP_AUDIO_TX_HALF (1 << 6)
+#define MP_AUDIO_TX_FULL (1 << 7)
+
+/* Playback mode bits */
+#define MP_AUDIO_16BIT_SAMPLE (1 << 0)
+#define MP_AUDIO_PLAYBACK_EN (1 << 7)
+#define MP_AUDIO_CLOCK_24MHZ (1 << 9)
+#define MP_AUDIO_MONO (1 << 14)
+
+#ifdef HAS_AUDIO
+typedef struct mv88w8618_audio_state {
+ SysBusDevice busdev;
+ qemu_irq irq;
+ uint32_t playback_mode;
+ uint32_t status;
+ uint32_t irq_enable;
+ unsigned long phys_buf;
+ uint32_t target_buffer;
+ unsigned int threshold;
+ unsigned int play_pos;
+ unsigned int last_free;
+ uint32_t clock_div;
+ DeviceState *wm;
+} mv88w8618_audio_state;
+
+static void mv88w8618_audio_callback(void *opaque, int free_out, int free_in)
+{
+ mv88w8618_audio_state *s = opaque;
+ int16_t *codec_buffer;
+ int8_t buf[4096];
+ int8_t *mem_buffer;
+ int pos, block_size;
+
+ if (!(s->playback_mode & MP_AUDIO_PLAYBACK_EN))
+ return;
+
+ if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE)
+ free_out <<= 1;
+
+ if (!(s->playback_mode & MP_AUDIO_MONO))
+ free_out <<= 1;
+
+ block_size = s->threshold / 2;
+ if (free_out - s->last_free < block_size)
+ return;
+
+ if (block_size > 4096)
+ return;
+
+ cpu_physical_memory_read(s->target_buffer + s->play_pos, (void *)buf,
+ block_size);
+ mem_buffer = buf;
+ if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE) {
+ if (s->playback_mode & MP_AUDIO_MONO) {
+ codec_buffer = wm8750_dac_buffer(s->wm, block_size >> 1);
+ for (pos = 0; pos < block_size; pos += 2) {
+ *codec_buffer++ = *(int16_t *)mem_buffer;
+ *codec_buffer++ = *(int16_t *)mem_buffer;
+ mem_buffer += 2;
+ }
+ } else
+ memcpy(wm8750_dac_buffer(s->wm, block_size >> 2),
+ (uint32_t *)mem_buffer, block_size);
+ } else {
+ if (s->playback_mode & MP_AUDIO_MONO) {
+ codec_buffer = wm8750_dac_buffer(s->wm, block_size);
+ for (pos = 0; pos < block_size; pos++) {
+ *codec_buffer++ = cpu_to_le16(256 * *mem_buffer);
+ *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
+ }
+ } else {
+ codec_buffer = wm8750_dac_buffer(s->wm, block_size >> 1);
+ for (pos = 0; pos < block_size; pos += 2) {
+ *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
+ *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
+ }
+ }
+ }
+ wm8750_dac_commit(s->wm);
+
+ s->last_free = free_out - block_size;
+
+ if (s->play_pos == 0) {
+ s->status |= MP_AUDIO_TX_HALF;
+ s->play_pos = block_size;
+ } else {
+ s->status |= MP_AUDIO_TX_FULL;
+ s->play_pos = 0;
+ }
+
+ if (s->status & s->irq_enable)
+ qemu_irq_raise(s->irq);
+}
+
+static void mv88w8618_audio_clock_update(mv88w8618_audio_state *s)
+{
+ int rate;
+
+ if (s->playback_mode & MP_AUDIO_CLOCK_24MHZ)
+ rate = 24576000 / 64; /* 24.576MHz */
+ else
+ rate = 11289600 / 64; /* 11.2896MHz */
+
+ rate /= ((s->clock_div >> 8) & 0xff) + 1;
+
+ wm8750_set_bclk_in(s->wm, rate);
+}
+
+static uint32_t mv88w8618_audio_read(void *opaque, target_phys_addr_t offset)
+{
+ mv88w8618_audio_state *s = opaque;
+
+ switch (offset) {
+ case MP_AUDIO_PLAYBACK_MODE:
+ return s->playback_mode;
+
+ case MP_AUDIO_CLOCK_DIV:
+ return s->clock_div;
+
+ case MP_AUDIO_IRQ_STATUS:
+ return s->status;
+
+ case MP_AUDIO_IRQ_ENABLE:
+ return s->irq_enable;
+
+ case MP_AUDIO_TX_STATUS:
+ return s->play_pos >> 2;
+
+ default:
+ return 0;
+ }
+}
+
+static void mv88w8618_audio_write(void *opaque, target_phys_addr_t offset,
+ uint32_t value)
+{
+ mv88w8618_audio_state *s = opaque;
+
+ switch (offset) {
+ case MP_AUDIO_PLAYBACK_MODE:
+ if (value & MP_AUDIO_PLAYBACK_EN &&
+ !(s->playback_mode & MP_AUDIO_PLAYBACK_EN)) {
+ s->status = 0;
+ s->last_free = 0;
+ s->play_pos = 0;
+ }
+ s->playback_mode = value;
+ mv88w8618_audio_clock_update(s);
+ break;
+
+ case MP_AUDIO_CLOCK_DIV:
+ s->clock_div = value;
+ s->last_free = 0;
+ s->play_pos = 0;
+ mv88w8618_audio_clock_update(s);
+ break;
+
+ case MP_AUDIO_IRQ_STATUS:
+ s->status &= ~value;
+ break;
+
+ case MP_AUDIO_IRQ_ENABLE:
+ s->irq_enable = value;
+ if (s->status & s->irq_enable)
+ qemu_irq_raise(s->irq);
+ break;
+
+ case MP_AUDIO_TX_START_LO:
+ s->phys_buf = (s->phys_buf & 0xFFFF0000) | (value & 0xFFFF);
+ s->target_buffer = s->phys_buf;
+ s->play_pos = 0;
+ s->last_free = 0;
+ break;
+
+ case MP_AUDIO_TX_THRESHOLD:
+ s->threshold = (value + 1) * 4;
+ break;
+
+ case MP_AUDIO_TX_START_HI:
+ s->phys_buf = (s->phys_buf & 0xFFFF) | (value << 16);
+ s->target_buffer = s->phys_buf;
+ s->play_pos = 0;
+ s->last_free = 0;
+ break;
+ }
+}
+
+static void mv88w8618_audio_reset(void *opaque)
+{
+ mv88w8618_audio_state *s = opaque;
+
+ s->playback_mode = 0;
+ s->status = 0;
+ s->irq_enable = 0;
+}
+
+static CPUReadMemoryFunc *mv88w8618_audio_readfn[] = {
+ mv88w8618_audio_read,
+ mv88w8618_audio_read,
+ mv88w8618_audio_read
+};
+
+static CPUWriteMemoryFunc *mv88w8618_audio_writefn[] = {
+ mv88w8618_audio_write,
+ mv88w8618_audio_write,
+ mv88w8618_audio_write
+};
+
+static void mv88w8618_audio_init(SysBusDevice *dev)
+{
+ mv88w8618_audio_state *s = FROM_SYSBUS(mv88w8618_audio_state, dev);
+ int iomemtype;
+
+ sysbus_init_irq(dev, &s->irq);
+
+ wm8750_data_req_set(s->wm, mv88w8618_audio_callback, s);
+
+ iomemtype = cpu_register_io_memory(mv88w8618_audio_readfn,
+ mv88w8618_audio_writefn, s);
+ sysbus_init_mmio(dev, MP_AUDIO_SIZE, iomemtype);
+
+ qemu_register_reset(mv88w8618_audio_reset, s);
+}
+
+static SysBusDeviceInfo mv88w8618_audio_info = {
+ .init = mv88w8618_audio_init,
+ .qdev.name = "mv88w8618_audio",
+ .qdev.size = sizeof(mv88w8618_audio_state),
+ .qdev.props = (Property[]) {
+ {
+ .name = "wm8750",
+ .info = &qdev_prop_ptr,
+ .offset = offsetof(mv88w8618_audio_state, wm),
+ },
+ {/* end of list */}
+ }
+};
+#endif
+
+static void mv88w8618_register_devices(void)
+{
+#ifdef HAS_AUDIO
+ sysbus_register_withprop(&mv88w8618_audio_info);
+#endif
+}
+
+device_init(mv88w8618_register_devices)
diff --git a/hw/musicpal.c b/hw/musicpal.c
index 2d26b3334..72d72644e 100644
--- a/hw/musicpal.c
+++ b/hw/musicpal.c
@@ -17,7 +17,6 @@
#include "block.h"
#include "flash.h"
#include "console.h"
-#include "audio/audio.h"
#include "i2c.h"
#define MP_MISC_BASE 0x80002000
@@ -39,7 +38,6 @@
#define MP_FLASHCFG_SIZE 0x00001000
#define MP_AUDIO_BASE 0x90007000
-#define MP_AUDIO_SIZE 0x00001000
#define MP_PIC_BASE 0x90008000
#define MP_PIC_SIZE 0x00001000
@@ -68,390 +66,9 @@
#define MP_RTC_IRQ 28
#define MP_AUDIO_IRQ 30
-static uint32_t gpio_in_state = 0xffffffff;
-static uint32_t gpio_isr;
-static uint32_t gpio_out_state;
-static ram_addr_t sram_off;
-
-typedef enum i2c_state {
- STOPPED = 0,
- INITIALIZING,
- SENDING_BIT7,
- SENDING_BIT6,
- SENDING_BIT5,
- SENDING_BIT4,
- SENDING_BIT3,
- SENDING_BIT2,
- SENDING_BIT1,
- SENDING_BIT0,
- WAITING_FOR_ACK,
- RECEIVING_BIT7,
- RECEIVING_BIT6,
- RECEIVING_BIT5,
- RECEIVING_BIT4,
- RECEIVING_BIT3,
- RECEIVING_BIT2,
- RECEIVING_BIT1,
- RECEIVING_BIT0,
- SENDING_ACK
-} i2c_state;
-
-typedef struct i2c_interface {
- i2c_bus *bus;
- i2c_state state;
- int last_data;
- int last_clock;
- uint8_t buffer;
- int current_addr;
-} i2c_interface;
-
-static void i2c_enter_stop(i2c_interface *i2c)
-{
- if (i2c->current_addr >= 0)
- i2c_end_transfer(i2c->bus);
- i2c->current_addr = -1;
- i2c->state = STOPPED;
-}
-
-static void i2c_state_update(i2c_interface *i2c, int data, int clock)
-{
- if (!i2c)
- return;
-
- switch (i2c->state) {
- case STOPPED:
- if (data == 0 && i2c->last_data == 1 && clock == 1)
- i2c->state = INITIALIZING;
- break;
-
- case INITIALIZING:
- if (clock == 0 && i2c->last_clock == 1 && data == 0)
- i2c->state = SENDING_BIT7;
- else
- i2c_enter_stop(i2c);
- break;
-
- case SENDING_BIT7 ... SENDING_BIT0:
- if (clock == 0 && i2c->last_clock == 1) {
- i2c->buffer = (i2c->buffer << 1) | data;
- i2c->state++; /* will end up in WAITING_FOR_ACK */
- } else if (data == 1 && i2c->last_data == 0 && clock == 1)
- i2c_enter_stop(i2c);
- break;
-
- case WAITING_FOR_ACK:
- if (clock == 0 && i2c->last_clock == 1) {
- if (i2c->current_addr < 0) {
- i2c->current_addr = i2c->buffer;
- i2c_start_transfer(i2c->bus, i2c->current_addr & 0xfe,
- i2c->buffer & 1);
- } else
- i2c_send(i2c->bus, i2c->buffer);
- if (i2c->current_addr & 1) {
- i2c->state = RECEIVING_BIT7;
- i2c->buffer = i2c_recv(i2c->bus);
- } else
- i2c->state = SENDING_BIT7;
- } else if (data == 1 && i2c->last_data == 0 && clock == 1)
- i2c_enter_stop(i2c);
- break;
-
- case RECEIVING_BIT7 ... RECEIVING_BIT0:
- if (clock == 0 && i2c->last_clock == 1) {
- i2c->state++; /* will end up in SENDING_ACK */
- i2c->buffer <<= 1;
- } else if (data == 1 && i2c->last_data == 0 && clock == 1)
- i2c_enter_stop(i2c);
- break;
-
- case SENDING_ACK:
- if (clock == 0 && i2c->last_clock == 1) {
- i2c->state = RECEIVING_BIT7;
- if (data == 0)
- i2c->buffer = i2c_recv(i2c->bus);
- else
- i2c_nack(i2c->bus);
- } else if (data == 1 && i2c->last_data == 0 && clock == 1)
- i2c_enter_stop(i2c);
- break;
- }
-
- i2c->last_data = data;
- i2c->last_clock = clock;
-}
-
-static int i2c_get_data(i2c_interface *i2c)
-{
- if (!i2c)
- return 0;
-
- switch (i2c->state) {
- case RECEIVING_BIT7 ... RECEIVING_BIT0:
- return (i2c->buffer >> 7);
-
- case WAITING_FOR_ACK:
- default:
- return 0;
- }
-}
-
-static i2c_interface *mixer_i2c;
-
-#ifdef HAS_AUDIO
-
-/* Audio register offsets */
-#define MP_AUDIO_PLAYBACK_MODE 0x00
-#define MP_AUDIO_CLOCK_DIV 0x18
-#define MP_AUDIO_IRQ_STATUS 0x20
-#define MP_AUDIO_IRQ_ENABLE 0x24
-#define MP_AUDIO_TX_START_LO 0x28
-#define MP_AUDIO_TX_THRESHOLD 0x2C
-#define MP_AUDIO_TX_STATUS 0x38
-#define MP_AUDIO_TX_START_HI 0x40
-
-/* Status register and IRQ enable bits */
-#define MP_AUDIO_TX_HALF (1 << 6)
-#define MP_AUDIO_TX_FULL (1 << 7)
-
-/* Playback mode bits */
-#define MP_AUDIO_16BIT_SAMPLE (1 << 0)
-#define MP_AUDIO_PLAYBACK_EN (1 << 7)
-#define MP_AUDIO_CLOCK_24MHZ (1 << 9)
-#define MP_AUDIO_MONO (1 << 14)
-
/* Wolfson 8750 I2C address */
#define MP_WM_ADDR 0x34
-static const char audio_name[] = "mv88w8618";
-
-typedef struct musicpal_audio_state {
- qemu_irq irq;
- uint32_t playback_mode;
- uint32_t status;
- uint32_t irq_enable;
- unsigned long phys_buf;
- uint32_t target_buffer;
- unsigned int threshold;
- unsigned int play_pos;
- unsigned int last_free;
- uint32_t clock_div;
- DeviceState *wm;
-} musicpal_audio_state;
-
-static void audio_callback(void *opaque, int free_out, int free_in)
-{
- musicpal_audio_state *s = opaque;
- int16_t *codec_buffer;
- int8_t buf[4096];
- int8_t *mem_buffer;
- int pos, block_size;
-
- if (!(s->playback_mode & MP_AUDIO_PLAYBACK_EN))
- return;
-
- if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE)
- free_out <<= 1;
-
- if (!(s->playback_mode & MP_AUDIO_MONO))
- free_out <<= 1;
-
- block_size = s->threshold/2;
- if (free_out - s->last_free < block_size)
- return;
-
- if (block_size > 4096)
- return;
-
- cpu_physical_memory_read(s->target_buffer + s->play_pos, (void *)buf,
- block_size);
- mem_buffer = buf;
- if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE) {
- if (s->playback_mode & MP_AUDIO_MONO) {
- codec_buffer = wm8750_dac_buffer(s->wm, block_size >> 1);
- for (pos = 0; pos < block_size; pos += 2) {
- *codec_buffer++ = *(int16_t *)mem_buffer;
- *codec_buffer++ = *(int16_t *)mem_buffer;
- mem_buffer += 2;
- }
- } else
- memcpy(wm8750_dac_buffer(s->wm, block_size >> 2),
- (uint32_t *)mem_buffer, block_size);
- } else {
- if (s->playback_mode & MP_AUDIO_MONO) {
- codec_buffer = wm8750_dac_buffer(s->wm, block_size);
- for (pos = 0; pos < block_size; pos++) {
- *codec_buffer++ = cpu_to_le16(256 * *mem_buffer);
- *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
- }
- } else {
- codec_buffer = wm8750_dac_buffer(s->wm, block_size >> 1);
- for (pos = 0; pos < block_size; pos += 2) {
- *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
- *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
- }
- }
- }
- wm8750_dac_commit(s->wm);
-
- s->last_free = free_out - block_size;
-
- if (s->play_pos == 0) {
- s->status |= MP_AUDIO_TX_HALF;
- s->play_pos = block_size;
- } else {
- s->status |= MP_AUDIO_TX_FULL;
- s->play_pos = 0;
- }
-
- if (s->status & s->irq_enable)
- qemu_irq_raise(s->irq);
-}
-
-static void musicpal_audio_clock_update(musicpal_audio_state *s)
-{
- int rate;
-
- if (s->playback_mode & MP_AUDIO_CLOCK_24MHZ)
- rate = 24576000 / 64; /* 24.576MHz */
- else
- rate = 11289600 / 64; /* 11.2896MHz */
-
- rate /= ((s->clock_div >> 8) & 0xff) + 1;
-
- wm8750_set_bclk_in(s->wm, rate);
-}
-
-static uint32_t musicpal_audio_read(void *opaque, target_phys_addr_t offset)
-{
- musicpal_audio_state *s = opaque;
-
- switch (offset) {
- case MP_AUDIO_PLAYBACK_MODE:
- return s->playback_mode;
-
- case MP_AUDIO_CLOCK_DIV:
- return s->clock_div;
-
- case MP_AUDIO_IRQ_STATUS:
- return s->status;
-
- case MP_AUDIO_IRQ_ENABLE:
- return s->irq_enable;
-
- case MP_AUDIO_TX_STATUS:
- return s->play_pos >> 2;
-
- default:
- return 0;
- }
-}
-
-static void musicpal_audio_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
-{
- musicpal_audio_state *s = opaque;
-
- switch (offset) {
- case MP_AUDIO_PLAYBACK_MODE:
- if (value & MP_AUDIO_PLAYBACK_EN &&
- !(s->playback_mode & MP_AUDIO_PLAYBACK_EN)) {
- s->status = 0;
- s->last_free = 0;
- s->play_pos = 0;
- }
- s->playback_mode = value;
- musicpal_audio_clock_update(s);
- break;
-
- case MP_AUDIO_CLOCK_DIV:
- s->clock_div = value;
- s->last_free = 0;
- s->play_pos = 0;
- musicpal_audio_clock_update(s);
- break;
-
- case MP_AUDIO_IRQ_STATUS:
- s->status &= ~value;
- break;
-
- case MP_AUDIO_IRQ_ENABLE:
- s->irq_enable = value;
- if (s->status & s->irq_enable)
- qemu_irq_raise(s->irq);
- break;
-
- case MP_AUDIO_TX_START_LO:
- s->phys_buf = (s->phys_buf & 0xFFFF0000) | (value & 0xFFFF);
- s->target_buffer = s->phys_buf;
- s->play_pos = 0;
- s->last_free = 0;
- break;
-
- case MP_AUDIO_TX_THRESHOLD:
- s->threshold = (value + 1) * 4;
- break;
-
- case MP_AUDIO_TX_START_HI:
- s->phys_buf = (s->phys_buf & 0xFFFF) | (value << 16);
- s->target_buffer = s->phys_buf;
- s->play_pos = 0;
- s->last_free = 0;
- break;
- }
-}
-
-static void musicpal_audio_reset(void *opaque)
-{
- musicpal_audio_state *s = opaque;
-
- s->playback_mode = 0;
- s->status = 0;
- s->irq_enable = 0;
-}
-
-static CPUReadMemoryFunc *musicpal_audio_readfn[] = {
- musicpal_audio_read,
- musicpal_audio_read,
- musicpal_audio_read
-};
-
-static CPUWriteMemoryFunc *musicpal_audio_writefn[] = {
- musicpal_audio_write,
- musicpal_audio_write,
- musicpal_audio_write
-};
-
-static i2c_interface *musicpal_audio_init(qemu_irq irq)
-{
- musicpal_audio_state *s;
- i2c_interface *i2c;
- int iomemtype;
-
- s = qemu_mallocz(sizeof(musicpal_audio_state));
- s->irq = irq;
-
- i2c = qemu_mallocz(sizeof(i2c_interface));
- i2c->bus = i2c_init_bus(NULL, "i2c");
- i2c->current_addr = -1;
-
- s->wm = i2c_create_slave(i2c->bus, "wm8750", MP_WM_ADDR);
- wm8750_data_req_set(s->wm, audio_callback, s);
-
- iomemtype = cpu_register_io_memory(musicpal_audio_readfn,
- musicpal_audio_writefn, s);
- cpu_register_physical_memory(MP_AUDIO_BASE, MP_AUDIO_SIZE, iomemtype);
-
- qemu_register_reset(musicpal_audio_reset, s);
-
- return i2c;
-}
-#else /* !HAS_AUDIO */
-static i2c_interface *musicpal_audio_init(qemu_irq irq)
-{
- return NULL;
-}
-#endif /* !HAS_AUDIO */
-
/* Ethernet register offsets */
#define MP_ETH_SMIR 0x010
#define MP_ETH_PCXR 0x408
@@ -782,6 +399,7 @@ static void mv88w8618_eth_init(SysBusDevice *dev)
typedef struct musicpal_lcd_state {
SysBusDevice busdev;
+ uint32_t brightness;
uint32_t mode;
uint32_t irqctrl;
int page;
@@ -790,37 +408,15 @@ typedef struct musicpal_lcd_state {
uint8_t video_ram[128*64/8];
} musicpal_lcd_state;
-static uint32_t lcd_brightness;
-
-static uint8_t scale_lcd_color(uint8_t col)
+static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col)
{
- int tmp = col;
-
- switch (lcd_brightness) {
- case 0x00000007: /* 0 */
+ switch (s->brightness) {
+ case 7:
+ return col;
+ case 0:
return 0;
-
- case 0x00020000: /* 1 */
- return (tmp * 1) / 7;
-
- case 0x00020001: /* 2 */
- return (tmp * 2) / 7;
-
- case 0x00040000: /* 3 */
- return (tmp * 3) / 7;
-
- case 0x00010006: /* 4 */
- return (tmp * 4) / 7;
-
- case 0x00020005: /* 5 */
- return (tmp * 5) / 7;
-
- case 0x00040003: /* 6 */
- return (tmp * 6) / 7;
-
- case 0x00030004: /* 7 */
default:
- return col;
+ return (col * s->brightness) / 7;
}
}
@@ -851,9 +447,9 @@ static void lcd_refresh(void *opaque)
return;
#define LCD_REFRESH(depth, func) \
case depth: \
- col = func(scale_lcd_color((MP_LCD_TEXTCOLOR >> 16) & 0xff), \
- scale_lcd_color((MP_LCD_TEXTCOLOR >> 8) & 0xff), \
- scale_lcd_color(MP_LCD_TEXTCOLOR & 0xff)); \
+ col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \
+ scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \
+ scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \
for (x = 0; x < 128; x++) \
for (y = 0; y < 64; y++) \
if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) \
@@ -877,6 +473,13 @@ static void lcd_invalidate(void *opaque)
{
}
+static void musicpal_lcd_gpio_brigthness_in(void *opaque, int irq, int level)
+{
+ musicpal_lcd_state *s = (musicpal_lcd_state *) opaque;
+ s->brightness &= ~(1 << irq);
+ s->brightness |= level << irq;
+}
+
static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset)
{
musicpal_lcd_state *s = opaque;
@@ -946,14 +549,17 @@ static void musicpal_lcd_init(SysBusDevice *dev)
musicpal_lcd_state *s = FROM_SYSBUS(musicpal_lcd_state, dev);
int iomemtype;
+ s->brightness = 7;
+
iomemtype = cpu_register_io_memory(musicpal_lcd_readfn,
musicpal_lcd_writefn, s);
sysbus_init_mmio(dev, MP_LCD_SIZE, iomemtype);
- cpu_register_physical_memory(MP_LCD_BASE, MP_LCD_SIZE, iomemtype);
s->ds = graphic_console_init(lcd_refresh, lcd_invalidate,
NULL, NULL, s);
qemu_console_resize(s->ds, 128*3, 64*3);
+
+ qdev_init_gpio_in(&dev->qdev, musicpal_lcd_gpio_brigthness_in, 3);
}
/* PIC register offsets */
@@ -1327,15 +933,7 @@ static void mv88w8618_wlan_init(SysBusDevice *dev)
#define MP_GPIO_ISR_HI 0x520
/* GPIO bits & masks */
-#define MP_GPIO_WHEEL_VOL (1 << 8)
-#define MP_GPIO_WHEEL_VOL_INV (1 << 9)
-#define MP_GPIO_WHEEL_NAV (1 << 10)
-#define MP_GPIO_WHEEL_NAV_INV (1 << 11)
#define MP_GPIO_LCD_BRIGHTNESS 0x00070000
-#define MP_GPIO_BTN_FAVORITS (1 << 19)
-#define MP_GPIO_BTN_MENU (1 << 20)
-#define MP_GPIO_BTN_VOLUME (1 << 21)
-#define MP_GPIO_BTN_NAVIGATION (1 << 22)
#define MP_GPIO_I2C_DATA_BIT 29
#define MP_GPIO_I2C_DATA (1 << MP_GPIO_I2C_DATA_BIT)
#define MP_GPIO_I2C_CLOCK_BIT 30
@@ -1343,29 +941,132 @@ static void mv88w8618_wlan_init(SysBusDevice *dev)
/* LCD brightness bits in GPIO_OE_HI */
#define MP_OE_LCD_BRIGHTNESS 0x0007
+typedef struct musicpal_gpio_state {
+ SysBusDevice busdev;
+ uint32_t lcd_brightness;
+ uint32_t out_state;
+ uint32_t in_state;
+ uint32_t isr;
+ uint32_t i2c_read_data;
+ uint32_t key_released;
+ uint32_t keys_event; /* store the received key event */
+ qemu_irq irq;
+ qemu_irq out[5];
+} musicpal_gpio_state;
+
+static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) {
+ int i;
+ uint32_t brightness;
+
+ /* compute brightness ratio */
+ switch (s->lcd_brightness) {
+ case 0x00000007:
+ brightness = 0;
+ break;
+
+ case 0x00020000:
+ brightness = 1;
+ break;
+
+ case 0x00020001:
+ brightness = 2;
+ break;
+
+ case 0x00040000:
+ brightness = 3;
+ break;
+
+ case 0x00010006:
+ brightness = 4;
+ break;
+
+ case 0x00020005:
+ brightness = 5;
+ break;
+
+ case 0x00040003:
+ brightness = 6;
+ break;
+
+ case 0x00030004:
+ default:
+ brightness = 7;
+ }
+
+ /* set lcd brightness GPIOs */
+ for (i = 0; i <= 2; i++)
+ qemu_set_irq(s->out[i], (brightness >> i) & 1);
+}
+
+static void musicpal_gpio_keys_update(musicpal_gpio_state *s)
+{
+ int gpio_mask = 0;
+
+ /* transform the key state for GPIO usage */
+ gpio_mask |= (s->keys_event & 15) << 8;
+ gpio_mask |= ((s->keys_event >> 4) & 15) << 19;
+
+ /* update GPIO state */
+ if (s->key_released) {
+ s->in_state |= gpio_mask;
+ } else {
+ s->in_state &= ~gpio_mask;
+ s->isr = gpio_mask;
+ qemu_irq_raise(s->irq);
+ }
+}
+
+static void musicpal_gpio_irq(void *opaque, int irq, int level)
+{
+ musicpal_gpio_state *s = (musicpal_gpio_state *) opaque;
+
+ if (irq == 10) {
+ s->i2c_read_data = level;
+ }
+
+ /* receives keys bits */
+ if (irq <= 7) {
+ s->keys_event &= ~(1 << irq);
+ s->keys_event |= level << irq;
+ return;
+ }
+
+ /* receives key press/release */
+ if (irq == 8) {
+ s->key_released = level;
+ return;
+ }
+
+ /* a key has been transmited */
+ if (irq == 9 && level == 1)
+ musicpal_gpio_keys_update(s);
+}
+
static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset)
{
+ musicpal_gpio_state *s = (musicpal_gpio_state *) opaque;
+
switch (offset) {
case MP_GPIO_OE_HI: /* used for LCD brightness control */
- return lcd_brightness & MP_OE_LCD_BRIGHTNESS;
+ return s->lcd_brightness & MP_OE_LCD_BRIGHTNESS;
case MP_GPIO_OUT_LO:
- return gpio_out_state & 0xFFFF;
+ return s->out_state & 0xFFFF;
case MP_GPIO_OUT_HI:
- return gpio_out_state >> 16;
+ return s->out_state >> 16;
case MP_GPIO_IN_LO:
- return gpio_in_state & 0xFFFF;
+ return s->in_state & 0xFFFF;
case MP_GPIO_IN_HI:
/* Update received I2C data */
- gpio_in_state = (gpio_in_state & ~MP_GPIO_I2C_DATA) |
- (i2c_get_data(mixer_i2c) << MP_GPIO_I2C_DATA_BIT);
- return gpio_in_state >> 16;
+ s->in_state = (s->in_state & ~MP_GPIO_I2C_DATA) |
+ (s->i2c_read_data << MP_GPIO_I2C_DATA_BIT);
+ return s->in_state >> 16;
case MP_GPIO_ISR_LO:
- return gpio_isr & 0xFFFF;
+ return s->isr & 0xFFFF;
case MP_GPIO_ISR_HI:
- return gpio_isr >> 16;
+ return s->isr >> 16;
default:
return 0;
@@ -1375,22 +1076,24 @@ static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset)
static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
+ musicpal_gpio_state *s = (musicpal_gpio_state *) opaque;
switch (offset) {
case MP_GPIO_OE_HI: /* used for LCD brightness control */
- lcd_brightness = (lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) |
+ s->lcd_brightness = (s->lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) |
(value & MP_OE_LCD_BRIGHTNESS);
+ musicpal_gpio_brightness_update(s);
break;
case MP_GPIO_OUT_LO:
- gpio_out_state = (gpio_out_state & 0xFFFF0000) | (value & 0xFFFF);
+ s->out_state = (s->out_state & 0xFFFF0000) | (value & 0xFFFF);
break;
case MP_GPIO_OUT_HI:
- gpio_out_state = (gpio_out_state & 0xFFFF) | (value << 16);
- lcd_brightness = (lcd_brightness & 0xFFFF) |
- (gpio_out_state & MP_GPIO_LCD_BRIGHTNESS);
- i2c_state_update(mixer_i2c,
- (gpio_out_state >> MP_GPIO_I2C_DATA_BIT) & 1,
- (gpio_out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1);
+ s->out_state = (s->out_state & 0xFFFF) | (value << 16);
+ s->lcd_brightness = (s->lcd_brightness & 0xFFFF) |
+ (s->out_state & MP_GPIO_LCD_BRIGHTNESS);
+ musicpal_gpio_brightness_update(s);
+ qemu_set_irq(s->out[3], (s->out_state >> MP_GPIO_I2C_DATA_BIT) & 1);
+ qemu_set_irq(s->out[4], (s->out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1);
break;
}
@@ -1408,13 +1111,32 @@ static CPUWriteMemoryFunc *musicpal_gpio_writefn[] = {
musicpal_gpio_write,
};
-static void musicpal_gpio_init(void)
+static void musicpal_gpio_reset(musicpal_gpio_state *s)
{
+ s->in_state = 0xffffffff;
+ s->i2c_read_data = 1;
+ s->key_released = 0;
+ s->keys_event = 0;
+ s->isr = 0;
+}
+
+static void musicpal_gpio_init(SysBusDevice *dev)
+{
+ musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state, dev);
int iomemtype;
+ sysbus_init_irq(dev, &s->irq);
+
iomemtype = cpu_register_io_memory(musicpal_gpio_readfn,
- musicpal_gpio_writefn, NULL);
- cpu_register_physical_memory(MP_GPIO_BASE, MP_GPIO_SIZE, iomemtype);
+ musicpal_gpio_writefn, s);
+ sysbus_init_mmio(dev, MP_GPIO_SIZE, iomemtype);
+
+ musicpal_gpio_reset(s);
+
+ /* 3 brightness out + 2 lcd (data and clock ) */
+ qdev_init_gpio_out(&dev->qdev, s->out, 5);
+ /* 10 gpio button input + 1 I2C data input */
+ qdev_init_gpio_in(&dev->qdev, musicpal_gpio_irq, 11);
}
/* Keyboard codes & masks */
@@ -1432,69 +1154,109 @@ static void musicpal_gpio_init(void)
#define KEYCODE_LEFT 0x4b
#define KEYCODE_RIGHT 0x4d
+#define MP_KEY_WHEEL_VOL (1)
+#define MP_KEY_WHEEL_VOL_INV (1 << 1)
+#define MP_KEY_WHEEL_NAV (1 << 2)
+#define MP_KEY_WHEEL_NAV_INV (1 << 3)
+#define MP_KEY_BTN_FAVORITS (1 << 4)
+#define MP_KEY_BTN_MENU (1 << 5)
+#define MP_KEY_BTN_VOLUME (1 << 6)
+#define MP_KEY_BTN_NAVIGATION (1 << 7)
+
+typedef struct musicpal_key_state {
+ SysBusDevice busdev;
+ uint32_t kbd_extended;
+ uint32_t keys_state;
+ qemu_irq out[10];
+} musicpal_key_state;
+
static void musicpal_key_event(void *opaque, int keycode)
{
- qemu_irq irq = opaque;
+ musicpal_key_state *s = (musicpal_key_state *) opaque;
uint32_t event = 0;
- static int kbd_extended;
+ int i;
if (keycode == KEYCODE_EXTENDED) {
- kbd_extended = 1;
+ s->kbd_extended = 1;
return;
}
- if (kbd_extended)
+ if (s->kbd_extended)
switch (keycode & KEY_CODE) {
case KEYCODE_UP:
- event = MP_GPIO_WHEEL_NAV | MP_GPIO_WHEEL_NAV_INV;
+ event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV;
break;
case KEYCODE_DOWN:
- event = MP_GPIO_WHEEL_NAV;
+ event = MP_KEY_WHEEL_NAV;
break;
case KEYCODE_LEFT:
- event = MP_GPIO_WHEEL_VOL | MP_GPIO_WHEEL_VOL_INV;
+ event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV;
break;
case KEYCODE_RIGHT:
- event = MP_GPIO_WHEEL_VOL;
+ event = MP_KEY_WHEEL_VOL;
break;
}
else {
switch (keycode & KEY_CODE) {
case KEYCODE_F:
- event = MP_GPIO_BTN_FAVORITS;
+ event = MP_KEY_BTN_FAVORITS;
break;
case KEYCODE_TAB:
- event = MP_GPIO_BTN_VOLUME;
+ event = MP_KEY_BTN_VOLUME;
break;
case KEYCODE_ENTER:
- event = MP_GPIO_BTN_NAVIGATION;
+ event = MP_KEY_BTN_NAVIGATION;
break;
case KEYCODE_M:
- event = MP_GPIO_BTN_MENU;
+ event = MP_KEY_BTN_MENU;
break;
}
/* Do not repeat already pressed buttons */
- if (!(keycode & KEY_RELEASED) && !(gpio_in_state & event))
+ if (!(keycode & KEY_RELEASED) && !(s->keys_state & event))
event = 0;
}
if (event) {
+
+ /* transmit key event on GPIOS */
+ for (i = 0; i <= 7; i++)
+ qemu_set_irq(s->out[i], (event >> i) & 1);
+
+ /* handle key press/release */
if (keycode & KEY_RELEASED) {
- gpio_in_state |= event;
+ s->keys_state |= event;
+ qemu_irq_raise(s->out[8]);
} else {
- gpio_in_state &= ~event;
- gpio_isr = event;
- qemu_irq_raise(irq);
+ s->keys_state &= ~event;
+ qemu_irq_lower(s->out[8]);
}
+
+ /* signal that a key event occured */
+ qemu_irq_pulse(s->out[9]);
}
- kbd_extended = 0;
+ s->kbd_extended = 0;
+}
+
+static void musicpal_key_init(SysBusDevice *dev)
+{
+ musicpal_key_state *s = FROM_SYSBUS(musicpal_key_state, dev);
+
+ sysbus_init_mmio(dev, 0x0, 0);
+
+ s->kbd_extended = 0;
+ s->keys_state = 0;
+
+ /* 8 key event GPIO + 1 key press/release + 1 strobe */
+ qdev_init_gpio_out(&dev->qdev, s->out, 10);
+
+ qemu_add_kbd_event_handler(musicpal_key_event, s);
}
static struct arm_boot_info musicpal_binfo = {
@@ -1511,9 +1273,18 @@ static void musicpal_init(ram_addr_t ram_size,
qemu_irq *cpu_pic;
qemu_irq pic[32];
DeviceState *dev;
+ DeviceState *i2c_dev;
+ DeviceState *lcd_dev;
+ DeviceState *key_dev;
+#ifdef HAS_AUDIO
+ DeviceState *wm8750_dev;
+ SysBusDevice *s;
+#endif
+ i2c_bus *i2c;
int i;
unsigned long flash_size;
DriveInfo *dinfo;
+ ram_addr_t sram_off;
if (!cpu_model)
cpu_model = "arm926";
@@ -1572,10 +1343,6 @@ static void musicpal_init(ram_addr_t ram_size,
}
sysbus_create_simple("mv88w8618_flashcfg", MP_FLASHCFG_BASE, NULL);
- sysbus_create_simple("musicpal_lcd", MP_LCD_BASE, NULL);
-
- qemu_add_kbd_event_handler(musicpal_key_event, pic[MP_GPIO_IRQ]);
-
qemu_check_nic_model(&nd_table[0], "mv88w8618");
dev = qdev_create(NULL, "mv88w8618_eth");
dev->nd = &nd_table[0];
@@ -1583,12 +1350,39 @@ static void musicpal_init(ram_addr_t ram_size,
sysbus_mmio_map(sysbus_from_qdev(dev), 0, MP_ETH_BASE);
sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[MP_ETH_IRQ]);
- mixer_i2c = musicpal_audio_init(pic[MP_AUDIO_IRQ]);
-
sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL);
musicpal_misc_init();
- musicpal_gpio_init();
+
+ dev = sysbus_create_simple("musicpal_gpio", MP_GPIO_BASE, pic[MP_GPIO_IRQ]);
+ i2c_dev = sysbus_create_simple("bitbang_i2c", 0, NULL);
+ i2c = (i2c_bus *)qdev_get_child_bus(i2c_dev, "i2c");
+
+ lcd_dev = sysbus_create_simple("musicpal_lcd", MP_LCD_BASE, NULL);
+ key_dev = sysbus_create_simple("musicpal_key", 0, NULL);
+
+ /* I2C read data */
+ qdev_connect_gpio_out(i2c_dev, 0, qdev_get_gpio_in(dev, 10));
+ /* I2C data */
+ qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(i2c_dev, 0));
+ /* I2C clock */
+ qdev_connect_gpio_out(dev, 4, qdev_get_gpio_in(i2c_dev, 1));
+
+ for (i = 0; i < 3; i++)
+ qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i));
+
+ for (i = 0; i < 10; i++)
+ qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i));
+
+#ifdef HAS_AUDIO
+ wm8750_dev = i2c_create_slave(i2c, "wm8750", MP_WM_ADDR);
+ dev = qdev_create(NULL, "mv88w8618_audio");
+ s = sysbus_from_qdev(dev);
+ qdev_prop_set_ptr(dev, "wm8750", wm8750_dev);
+ qdev_init(dev);
+ sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
+ sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
+#endif
musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
musicpal_binfo.kernel_filename = kernel_filename;
@@ -1624,6 +1418,10 @@ static void musicpal_register_devices(void)
mv88w8618_wlan_init);
sysbus_register_dev("musicpal_lcd", sizeof(musicpal_lcd_state),
musicpal_lcd_init);
+ sysbus_register_dev("musicpal_gpio", sizeof(musicpal_gpio_state),
+ musicpal_gpio_init);
+ sysbus_register_dev("musicpal_key", sizeof(musicpal_key_state),
+ musicpal_key_init);
}
device_init(musicpal_register_devices)
diff --git a/hw/pc.c b/hw/pc.c
index ca681b8b2..2e9290247 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -92,6 +92,17 @@ static void option_rom_setup_reset(target_phys_addr_t addr, unsigned size)
qemu_register_reset(option_rom_reset, rrd);
}
+typedef struct isa_irq_state {
+ qemu_irq *i8259;
+} IsaIrqState;
+
+static void isa_irq_handler(void *opaque, int n, int level)
+{
+ IsaIrqState *isa = (IsaIrqState *)opaque;
+
+ qemu_set_irq(isa->i8259[n], level);
+}
+
static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
{
}
@@ -1130,7 +1141,9 @@ static void pc_init1(ram_addr_t ram_size,
int piix3_devfn = -1;
CPUState *env;
qemu_irq *cpu_irq;
+ qemu_irq *isa_irq;
qemu_irq *i8259;
+ IsaIrqState *isa_irq_state;
DriveInfo *dinfo;
BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
BlockDriverState *fd[MAX_FD];
@@ -1282,10 +1295,13 @@ static void pc_init1(ram_addr_t ram_size,
} else
#endif
i8259 = i8259_init(cpu_irq[0]);
- ferr_irq = i8259[13];
+ isa_irq_state = qemu_mallocz(sizeof(*isa_irq_state));
+ isa_irq_state->i8259 = i8259;
+ isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 16);
+ ferr_irq = isa_irq[13];
if (pci_enabled) {
- pci_bus = i440fx_init(&i440fx_state, i8259);
+ pci_bus = i440fx_init(&i440fx_state, isa_irq);
piix3_devfn = piix3_init(pci_bus, -1);
} else {
pci_bus = NULL;
@@ -1315,7 +1331,7 @@ static void pc_init1(ram_addr_t ram_size,
}
}
- rtc_state = rtc_init(0x70, i8259[8], 2000);
+ rtc_state = rtc_init(0x70, isa_irq[8], 2000);
qemu_register_boot_set(pc_boot_set, rtc_state);
@@ -1327,13 +1343,13 @@ static void pc_init1(ram_addr_t ram_size,
}
#ifdef USE_KVM_PIT
if (kvm_enabled() && qemu_kvm_pit_in_kernel())
- pit = kvm_pit_init(0x40, i8259[0]);
+ pit = kvm_pit_init(0x40, isa_irq[0]);
else
#endif
- pit = pit_init(0x40, i8259[0]);
+ pit = pit_init(0x40, isa_irq[0]);
pcspk_init(pit);
if (!no_hpet) {
- hpet_init(i8259);
+ hpet_init(isa_irq);
}
if (pci_enabled) {
pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic);
@@ -1341,14 +1357,14 @@ static void pc_init1(ram_addr_t ram_size,
for(i = 0; i < MAX_SERIAL_PORTS; i++) {
if (serial_hds[i]) {
- serial_init(serial_io[i], i8259[serial_irq[i]], 115200,
+ serial_init(serial_io[i], isa_irq[serial_irq[i]], 115200,
serial_hds[i]);
}
}
for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
if (parallel_hds[i]) {
- parallel_init(parallel_io[i], i8259[parallel_irq[i]],
+ parallel_init(parallel_io[i], isa_irq[parallel_irq[i]],
parallel_hds[i]);
}
}
@@ -1359,7 +1375,7 @@ static void pc_init1(ram_addr_t ram_size,
NICInfo *nd = &nd_table[i];
if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
- pc_init_ne2k_isa(nd, i8259);
+ pc_init_ne2k_isa(nd, isa_irq);
else
pci_nic_init(nd, "rtl8139", NULL);
}
@@ -1377,27 +1393,27 @@ static void pc_init1(ram_addr_t ram_size,
}
if (pci_enabled) {
- pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, i8259);
+ pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, isa_irq);
} else {
for(i = 0; i < MAX_IDE_BUS; i++) {
- isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
+ isa_ide_init(ide_iobase[i], ide_iobase2[i], isa_irq[ide_irq[i]],
hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
}
}
isa_dev = isa_create_simple("i8042", 0x60, 0x64);
- isa_connect_irq(isa_dev, 0, i8259[1]);
- isa_connect_irq(isa_dev, 1, i8259[12]);
+ isa_connect_irq(isa_dev, 0, isa_irq[1]);
+ isa_connect_irq(isa_dev, 1, isa_irq[12]);
DMA_init(0);
#ifdef HAS_AUDIO
- audio_init(pci_enabled ? pci_bus : NULL, i8259);
+ audio_init(pci_enabled ? pci_bus : NULL, isa_irq);
#endif
for(i = 0; i < MAX_FD; i++) {
dinfo = drive_get(IF_FLOPPY, 0, i);
fd[i] = dinfo ? dinfo->bdrv : NULL;
}
- floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);
+ floppy_controller = fdctrl_init(isa_irq[6], 2, 0, 0x3f0, fd);
cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd);
@@ -1410,7 +1426,7 @@ static void pc_init1(ram_addr_t ram_size,
i2c_bus *smbus;
/* TODO: Populate SPD eeprom data. */
- smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, i8259[9]);
+ smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, isa_irq[9]);
for (i = 0; i < 8; i++) {
DeviceState *eeprom;
eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
diff --git a/hw/pci-hotplug.c b/hw/pci-hotplug.c
index 598b20b2f..69ee92a13 100644
--- a/hw/pci-hotplug.c
+++ b/hw/pci-hotplug.c
@@ -126,9 +126,8 @@ static PCIDevice *qemu_pci_hot_add_storage(Monitor *mon,
monitor_printf(mon, "Parameter addr not supported\n");
return NULL;
}
- } else if (type == IF_VIRTIO) {
- monitor_printf(mon, "virtio requires a backing file/device.\n");
- return NULL;
+ } else {
+ dinfo = NULL;
}
switch (type) {
@@ -136,6 +135,10 @@ static PCIDevice *qemu_pci_hot_add_storage(Monitor *mon,
dev = pci_create("lsi53c895a", devaddr);
break;
case IF_VIRTIO:
+ if (!dinfo) {
+ monitor_printf(mon, "virtio requires a backing file/device.\n");
+ return NULL;
+ }
dev = pci_create("virtio-blk-pci", devaddr);
qdev_prop_set_drive(&dev->qdev, "drive", dinfo);
break;
diff --git a/hw/ppc.c b/hw/ppc.c
index c23a02d27..a01bde9b3 100644
--- a/hw/ppc.c
+++ b/hw/ppc.c
@@ -393,8 +393,8 @@ struct ppc_tb_t {
void *opaque;
};
-static always_inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env, uint64_t vmclk,
- int64_t tb_offset)
+static inline uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk,
+ int64_t tb_offset)
{
/* TB time in tb periods */
return muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec) + tb_offset;
@@ -411,7 +411,7 @@ uint32_t cpu_ppc_load_tbl (CPUState *env)
return tb & 0xFFFFFFFF;
}
-static always_inline uint32_t _cpu_ppc_load_tbu (CPUState *env)
+static inline uint32_t _cpu_ppc_load_tbu(CPUState *env)
{
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
@@ -427,9 +427,8 @@ uint32_t cpu_ppc_load_tbu (CPUState *env)
return _cpu_ppc_load_tbu(env);
}
-static always_inline void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t vmclk,
- int64_t *tb_offsetp,
- uint64_t value)
+static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk,
+ int64_t *tb_offsetp, uint64_t value)
{
*tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec);
LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n",
@@ -447,7 +446,7 @@ void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
&tb_env->tb_offset, tb | (uint64_t)value);
}
-static always_inline void _cpu_ppc_store_tbu (CPUState *env, uint32_t value)
+static inline void _cpu_ppc_store_tbu(CPUState *env, uint32_t value)
{
ppc_tb_t *tb_env = env->tb_env;
uint64_t tb;
@@ -550,8 +549,7 @@ static void cpu_ppc_tb_start (CPUState *env)
}
}
-static always_inline uint32_t _cpu_ppc_load_decr (CPUState *env,
- uint64_t next)
+static inline uint32_t _cpu_ppc_load_decr(CPUState *env, uint64_t next)
{
ppc_tb_t *tb_env = env->tb_env;
uint32_t decr;
@@ -594,14 +592,14 @@ uint64_t cpu_ppc_load_purr (CPUState *env)
/* When decrementer expires,
* all we need to do is generate or queue a CPU exception
*/
-static always_inline void cpu_ppc_decr_excp (CPUState *env)
+static inline void cpu_ppc_decr_excp(CPUState *env)
{
/* Raise it */
LOG_TB("raise decrementer exception\n");
ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);
}
-static always_inline void cpu_ppc_hdecr_excp (CPUState *env)
+static inline void cpu_ppc_hdecr_excp(CPUState *env)
{
/* Raise it */
LOG_TB("raise decrementer exception\n");
@@ -635,8 +633,8 @@ static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp,
(*raise_excp)(env);
}
-static always_inline void _cpu_ppc_store_decr (CPUState *env, uint32_t decr,
- uint32_t value, int is_excp)
+static inline void _cpu_ppc_store_decr(CPUState *env, uint32_t decr,
+ uint32_t value, int is_excp)
{
ppc_tb_t *tb_env = env->tb_env;
@@ -654,8 +652,8 @@ static void cpu_ppc_decr_cb (void *opaque)
_cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1);
}
-static always_inline void _cpu_ppc_store_hdecr (CPUState *env, uint32_t hdecr,
- uint32_t value, int is_excp)
+static inline void _cpu_ppc_store_hdecr(CPUState *env, uint32_t hdecr,
+ uint32_t value, int is_excp)
{
ppc_tb_t *tb_env = env->tb_env;
@@ -797,9 +795,9 @@ static void cpu_4xx_fit_cb (void *opaque)
env->spr[SPR_40x_TSR] |= 1 << 26;
if ((env->spr[SPR_40x_TCR] >> 23) & 0x1)
ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
- LOG_TB("%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__,
- (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
- env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
+ LOG_TB("%s: ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__,
+ (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
+ env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
}
/* Programmable interval timer */
@@ -843,12 +841,12 @@ static void cpu_4xx_pit_cb (void *opaque)
if ((env->spr[SPR_40x_TCR] >> 26) & 0x1)
ppc_set_irq(env, PPC_INTERRUPT_PIT, 1);
start_stop_pit(env, tb_env, 1);
- LOG_TB("%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " "
- "%016" PRIx64 "\n", __func__,
- (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
- (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
- env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
- ppcemb_timer->pit_reload);
+ LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " "
+ "%016" PRIx64 "\n", __func__,
+ (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
+ (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
+ env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
+ ppcemb_timer->pit_reload);
}
/* Watchdog timer */
@@ -883,8 +881,8 @@ static void cpu_4xx_wdt_cb (void *opaque)
next = now + muldiv64(next, ticks_per_sec, tb_env->decr_freq);
if (next == now)
next++;
- LOG_TB("%s: TCR " ADDRX " TSR " ADDRX "\n", __func__,
- env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
+ LOG_TB("%s: TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__,
+ env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
case 0x0:
case 0x1:
@@ -926,7 +924,7 @@ void store_40x_pit (CPUState *env, target_ulong val)
tb_env = env->tb_env;
ppcemb_timer = tb_env->opaque;
- LOG_TB("%s val" ADDRX "\n", __func__, val);
+ LOG_TB("%s val" TARGET_FMT_lx "\n", __func__, val);
ppcemb_timer->pit_reload = val;
start_stop_pit(env, tb_env, 0);
}
@@ -938,7 +936,7 @@ target_ulong load_40x_pit (CPUState *env)
void store_booke_tsr (CPUState *env, target_ulong val)
{
- LOG_TB("%s: val " ADDRX "\n", __func__, val);
+ LOG_TB("%s: val " TARGET_FMT_lx "\n", __func__, val);
env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000);
if (val & 0x80000000)
ppc_set_irq(env, PPC_INTERRUPT_PIT, 0);
@@ -949,7 +947,7 @@ void store_booke_tcr (CPUState *env, target_ulong val)
ppc_tb_t *tb_env;
tb_env = env->tb_env;
- LOG_TB("%s: val " ADDRX "\n", __func__, val);
+ LOG_TB("%s: val " TARGET_FMT_lx "\n", __func__, val);
env->spr[SPR_40x_TCR] = val & 0xFFC00000;
start_stop_pit(env, tb_env, 1);
cpu_4xx_wdt_cb(env);
diff --git a/hw/ppc405_boards.c b/hw/ppc405_boards.c
index f2b4a8419..0377d1c6c 100644
--- a/hw/ppc405_boards.c
+++ b/hw/ppc405_boards.c
@@ -221,8 +221,8 @@ static void ref405ep_init (ram_addr_t ram_size,
bios_offset = qemu_ram_alloc(bios_size);
fl_sectors = (bios_size + 65535) >> 16;
#ifdef DEBUG_BOARD_INIT
- printf("Register parallel flash %d size " ADDRX " at offset %08lx "
- " addr " ADDRX " '%s' %d\n",
+ printf("Register parallel flash %d size " TARGET_FMT_lx
+ " at offset %08lx addr " TARGET_FMT_lx " '%s' %d\n",
fl_idx, bios_size, bios_offset, -bios_size,
bdrv_get_device_name(dinfo->bdrv), fl_sectors);
#endif
@@ -536,8 +536,8 @@ static void taihu_405ep_init(ram_addr_t ram_size,
fl_sectors = (bios_size + 65535) >> 16;
bios_offset = qemu_ram_alloc(bios_size);
#ifdef DEBUG_BOARD_INIT
- printf("Register parallel flash %d size " ADDRX " at offset %08lx "
- " addr " ADDRX " '%s' %d\n",
+ printf("Register parallel flash %d size " TARGET_FMT_lx
+ " at offset %08lx addr " TARGET_FMT_lx " '%s' %d\n",
fl_idx, bios_size, bios_offset, -bios_size,
bdrv_get_device_name(dinfo->bdrv), fl_sectors);
#endif
@@ -577,8 +577,8 @@ static void taihu_405ep_init(ram_addr_t ram_size,
bios_size = 32 * 1024 * 1024;
fl_sectors = (bios_size + 65535) >> 16;
#ifdef DEBUG_BOARD_INIT
- printf("Register parallel flash %d size " ADDRX " at offset %08lx "
- " addr " ADDRX " '%s'\n",
+ printf("Register parallel flash %d size " TARGET_FMT_lx
+ " at offset %08lx addr " TARGET_FMT_lx " '%s'\n",
fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
bdrv_get_device_name(dinfo->bdrv));
#endif
diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c
index e050b75e4..aa2f0db03 100644
--- a/hw/ppc405_uc.c
+++ b/hw/ppc405_uc.c
@@ -267,7 +267,7 @@ static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)
uint32_t ret;
#ifdef DEBUG_OPBA
- printf("%s: addr " PADDRX "\n", __func__, addr);
+ printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
opba = opaque;
switch (addr) {
@@ -291,7 +291,8 @@ static void opba_writeb (void *opaque,
ppc4xx_opba_t *opba;
#ifdef DEBUG_OPBA
- printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
+ printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
+ value);
#endif
opba = opaque;
switch (addr) {
@@ -311,7 +312,7 @@ static uint32_t opba_readw (void *opaque, target_phys_addr_t addr)
uint32_t ret;
#ifdef DEBUG_OPBA
- printf("%s: addr " PADDRX "\n", __func__, addr);
+ printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
ret = opba_readb(opaque, addr) << 8;
ret |= opba_readb(opaque, addr + 1);
@@ -323,7 +324,8 @@ static void opba_writew (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
#ifdef DEBUG_OPBA
- printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
+ printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
+ value);
#endif
opba_writeb(opaque, addr, value >> 8);
opba_writeb(opaque, addr + 1, value);
@@ -334,7 +336,7 @@ static uint32_t opba_readl (void *opaque, target_phys_addr_t addr)
uint32_t ret;
#ifdef DEBUG_OPBA
- printf("%s: addr " PADDRX "\n", __func__, addr);
+ printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
ret = opba_readb(opaque, addr) << 24;
ret |= opba_readb(opaque, addr + 1) << 16;
@@ -346,7 +348,8 @@ static void opba_writel (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
#ifdef DEBUG_OPBA
- printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
+ printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
+ value);
#endif
opba_writeb(opaque, addr, value >> 24);
opba_writeb(opaque, addr + 1, value >> 16);
@@ -380,7 +383,7 @@ static void ppc4xx_opba_init(target_phys_addr_t base)
opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
#ifdef DEBUG_OPBA
- printf("%s: offset " PADDRX "\n", __func__, base);
+ printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
io = cpu_register_io_memory(opba_read, opba_write, opba);
cpu_register_physical_memory(base, 0x002, io);
@@ -744,7 +747,7 @@ static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
gpio = opaque;
#ifdef DEBUG_GPIO
- printf("%s: addr " PADDRX "\n", __func__, addr);
+ printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
return 0;
@@ -757,7 +760,8 @@ static void ppc405_gpio_writeb (void *opaque,
gpio = opaque;
#ifdef DEBUG_GPIO
- printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
+ printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
+ value);
#endif
}
@@ -767,7 +771,7 @@ static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
gpio = opaque;
#ifdef DEBUG_GPIO
- printf("%s: addr " PADDRX "\n", __func__, addr);
+ printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
return 0;
@@ -780,7 +784,8 @@ static void ppc405_gpio_writew (void *opaque,
gpio = opaque;
#ifdef DEBUG_GPIO
- printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
+ printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
+ value);
#endif
}
@@ -790,7 +795,7 @@ static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
gpio = opaque;
#ifdef DEBUG_GPIO
- printf("%s: addr " PADDRX "\n", __func__, addr);
+ printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
return 0;
@@ -803,7 +808,8 @@ static void ppc405_gpio_writel (void *opaque,
gpio = opaque;
#ifdef DEBUG_GPIO
- printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
+ printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
+ value);
#endif
}
@@ -833,7 +839,7 @@ static void ppc405_gpio_init(target_phys_addr_t base)
gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
#ifdef DEBUG_GPIO
- printf("%s: offset " PADDRX "\n", __func__, base);
+ printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio);
cpu_register_physical_memory(base, 0x038, io);
@@ -1035,7 +1041,7 @@ static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
uint32_t ret;
#ifdef DEBUG_I2C
- printf("%s: addr " PADDRX "\n", __func__, addr);
+ printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
i2c = opaque;
switch (addr) {
@@ -1090,7 +1096,7 @@ static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
break;
}
#ifdef DEBUG_I2C
- printf("%s: addr " PADDRX " %02" PRIx32 "\n", __func__, addr, ret);
+ printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, ret);
#endif
return ret;
@@ -1102,7 +1108,8 @@ static void ppc4xx_i2c_writeb (void *opaque,
ppc4xx_i2c_t *i2c;
#ifdef DEBUG_I2C
- printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
+ printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
+ value);
#endif
i2c = opaque;
switch (addr) {
@@ -1160,7 +1167,7 @@ static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr)
uint32_t ret;
#ifdef DEBUG_I2C
- printf("%s: addr " PADDRX "\n", __func__, addr);
+ printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
ret = ppc4xx_i2c_readb(opaque, addr) << 8;
ret |= ppc4xx_i2c_readb(opaque, addr + 1);
@@ -1172,7 +1179,8 @@ static void ppc4xx_i2c_writew (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
#ifdef DEBUG_I2C
- printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
+ printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
+ value);
#endif
ppc4xx_i2c_writeb(opaque, addr, value >> 8);
ppc4xx_i2c_writeb(opaque, addr + 1, value);
@@ -1183,7 +1191,7 @@ static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr)
uint32_t ret;
#ifdef DEBUG_I2C
- printf("%s: addr " PADDRX "\n", __func__, addr);
+ printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
ret = ppc4xx_i2c_readb(opaque, addr) << 24;
ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
@@ -1197,7 +1205,8 @@ static void ppc4xx_i2c_writel (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
#ifdef DEBUG_I2C
- printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
+ printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
+ value);
#endif
ppc4xx_i2c_writeb(opaque, addr, value >> 24);
ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
@@ -1241,7 +1250,7 @@ static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
i2c->irq = irq;
#ifdef DEBUG_I2C
- printf("%s: offset " PADDRX "\n", __func__, base);
+ printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
io = cpu_register_io_memory(i2c_read, i2c_write, i2c);
cpu_register_physical_memory(base, 0x011, io);
@@ -1269,7 +1278,7 @@ struct ppc4xx_gpt_t {
static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr)
{
#ifdef DEBUG_GPT
- printf("%s: addr " PADDRX "\n", __func__, addr);
+ printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
/* XXX: generate a bus fault */
return -1;
@@ -1279,7 +1288,8 @@ static void ppc4xx_gpt_writeb (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
#ifdef DEBUG_I2C
- printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
+ printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
+ value);
#endif
/* XXX: generate a bus fault */
}
@@ -1287,7 +1297,7 @@ static void ppc4xx_gpt_writeb (void *opaque,
static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr)
{
#ifdef DEBUG_GPT
- printf("%s: addr " PADDRX "\n", __func__, addr);
+ printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
/* XXX: generate a bus fault */
return -1;
@@ -1297,7 +1307,8 @@ static void ppc4xx_gpt_writew (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
#ifdef DEBUG_I2C
- printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
+ printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
+ value);
#endif
/* XXX: generate a bus fault */
}
@@ -1361,7 +1372,7 @@ static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
int idx;
#ifdef DEBUG_GPT
- printf("%s: addr " PADDRX "\n", __func__, addr);
+ printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
gpt = opaque;
switch (addr) {
@@ -1416,7 +1427,8 @@ static void ppc4xx_gpt_writel (void *opaque,
int idx;
#ifdef DEBUG_I2C
- printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
+ printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
+ value);
#endif
gpt = opaque;
switch (addr) {
@@ -1522,7 +1534,7 @@ static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
}
gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt);
#ifdef DEBUG_GPT
- printf("%s: offset " PADDRX "\n", __func__, base);
+ printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
io = cpu_register_io_memory(gpt_read, gpt_write, gpt);
cpu_register_physical_memory(base, 0x0d4, io);
diff --git a/hw/ppc4xx_devs.c b/hw/ppc4xx_devs.c
index 8f8a44c39..0b1c93b80 100644
--- a/hw/ppc4xx_devs.c
+++ b/hw/ppc4xx_devs.c
@@ -235,7 +235,7 @@ static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
uic = opaque;
dcrn -= uic->dcr_base;
- LOG_UIC("%s: dcr %d val " ADDRX "\n", __func__, dcrn, val);
+ LOG_UIC("%s: dcr %d val " TARGET_FMT_lx "\n", __func__, dcrn, val);
switch (dcrn) {
case DCR_UICSR:
uic->uicsr &= ~val;
@@ -368,7 +368,8 @@ static uint32_t sdram_bcr (target_phys_addr_t ram_base,
bcr = 0x000C0000;
break;
default:
- printf("%s: invalid RAM size " PADDRX "\n", __func__, ram_size);
+ printf("%s: invalid RAM size " TARGET_FMT_plx "\n", __func__,
+ ram_size);
return 0x00000000;
}
bcr |= ram_base & 0xFF800000;
@@ -377,7 +378,7 @@ static uint32_t sdram_bcr (target_phys_addr_t ram_base,
return bcr;
}
-static always_inline target_phys_addr_t sdram_base (uint32_t bcr)
+static inline target_phys_addr_t sdram_base(uint32_t bcr)
{
return bcr & 0xFF800000;
}
@@ -401,7 +402,7 @@ static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
if (*bcrp & 0x00000001) {
/* Unmap RAM */
#ifdef DEBUG_SDRAM
- printf("%s: unmap RAM area " PADDRX " " ADDRX "\n",
+ printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
__func__, sdram_base(*bcrp), sdram_size(*bcrp));
#endif
cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp),
@@ -410,7 +411,7 @@ static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
*bcrp = bcr & 0xFFDEE001;
if (enabled && (bcr & 0x00000001)) {
#ifdef DEBUG_SDRAM
- printf("%s: Map RAM area " PADDRX " " ADDRX "\n",
+ printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
__func__, sdram_base(bcr), sdram_size(bcr));
#endif
cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr),
@@ -439,7 +440,7 @@ static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
for (i = 0; i < sdram->nbanks; i++) {
#ifdef DEBUG_SDRAM
- printf("%s: Unmap RAM area " PADDRX " " ADDRX "\n",
+ printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
__func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
#endif
cpu_register_physical_memory(sdram_base(sdram->bcr[i]),
diff --git a/hw/ppc_oldworld.c b/hw/ppc_oldworld.c
index 549ba0cde..6a283059c 100644
--- a/hw/ppc_oldworld.c
+++ b/hw/ppc_oldworld.c
@@ -48,7 +48,9 @@ static int vga_osi_call (CPUState *env)
static int vga_vbl_enabled;
int linesize;
- // printf("osi_call R5=" REGX "\n", ppc_dump_gpr(env, 5));
+#if 0
+ printf("osi_call R5=%016" PRIx64 "\n", ppc_dump_gpr(env, 5));
+#endif
/* same handler as PearPC, coming from the original MOL video
driver. */
@@ -100,7 +102,7 @@ static int vga_osi_call (CPUState *env)
/* R6 = x, R7 = y, R8 = visible, R9 = data */
break;
default:
- fprintf(stderr, "unsupported OSI call R5=" REGX "\n",
+ fprintf(stderr, "unsupported OSI call R5=%016" PRIx64 "\n",
ppc_dump_gpr(env, 5));
break;
}
diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
index 97190a2b7..adfa44d0a 100644
--- a/hw/ppc_prep.c
+++ b/hw/ppc_prep.c
@@ -112,16 +112,22 @@ static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
static void _PPC_intack_write (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
-// printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
+#if 0
+ printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
+ value);
+#endif
}
-static always_inline uint32_t _PPC_intack_read (target_phys_addr_t addr)
+static inline uint32_t _PPC_intack_read(target_phys_addr_t addr)
{
uint32_t retval = 0;
if ((addr & 0xf) == 0)
retval = pic_intack_read(isa_pic);
-// printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
+#if 0
+ printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
+ retval);
+#endif
return retval;
}
@@ -191,7 +197,8 @@ static struct {
static void PPC_XCSR_writeb (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
- printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
+ printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
+ value);
}
static void PPC_XCSR_writew (void *opaque,
@@ -200,7 +207,8 @@ static void PPC_XCSR_writew (void *opaque,
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap16(value);
#endif
- printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
+ printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
+ value);
}
static void PPC_XCSR_writel (void *opaque,
@@ -209,14 +217,16 @@ static void PPC_XCSR_writel (void *opaque,
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap32(value);
#endif
- printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
+ printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
+ value);
}
static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
{
uint32_t retval = 0;
- printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
+ printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
+ retval);
return retval;
}
@@ -225,7 +235,8 @@ static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
{
uint32_t retval = 0;
- printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
+ printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
+ retval);
#ifdef TARGET_WORDS_BIGENDIAN
retval = bswap16(retval);
#endif
@@ -237,7 +248,8 @@ static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
{
uint32_t retval = 0;
- printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
+ printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
+ retval);
#ifdef TARGET_WORDS_BIGENDIAN
retval = bswap32(retval);
#endif
@@ -426,9 +438,8 @@ static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
return retval;
}
-static always_inline target_phys_addr_t prep_IO_address (sysctrl_t *sysctrl,
- target_phys_addr_t
- addr)
+static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl,
+ target_phys_addr_t addr)
{
if (sysctrl->contiguous_map == 0) {
/* 64 KB contiguous space for IOs */
@@ -470,7 +481,7 @@ static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap16(value);
#endif
- PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value);
+ PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
cpu_outw(NULL, addr, value);
}
@@ -484,7 +495,7 @@ static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
#ifdef TARGET_WORDS_BIGENDIAN
ret = bswap16(ret);
#endif
- PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret);
+ PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
return ret;
}
@@ -498,7 +509,7 @@ static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap32(value);
#endif
- PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value);
+ PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
cpu_outl(NULL, addr, value);
}
@@ -512,7 +523,7 @@ static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
#ifdef TARGET_WORDS_BIGENDIAN
ret = bswap32(ret);
#endif
- PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret);
+ PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
return ret;
}
diff --git a/hw/slavio_intctl.c b/hw/slavio_intctl.c
index dbea1f93a..c9bad2607 100644
--- a/hw/slavio_intctl.c
+++ b/hw/slavio_intctl.c
@@ -220,11 +220,14 @@ static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
slavio_intctlm_mem_writel,
};
-void slavio_pic_info(Monitor *mon, void *opaque)
+void slavio_pic_info(Monitor *mon, DeviceState *dev)
{
- SLAVIO_INTCTLState *s = opaque;
+ SysBusDevice *sd;
+ SLAVIO_INTCTLState *s;
int i;
+ sd = sysbus_from_qdev(dev);
+ s = FROM_SYSBUS(SLAVIO_INTCTLState, sd);
for (i = 0; i < MAX_CPUS; i++) {
monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i,
s->slaves[i].intreg_pending);
@@ -233,15 +236,18 @@ void slavio_pic_info(Monitor *mon, void *opaque)
s->intregm_pending, s->intregm_disabled);
}
-void slavio_irq_info(Monitor *mon, void *opaque)
+void slavio_irq_info(Monitor *mon, DeviceState *dev)
{
#ifndef DEBUG_IRQ_COUNT
monitor_printf(mon, "irq statistic code not compiled.\n");
#else
- SLAVIO_INTCTLState *s = opaque;
+ SysBusDevice *sd;
+ SLAVIO_INTCTLState *s;
int i;
int64_t count;
+ sd = sysbus_from_qdev(dev);
+ s = FROM_SYSBUS(SLAVIO_INTCTLState, sd);
monitor_printf(mon, "IRQ statistics:\n");
for (i = 0; i < 32; i++) {
count = s->irq_count[i];
diff --git a/hw/sun4m.c b/hw/sun4m.c
index ddc295a9a..88a0b2511 100644
--- a/hw/sun4m.c
+++ b/hw/sun4m.c
@@ -209,7 +209,7 @@ static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
m48t59_write(nvram, i, image[i]);
}
-static void *slavio_intctl;
+static DeviceState *slavio_intctl;
void pic_info(Monitor *mon)
{
@@ -748,7 +748,6 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
unsigned long kernel_size;
BlockDriverState *fd[MAX_FD];
void *fw_cfg;
- DeviceState *dev;
DriveInfo *dinfo;
/* init CPUs */
@@ -768,16 +767,16 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
prom_init(hwdef->slavio_base, bios_name);
- dev = slavio_intctl_init(hwdef->intctl_base,
- hwdef->intctl_base + 0x10000ULL,
- cpu_irqs,
- 7);
+ slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
+ hwdef->intctl_base + 0x10000ULL,
+ cpu_irqs,
+ 7);
for (i = 0; i < 32; i++) {
- slavio_irq[i] = qdev_get_gpio_in(dev, i);
+ slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
}
for (i = 0; i < MAX_CPUS; i++) {
- slavio_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
+ slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
}
if (hwdef->idreg_base) {
diff --git a/hw/sun4m.h b/hw/sun4m.h
index 9f540920a..ce97ee5a7 100644
--- a/hw/sun4m.h
+++ b/hw/sun4m.h
@@ -23,8 +23,8 @@ static inline void sparc_iommu_memory_write(void *opaque,
}
/* slavio_intctl.c */
-void slavio_pic_info(Monitor *mon, void *opaque);
-void slavio_irq_info(Monitor *mon, void *opaque);
+void slavio_pic_info(Monitor *mon, DeviceState *dev);
+void slavio_irq_info(Monitor *mon, DeviceState *dev);
/* sun4c_intctl.c */
void sun4c_pic_info(Monitor *mon, void *opaque);
diff --git a/hw/vga.c b/hw/vga.c
index 887e6404e..b467520dd 100644
--- a/hw/vga.c
+++ b/hw/vga.c
@@ -151,6 +151,8 @@ static uint16_t expand2[256];
static uint8_t expand4to8[16];
static void vga_screen_dump(void *opaque, const char *filename);
+static char *screen_dump_filename;
+static DisplayChangeListener *screen_dump_dcl;
static void vga_dumb_update_retrace_info(VGAState *s)
{
@@ -2591,9 +2593,13 @@ device_init(vga_register);
/********************************************************/
/* vga screen dump */
-static void vga_save_dpy_update(DisplayState *s,
+static void vga_save_dpy_update(DisplayState *ds,
int x, int y, int w, int h)
{
+ if (screen_dump_filename) {
+ ppm_save(screen_dump_filename, ds->surface);
+ screen_dump_filename = NULL;
+ }
}
static void vga_save_dpy_resize(DisplayState *s)
@@ -2642,70 +2648,16 @@ int ppm_save(const char *filename, struct DisplaySurface *ds)
return 0;
}
-static void vga_screen_dump_blank(VGAState *s, const char *filename)
-{
- FILE *f;
- unsigned int y, x, w, h;
- unsigned char blank_sample[3] = { 0, 0, 0 };
-
- w = s->last_scr_width;
- h = s->last_scr_height;
-
- f = fopen(filename, "wb");
- if (!f)
- return;
- fprintf(f, "P6\n%d %d\n%d\n", w, h, 255);
- for (y = 0; y < h; y++) {
- for (x = 0; x < w; x++) {
- fwrite(blank_sample, 3, 1, f);
- }
- }
- fclose(f);
-}
-
-static void vga_screen_dump_common(VGAState *s, const char *filename,
- int w, int h)
-{
- DisplayState *saved_ds, ds1, *ds = &ds1;
- DisplayChangeListener dcl;
-
- /* XXX: this is a little hackish */
- vga_invalidate_display(s);
- saved_ds = s->ds;
-
- memset(ds, 0, sizeof(DisplayState));
- memset(&dcl, 0, sizeof(DisplayChangeListener));
- dcl.dpy_update = vga_save_dpy_update;
- dcl.dpy_resize = vga_save_dpy_resize;
- dcl.dpy_refresh = vga_save_dpy_refresh;
- register_displaychangelistener(ds, &dcl);
- ds->allocator = &default_allocator;
- ds->surface = qemu_create_displaysurface(ds, w, h);
-
- s->ds = ds;
- s->graphic_mode = -1;
- vga_update_display(s);
-
- ppm_save(filename, ds->surface);
-
- qemu_free_displaysurface(ds);
- s->ds = saved_ds;
-}
-
-static void vga_screen_dump_graphic(VGAState *s, const char *filename)
+static DisplayChangeListener* vga_screen_dump_init(DisplayState *ds)
{
- int w, h;
+ DisplayChangeListener *dcl;
- s->get_resolution(s, &w, &h);
- vga_screen_dump_common(s, filename, w, h);
-}
-
-static void vga_screen_dump_text(VGAState *s, const char *filename)
-{
- int w, h, cwidth, cheight;
-
- vga_get_text_resolution(s, &w, &h, &cwidth, &cheight);
- vga_screen_dump_common(s, filename, w * cwidth, h * cheight);
+ dcl = qemu_mallocz(sizeof(DisplayChangeListener));
+ dcl->dpy_update = vga_save_dpy_update;
+ dcl->dpy_resize = vga_save_dpy_resize;
+ dcl->dpy_refresh = vga_save_dpy_refresh;
+ register_displaychangelistener(ds, dcl);
+ return dcl;
}
/* save the vga display in a PPM image even if no display is
@@ -2714,11 +2666,11 @@ static void vga_screen_dump(void *opaque, const char *filename)
{
VGAState *s = (VGAState *)opaque;
- if (!(s->ar_index & 0x20))
- vga_screen_dump_blank(s, filename);
- else if (s->gr[6] & 1)
- vga_screen_dump_graphic(s, filename);
- else
- vga_screen_dump_text(s, filename);
+ if (!screen_dump_dcl)
+ screen_dump_dcl = vga_screen_dump_init(s->ds);
+
+ screen_dump_filename = (char *)filename;
vga_invalidate_display(s);
+ vga_hw_update();
}
+
diff --git a/hw/zaurus.c b/hw/zaurus.c
index e52f29b57..78a120c9d 100644
--- a/hw/zaurus.c
+++ b/hw/zaurus.c
@@ -155,7 +155,7 @@ static CPUWriteMemoryFunc *scoop_writefn[] = {
void scoop_gpio_set(void *opaque, int line, int level)
{
- ScoopInfo *s = (ScoopInfo *) s;
+ ScoopInfo *s = (ScoopInfo *) opaque;
if (level)
s->gpio_level |= (1 << line);
diff --git a/linux-user/main.c b/linux-user/main.c
index aa381f60d..a628c0172 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -1140,7 +1140,7 @@ void cpu_loop(CPUPPCState *env)
"Aborting\n");
break;
case POWERPC_EXCP_DSI: /* Data storage exception */
- EXCP_DUMP(env, "Invalid data memory access: 0x" ADDRX "\n",
+ EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
env->spr[SPR_DAR]);
/* XXX: check this. Seems bugged */
switch (env->error_code & 0xFF000000) {
@@ -1172,8 +1172,8 @@ void cpu_loop(CPUPPCState *env)
queue_signal(env, info.si_signo, &info);
break;
case POWERPC_EXCP_ISI: /* Instruction storage exception */
- EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" ADDRX "\n",
- env->spr[SPR_SRR0]);
+ EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
+ "\n", env->spr[SPR_SRR0]);
/* XXX: check this */
switch (env->error_code & 0xFF000000) {
case 0x40000000:
diff --git a/migration-exec.c b/migration-exec.c
index e3616be5f..ef4620f79 100644
--- a/migration-exec.c
+++ b/migration-exec.c
@@ -73,10 +73,7 @@ MigrationState *exec_start_outgoing_migration(const char *command,
goto err_after_open;
}
- if (fcntl(s->fd, F_SETFD, O_NONBLOCK) == -1) {
- dprintf("Unable to set nonblocking mode on file descriptor\n");
- goto err_after_open;
- }
+ socket_set_nonblock(s->fd);
s->opaque = qemu_popen(f, "w");
diff --git a/monitor.c b/monitor.c
index 50a3cd257..002092263 100644
--- a/monitor.c
+++ b/monitor.c
@@ -3086,6 +3086,9 @@ static void monitor_find_completion(const char *cmdline)
}
}
str = args[nb_args - 1];
+ if (*ptype == '-' && ptype[1] != '\0') {
+ ptype += 2;
+ }
switch(*ptype) {
case 'F':
/* file completion */
diff --git a/net.c b/net.c
index 1e845cf00..e414b349c 100644
--- a/net.c
+++ b/net.c
@@ -3088,7 +3088,7 @@ void do_set_link(Monitor *mon, const char *name, const char *up_or_down)
done:
if (!vc) {
- monitor_printf(mon, "could not find network device '%s'", name);
+ monitor_printf(mon, "could not find network device '%s'\n", name);
return;
}
diff --git a/osdep.h b/osdep.h
index ffbf221d7..2517b1a36 100644
--- a/osdep.h
+++ b/osdep.h
@@ -48,12 +48,9 @@
#endif
#ifndef always_inline
-#if (__GNUC__ < 3) || defined(__APPLE__)
-#define always_inline inline
-#else
-#define always_inline __attribute__ (( always_inline )) __inline__
+#if !((__GNUC__ < 3) || defined(__APPLE__))
#ifdef __OPTIMIZE__
-#define inline always_inline
+#define inline __attribute__ (( always_inline )) __inline__
#endif
#endif
#else
diff --git a/sdl.c b/sdl.c
index 36fb07f22..33edfb8dd 100644
--- a/sdl.c
+++ b/sdl.c
@@ -771,6 +771,9 @@ static void sdl_mouse_define(int width, int height, int bpp,
line = image;
for (x = 0; x < width; x ++, dst ++) {
switch (bpp) {
+ case 32:
+ src = *(line ++); src |= *(line ++); src |= *(line ++); line++;
+ break;
case 24:
src = *(line ++); src |= *(line ++); src |= *(line ++);
break;
diff --git a/sysemu.h b/sysemu.h
index c9f8a5a93..bcb470bb3 100644
--- a/sysemu.h
+++ b/sysemu.h
@@ -100,10 +100,17 @@ typedef enum DisplayType
extern int autostart;
extern int bios_size;
-extern int cirrus_vga_enabled;
-extern int std_vga_enabled;
-extern int vmsvga_enabled;
-extern int xenfb_enabled;
+
+typedef enum {
+ VGA_NONE, VGA_STD, VGA_CIRRUS, VGA_VMWARE, VGA_XENFB
+} VGAInterfaceType;
+
+extern int vga_interface_type;
+#define cirrus_vga_enabled (vga_interface_type == VGA_CIRRUS)
+#define std_vga_enabled (vga_interface_type == VGA_STD)
+#define xenfb_enabled (vga_interface_type == VGA_XENFB)
+#define vmsvga_enabled (vga_interface_type == VGA_VMWARE)
+
extern int graphic_width;
extern int graphic_height;
extern int graphic_depth;
diff --git a/target-alpha/exec.h b/target-alpha/exec.h
index 35d6a1677..3533eb171 100644
--- a/target-alpha/exec.h
+++ b/target-alpha/exec.h
@@ -39,20 +39,21 @@ register struct CPUAlphaState *env asm(AREG0);
#include "softmmu_exec.h"
#endif /* !defined(CONFIG_USER_ONLY) */
-static always_inline void env_to_regs(void)
+static inline void env_to_regs(void)
{
}
-static always_inline void regs_to_env(void)
+static inline void regs_to_env(void)
{
}
-static always_inline int cpu_has_work(CPUState *env)
+static inline int cpu_has_work(CPUState *env)
{
return (env->interrupt_request & CPU_INTERRUPT_HARD);
}
-static always_inline int cpu_halted(CPUState *env) {
+static inline int cpu_halted(CPUState *env)
+{
if (!env->halted)
return 0;
if (cpu_has_work(env)) {
diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c
index 22812ca46..e9d2732df 100644
--- a/target-alpha/op_helper.c
+++ b/target-alpha/op_helper.c
@@ -200,7 +200,7 @@ uint64_t helper_cttz (uint64_t arg)
return ctz64(arg);
}
-static always_inline uint64_t byte_zap (uint64_t op, uint8_t mskb)
+static inline uint64_t byte_zap(uint64_t op, uint8_t mskb)
{
uint64_t mask;
@@ -322,7 +322,7 @@ uint64_t helper_cmpbge (uint64_t op1, uint64_t op2)
/* Floating point helpers */
/* F floating (VAX) */
-static always_inline uint64_t float32_to_f (float32 fa)
+static inline uint64_t float32_to_f(float32 fa)
{
uint64_t r, exp, mant, sig;
CPU_FloatU a;
@@ -355,7 +355,7 @@ static always_inline uint64_t float32_to_f (float32 fa)
return r;
}
-static always_inline float32 f_to_float32 (uint64_t a)
+static inline float32 f_to_float32(uint64_t a)
{
uint32_t exp, mant_sig;
CPU_FloatU r;
@@ -449,7 +449,7 @@ uint64_t helper_sqrtf (uint64_t t)
/* G floating (VAX) */
-static always_inline uint64_t float64_to_g (float64 fa)
+static inline uint64_t float64_to_g(float64 fa)
{
uint64_t r, exp, mant, sig;
CPU_DoubleU a;
@@ -482,7 +482,7 @@ static always_inline uint64_t float64_to_g (float64 fa)
return r;
}
-static always_inline float64 g_to_float64 (uint64_t a)
+static inline float64 g_to_float64(uint64_t a)
{
uint64_t exp, mant_sig;
CPU_DoubleU r;
@@ -576,7 +576,7 @@ uint64_t helper_sqrtg (uint64_t a)
/* S floating (single) */
-static always_inline uint64_t float32_to_s (float32 fa)
+static inline uint64_t float32_to_s(float32 fa)
{
CPU_FloatU a;
uint64_t r;
@@ -589,7 +589,7 @@ static always_inline uint64_t float32_to_s (float32 fa)
return r;
}
-static always_inline float32 s_to_float32 (uint64_t a)
+static inline float32 s_to_float32(uint64_t a)
{
CPU_FloatU r;
r.l = ((a >> 32) & 0xc0000000) | ((a >> 29) & 0x3fffffff);
@@ -660,7 +660,7 @@ uint64_t helper_sqrts (uint64_t a)
/* T floating (double) */
-static always_inline float64 t_to_float64 (uint64_t a)
+static inline float64 t_to_float64(uint64_t a)
{
/* Memory format is the same as float64 */
CPU_DoubleU r;
@@ -668,7 +668,7 @@ static always_inline float64 t_to_float64 (uint64_t a)
return r.d;
}
-static always_inline uint64_t float64_to_t (float64 fa)
+static inline uint64_t float64_to_t(float64 fa)
{
/* Memory format is the same as float64 */
CPU_DoubleU r;
@@ -939,7 +939,7 @@ uint64_t helper_cvtlq (uint64_t a)
return (int64_t)((int32_t)((a >> 32) | ((a >> 29) & 0x3FFFFFFF)));
}
-static always_inline uint64_t __helper_cvtql (uint64_t a, int s, int v)
+static inline uint64_t __helper_cvtql(uint64_t a, int s, int v)
{
uint64_t r;
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 1fc5119cb..1dd85629b 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -103,8 +103,7 @@ static void alpha_translate_init(void)
done_init = 1;
}
-static always_inline void gen_excp (DisasContext *ctx,
- int exception, int error_code)
+static inline void gen_excp(DisasContext *ctx, int exception, int error_code)
{
TCGv_i32 tmp1, tmp2;
@@ -116,12 +115,12 @@ static always_inline void gen_excp (DisasContext *ctx,
tcg_temp_free_i32(tmp1);
}
-static always_inline void gen_invalid (DisasContext *ctx)
+static inline void gen_invalid(DisasContext *ctx)
{
gen_excp(ctx, EXCP_OPCDEC, 0);
}
-static always_inline void gen_qemu_ldf (TCGv t0, TCGv t1, int flags)
+static inline void gen_qemu_ldf(TCGv t0, TCGv t1, int flags)
{
TCGv tmp = tcg_temp_new();
TCGv_i32 tmp32 = tcg_temp_new_i32();
@@ -132,7 +131,7 @@ static always_inline void gen_qemu_ldf (TCGv t0, TCGv t1, int flags)
tcg_temp_free(tmp);
}
-static always_inline void gen_qemu_ldg (TCGv t0, TCGv t1, int flags)
+static inline void gen_qemu_ldg(TCGv t0, TCGv t1, int flags)
{
TCGv tmp = tcg_temp_new();
tcg_gen_qemu_ld64(tmp, t1, flags);
@@ -140,7 +139,7 @@ static always_inline void gen_qemu_ldg (TCGv t0, TCGv t1, int flags)
tcg_temp_free(tmp);
}
-static always_inline void gen_qemu_lds (TCGv t0, TCGv t1, int flags)
+static inline void gen_qemu_lds(TCGv t0, TCGv t1, int flags)
{
TCGv tmp = tcg_temp_new();
TCGv_i32 tmp32 = tcg_temp_new_i32();
@@ -151,22 +150,23 @@ static always_inline void gen_qemu_lds (TCGv t0, TCGv t1, int flags)
tcg_temp_free(tmp);
}
-static always_inline void gen_qemu_ldl_l (TCGv t0, TCGv t1, int flags)
+static inline void gen_qemu_ldl_l(TCGv t0, TCGv t1, int flags)
{
tcg_gen_mov_i64(cpu_lock, t1);
tcg_gen_qemu_ld32s(t0, t1, flags);
}
-static always_inline void gen_qemu_ldq_l (TCGv t0, TCGv t1, int flags)
+static inline void gen_qemu_ldq_l(TCGv t0, TCGv t1, int flags)
{
tcg_gen_mov_i64(cpu_lock, t1);
tcg_gen_qemu_ld64(t0, t1, flags);
}
-static always_inline void gen_load_mem (DisasContext *ctx,
- void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1, int flags),
- int ra, int rb, int32_t disp16,
- int fp, int clear)
+static inline void gen_load_mem(DisasContext *ctx,
+ void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1,
+ int flags),
+ int ra, int rb, int32_t disp16, int fp,
+ int clear)
{
TCGv addr;
@@ -190,7 +190,7 @@ static always_inline void gen_load_mem (DisasContext *ctx,
tcg_temp_free(addr);
}
-static always_inline void gen_qemu_stf (TCGv t0, TCGv t1, int flags)
+static inline void gen_qemu_stf(TCGv t0, TCGv t1, int flags)
{
TCGv_i32 tmp32 = tcg_temp_new_i32();
TCGv tmp = tcg_temp_new();
@@ -201,7 +201,7 @@ static always_inline void gen_qemu_stf (TCGv t0, TCGv t1, int flags)
tcg_temp_free_i32(tmp32);
}
-static always_inline void gen_qemu_stg (TCGv t0, TCGv t1, int flags)
+static inline void gen_qemu_stg(TCGv t0, TCGv t1, int flags)
{
TCGv tmp = tcg_temp_new();
gen_helper_g_to_memory(tmp, t0);
@@ -209,7 +209,7 @@ static always_inline void gen_qemu_stg (TCGv t0, TCGv t1, int flags)
tcg_temp_free(tmp);
}
-static always_inline void gen_qemu_sts (TCGv t0, TCGv t1, int flags)
+static inline void gen_qemu_sts(TCGv t0, TCGv t1, int flags)
{
TCGv_i32 tmp32 = tcg_temp_new_i32();
TCGv tmp = tcg_temp_new();
@@ -220,7 +220,7 @@ static always_inline void gen_qemu_sts (TCGv t0, TCGv t1, int flags)
tcg_temp_free_i32(tmp32);
}
-static always_inline void gen_qemu_stl_c (TCGv t0, TCGv t1, int flags)
+static inline void gen_qemu_stl_c(TCGv t0, TCGv t1, int flags)
{
int l1, l2;
@@ -236,7 +236,7 @@ static always_inline void gen_qemu_stl_c (TCGv t0, TCGv t1, int flags)
tcg_gen_movi_i64(cpu_lock, -1);
}
-static always_inline void gen_qemu_stq_c (TCGv t0, TCGv t1, int flags)
+static inline void gen_qemu_stq_c(TCGv t0, TCGv t1, int flags)
{
int l1, l2;
@@ -252,10 +252,11 @@ static always_inline void gen_qemu_stq_c (TCGv t0, TCGv t1, int flags)
tcg_gen_movi_i64(cpu_lock, -1);
}
-static always_inline void gen_store_mem (DisasContext *ctx,
- void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1, int flags),
- int ra, int rb, int32_t disp16,
- int fp, int clear, int local)
+static inline void gen_store_mem(DisasContext *ctx,
+ void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1,
+ int flags),
+ int ra, int rb, int32_t disp16, int fp,
+ int clear, int local)
{
TCGv addr;
if (local)
@@ -288,9 +289,8 @@ static always_inline void gen_store_mem (DisasContext *ctx,
tcg_temp_free(addr);
}
-static always_inline void gen_bcond (DisasContext *ctx,
- TCGCond cond,
- int ra, int32_t disp, int mask)
+static inline void gen_bcond(DisasContext *ctx, TCGCond cond, int ra,
+ int32_t disp, int mask)
{
int l1, l2;
@@ -317,8 +317,8 @@ static always_inline void gen_bcond (DisasContext *ctx,
gen_set_label(l2);
}
-static always_inline void gen_fbcond (DisasContext *ctx, int opc,
- int ra, int32_t disp16)
+static inline void gen_fbcond(DisasContext *ctx, int opc, int ra,
+ int32_t disp16)
{
int l1, l2;
TCGv tmp;
@@ -363,9 +363,8 @@ static always_inline void gen_fbcond (DisasContext *ctx, int opc,
gen_set_label(l2);
}
-static always_inline void gen_cmov (TCGCond inv_cond,
- int ra, int rb, int rc,
- int islit, uint8_t lit, int mask)
+static inline void gen_cmov(TCGCond inv_cond, int ra, int rb, int rc,
+ int islit, uint8_t lit, int mask)
{
int l1;
@@ -397,7 +396,7 @@ static always_inline void gen_cmov (TCGCond inv_cond,
}
#define FARITH2(name) \
-static always_inline void glue(gen_f, name)(int rb, int rc) \
+static inline void glue(gen_f, name)(int rb, int rc) \
{ \
if (unlikely(rc == 31)) \
return; \
@@ -429,7 +428,7 @@ FARITH2(cvtqlv)
FARITH2(cvtqlsv)
#define FARITH3(name) \
-static always_inline void glue(gen_f, name) (int ra, int rb, int rc) \
+static inline void glue(gen_f, name)(int ra, int rb, int rc) \
{ \
if (unlikely(rc == 31)) \
return; \
@@ -480,7 +479,7 @@ FARITH3(cpysn)
FARITH3(cpyse)
#define FCMOV(name) \
-static always_inline void glue(gen_f, name) (int ra, int rb, int rc) \
+static inline void glue(gen_f, name)(int ra, int rb, int rc) \
{ \
int l1; \
TCGv tmp; \
@@ -512,9 +511,8 @@ FCMOV(cmpfle)
FCMOV(cmpfgt)
/* EXTWH, EXTWH, EXTLH, EXTQH */
-static always_inline void gen_ext_h(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
- int ra, int rb, int rc,
- int islit, uint8_t lit)
+static inline void gen_ext_h(void(*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
+ int ra, int rb, int rc, int islit, uint8_t lit)
{
if (unlikely(rc == 31))
return;
@@ -543,9 +541,8 @@ static always_inline void gen_ext_h(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
}
/* EXTBL, EXTWL, EXTWL, EXTLL, EXTQL */
-static always_inline void gen_ext_l(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
- int ra, int rb, int rc,
- int islit, uint8_t lit)
+static inline void gen_ext_l(void(*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
+ int ra, int rb, int rc, int islit, uint8_t lit)
{
if (unlikely(rc == 31))
return;
@@ -568,8 +565,8 @@ static always_inline void gen_ext_l(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
/* Code to call arith3 helpers */
#define ARITH3(name) \
-static always_inline void glue(gen_, name) (int ra, int rb, int rc, \
- int islit, uint8_t lit) \
+static inline void glue(gen_, name)(int ra, int rb, int rc, int islit,\
+ uint8_t lit) \
{ \
if (unlikely(rc == 31)) \
return; \
@@ -617,9 +614,8 @@ ARITH3(umulh)
ARITH3(mullv)
ARITH3(mulqv)
-static always_inline void gen_cmp(TCGCond cond,
- int ra, int rb, int rc,
- int islit, uint8_t lit)
+static inline void gen_cmp(TCGCond cond, int ra, int rb, int rc, int islit,
+ uint8_t lit)
{
int l1, l2;
TCGv tmp;
@@ -647,7 +643,7 @@ static always_inline void gen_cmp(TCGCond cond,
gen_set_label(l2);
}
-static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
+static inline int translate_one(DisasContext *ctx, uint32_t insn)
{
uint32_t palcode;
int32_t disp21, disp16, disp12;
@@ -2336,9 +2332,9 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
return ret;
}
-static always_inline void gen_intermediate_code_internal (CPUState *env,
- TranslationBlock *tb,
- int search_pc)
+static inline void gen_intermediate_code_internal(CPUState *env,
+ TranslationBlock *tb,
+ int search_pc)
{
#if defined ALPHA_DEBUG_DISAS
static int insn_count;
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index dc3580f3f..4f340f3b7 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -57,10 +57,6 @@
#include "cpu-defs.h"
-#define REGX "%016" PRIx64
-#define ADDRX TARGET_FMT_lx
-#define PADDRX TARGET_FMT_plx
-
#include <setjmp.h>
#include "softfloat.h"
@@ -782,7 +778,7 @@ int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
#endif
#endif
-static always_inline uint64_t ppc_dump_gpr (CPUPPCState *env, int gprn)
+static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
{
uint64_t gprv;
diff --git a/target-ppc/exec.h b/target-ppc/exec.h
index 0481eb235..ef1e44bda 100644
--- a/target-ppc/exec.h
+++ b/target-ppc/exec.h
@@ -35,21 +35,21 @@ register struct CPUPPCState *env asm(AREG0);
#include "softmmu_exec.h"
#endif /* !defined(CONFIG_USER_ONLY) */
-static always_inline void env_to_regs (void)
+static inline void env_to_regs(void)
{
}
-static always_inline void regs_to_env (void)
+static inline void regs_to_env(void)
{
}
-static always_inline int cpu_has_work(CPUState *env)
+static inline int cpu_has_work(CPUState *env)
{
return (msr_ee && (env->interrupt_request & CPU_INTERRUPT_HARD));
}
-static always_inline int cpu_halted (CPUState *env)
+static inline int cpu_halted(CPUState *env)
{
if (!env->halted)
return 0;
diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index 8daf9758a..ba2a49534 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -105,23 +105,23 @@ target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
#else
/* Common routines used by software and hardware TLBs emulation */
-static always_inline int pte_is_valid (target_ulong pte0)
+static inline int pte_is_valid(target_ulong pte0)
{
return pte0 & 0x80000000 ? 1 : 0;
}
-static always_inline void pte_invalidate (target_ulong *pte0)
+static inline void pte_invalidate(target_ulong *pte0)
{
*pte0 &= ~0x80000000;
}
#if defined(TARGET_PPC64)
-static always_inline int pte64_is_valid (target_ulong pte0)
+static inline int pte64_is_valid(target_ulong pte0)
{
return pte0 & 0x0000000000000001ULL ? 1 : 0;
}
-static always_inline void pte64_invalidate (target_ulong *pte0)
+static inline void pte64_invalidate(target_ulong *pte0)
{
*pte0 &= ~0x0000000000000001ULL;
}
@@ -134,7 +134,7 @@ static always_inline void pte64_invalidate (target_ulong *pte0)
#define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F)
#endif
-static always_inline int pp_check (int key, int pp, int nx)
+static inline int pp_check(int key, int pp, int nx)
{
int access;
@@ -174,7 +174,7 @@ static always_inline int pp_check (int key, int pp, int nx)
return access;
}
-static always_inline int check_prot (int prot, int rw, int access_type)
+static inline int check_prot(int prot, int rw, int access_type)
{
int ret;
@@ -198,9 +198,8 @@ static always_inline int check_prot (int prot, int rw, int access_type)
return ret;
}
-static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b,
- target_ulong pte0, target_ulong pte1,
- int h, int rw, int type)
+static inline int _pte_check(mmu_ctx_t *ctx, int is_64b, target_ulong pte0,
+ target_ulong pte1, int h, int rw, int type)
{
target_ulong ptem, mmask;
int access, ret, pteh, ptev, pp;
@@ -261,24 +260,22 @@ static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b,
return ret;
}
-static always_inline int pte32_check (mmu_ctx_t *ctx,
- target_ulong pte0, target_ulong pte1,
- int h, int rw, int type)
+static inline int pte32_check(mmu_ctx_t *ctx, target_ulong pte0,
+ target_ulong pte1, int h, int rw, int type)
{
return _pte_check(ctx, 0, pte0, pte1, h, rw, type);
}
#if defined(TARGET_PPC64)
-static always_inline int pte64_check (mmu_ctx_t *ctx,
- target_ulong pte0, target_ulong pte1,
- int h, int rw, int type)
+static inline int pte64_check(mmu_ctx_t *ctx, target_ulong pte0,
+ target_ulong pte1, int h, int rw, int type)
{
return _pte_check(ctx, 1, pte0, pte1, h, rw, type);
}
#endif
-static always_inline int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
- int ret, int rw)
+static inline int pte_update_flags(mmu_ctx_t *ctx, target_ulong *pte1p,
+ int ret, int rw)
{
int store = 0;
@@ -303,8 +300,8 @@ static always_inline int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
}
/* Software driven TLB helpers */
-static always_inline int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,
- int way, int is_code)
+static inline int ppc6xx_tlb_getnum(CPUState *env, target_ulong eaddr, int way,
+ int is_code)
{
int nr;
@@ -319,7 +316,7 @@ static always_inline int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,
return nr;
}
-static always_inline void ppc6xx_tlb_invalidate_all (CPUState *env)
+static inline void ppc6xx_tlb_invalidate_all(CPUState *env)
{
ppc6xx_tlb_t *tlb;
int nr, max;
@@ -336,10 +333,9 @@ static always_inline void ppc6xx_tlb_invalidate_all (CPUState *env)
tlb_flush(env, 1);
}
-static always_inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
- target_ulong eaddr,
- int is_code,
- int match_epn)
+static inline void __ppc6xx_tlb_invalidate_virt(CPUState *env,
+ target_ulong eaddr,
+ int is_code, int match_epn)
{
#if !defined(FLUSH_ALL_TLBS)
ppc6xx_tlb_t *tlb;
@@ -350,8 +346,8 @@ static always_inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
tlb = &env->tlb[nr].tlb6;
if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
- LOG_SWTLB("TLB invalidate %d/%d " ADDRX "\n",
- nr, env->nb_tlb, eaddr);
+ LOG_SWTLB("TLB invalidate %d/%d " TARGET_FMT_lx "\n", nr,
+ env->nb_tlb, eaddr);
pte_invalidate(&tlb->pte0);
tlb_flush_page(env, tlb->EPN);
}
@@ -362,9 +358,8 @@ static always_inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
#endif
}
-static always_inline void ppc6xx_tlb_invalidate_virt (CPUState *env,
- target_ulong eaddr,
- int is_code)
+static inline void ppc6xx_tlb_invalidate_virt(CPUState *env,
+ target_ulong eaddr, int is_code)
{
__ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
}
@@ -377,8 +372,8 @@ void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
tlb = &env->tlb[nr].tlb6;
- LOG_SWTLB("Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX
- " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1);
+ LOG_SWTLB("Set TLB %d/%d EPN " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx
+ " PTE1 " TARGET_FMT_lx "\n", nr, env->nb_tlb, EPN, pte0, pte1);
/* Invalidate any pending reference in Qemu for this virtual address */
__ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
tlb->pte0 = pte0;
@@ -388,9 +383,8 @@ void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
env->last_way = way;
}
-static always_inline int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
- target_ulong eaddr, int rw,
- int access_type)
+static inline int ppc6xx_tlb_check(CPUState *env, mmu_ctx_t *ctx,
+ target_ulong eaddr, int rw, int access_type)
{
ppc6xx_tlb_t *tlb;
int nr, best, way;
@@ -404,19 +398,17 @@ static always_inline int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
tlb = &env->tlb[nr].tlb6;
/* This test "emulates" the PTE index match for hardware TLBs */
if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
- LOG_SWTLB("TLB %d/%d %s [" ADDRX " " ADDRX
- "] <> " ADDRX "\n",
- nr, env->nb_tlb,
- pte_is_valid(tlb->pte0) ? "valid" : "inval",
- tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
+ LOG_SWTLB("TLB %d/%d %s [" TARGET_FMT_lx " " TARGET_FMT_lx
+ "] <> " TARGET_FMT_lx "\n", nr, env->nb_tlb,
+ pte_is_valid(tlb->pte0) ? "valid" : "inval",
+ tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
continue;
}
- LOG_SWTLB("TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX
- " %c %c\n",
- nr, env->nb_tlb,
- pte_is_valid(tlb->pte0) ? "valid" : "inval",
- tlb->EPN, eaddr, tlb->pte1,
- rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
+ LOG_SWTLB("TLB %d/%d %s " TARGET_FMT_lx " <> " TARGET_FMT_lx " "
+ TARGET_FMT_lx " %c %c\n", nr, env->nb_tlb,
+ pte_is_valid(tlb->pte0) ? "valid" : "inval",
+ tlb->EPN, eaddr, tlb->pte1,
+ rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) {
case -3:
/* TLB inconsistency */
@@ -443,8 +435,8 @@ static always_inline int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
}
if (best != -1) {
done:
- LOG_SWTLB("found TLB at addr " PADDRX " prot=%01x ret=%d\n",
- ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
+ LOG_SWTLB("found TLB at addr " TARGET_FMT_plx " prot=%01x ret=%d\n",
+ ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
/* Update page flags */
pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);
}
@@ -453,9 +445,9 @@ static always_inline int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
}
/* Perform BAT hit & translation */
-static always_inline void bat_size_prot (CPUState *env, target_ulong *blp,
- int *validp, int *protp,
- target_ulong *BATu, target_ulong *BATl)
+static inline void bat_size_prot(CPUState *env, target_ulong *blp, int *validp,
+ int *protp, target_ulong *BATu,
+ target_ulong *BATl)
{
target_ulong bl;
int pp, valid, prot;
@@ -478,17 +470,16 @@ static always_inline void bat_size_prot (CPUState *env, target_ulong *blp,
*protp = prot;
}
-static always_inline void bat_601_size_prot (CPUState *env,target_ulong *blp,
- int *validp, int *protp,
- target_ulong *BATu,
- target_ulong *BATl)
+static inline void bat_601_size_prot(CPUState *env, target_ulong *blp,
+ int *validp, int *protp,
+ target_ulong *BATu, target_ulong *BATl)
{
target_ulong bl;
int key, pp, valid, prot;
bl = (*BATl & 0x0000003F) << 17;
- LOG_BATS("b %02x ==> bl " ADDRX " msk " ADDRX "\n",
- (uint8_t)(*BATl & 0x0000003F), bl, ~bl);
+ LOG_BATS("b %02x ==> bl " TARGET_FMT_lx " msk " TARGET_FMT_lx "\n",
+ (uint8_t)(*BATl & 0x0000003F), bl, ~bl);
prot = 0;
valid = (*BATl >> 6) & 1;
if (valid) {
@@ -504,16 +495,16 @@ static always_inline void bat_601_size_prot (CPUState *env,target_ulong *blp,
*protp = prot;
}
-static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx,
- target_ulong virtual, int rw, int type)
+static inline int get_bat(CPUState *env, mmu_ctx_t *ctx, target_ulong virtual,
+ int rw, int type)
{
target_ulong *BATlt, *BATut, *BATu, *BATl;
target_ulong base, BEPIl, BEPIu, bl;
int i, valid, prot;
int ret = -1;
- LOG_BATS("%s: %cBAT v " ADDRX "\n", __func__,
- type == ACCESS_CODE ? 'I' : 'D', virtual);
+ LOG_BATS("%s: %cBAT v " TARGET_FMT_lx "\n", __func__,
+ type == ACCESS_CODE ? 'I' : 'D', virtual);
switch (type) {
case ACCESS_CODE:
BATlt = env->IBAT[1];
@@ -535,9 +526,9 @@ static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx,
} else {
bat_size_prot(env, &bl, &valid, &prot, BATu, BATl);
}
- LOG_BATS("%s: %cBAT%d v " ADDRX " BATu " ADDRX
- " BATl " ADDRX "\n", __func__,
- type == ACCESS_CODE ? 'I' : 'D', i, virtual, *BATu, *BATl);
+ LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
+ " BATl " TARGET_FMT_lx "\n", __func__,
+ type == ACCESS_CODE ? 'I' : 'D', i, virtual, *BATu, *BATl);
if ((virtual & 0xF0000000) == BEPIu &&
((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
/* BAT matches */
@@ -550,7 +541,7 @@ static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx,
ctx->prot = prot;
ret = check_prot(ctx->prot, rw, type);
if (ret == 0)
- LOG_BATS("BAT %d match: r " PADDRX " prot=%c%c\n",
+ LOG_BATS("BAT %d match: r " TARGET_FMT_plx " prot=%c%c\n",
i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
ctx->prot & PAGE_WRITE ? 'W' : '-');
break;
@@ -560,15 +551,16 @@ static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx,
if (ret < 0) {
#if defined(DEBUG_BATS)
if (qemu_log_enabled()) {
- LOG_BATS("no BAT match for " ADDRX ":\n", virtual);
+ LOG_BATS("no BAT match for " TARGET_FMT_lx ":\n", virtual);
for (i = 0; i < 4; i++) {
BATu = &BATut[i];
BATl = &BATlt[i];
BEPIu = *BATu & 0xF0000000;
BEPIl = *BATu & 0x0FFE0000;
bl = (*BATu & 0x00001FFC) << 15;
- LOG_BATS("%s: %cBAT%d v " ADDRX " BATu " ADDRX
- " BATl " ADDRX " \n\t" ADDRX " " ADDRX " " ADDRX "\n",
+ LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
+ " BATl " TARGET_FMT_lx " \n\t" TARGET_FMT_lx " "
+ TARGET_FMT_lx " " TARGET_FMT_lx "\n",
__func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
*BATu, *BATl, BEPIu, BEPIl, bl);
}
@@ -580,9 +572,8 @@ static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx,
}
/* PTE table lookup */
-static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h,
- int rw, int type,
- int target_page_bits)
+static inline int _find_pte(mmu_ctx_t *ctx, int is_64b, int h, int rw,
+ int type, int target_page_bits)
{
target_ulong base, pte0, pte1;
int i, good = -1;
@@ -603,22 +594,20 @@ static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h,
& TARGET_PAGE_MASK;
r = pte64_check(ctx, pte0, pte1, h, rw, type);
- LOG_MMU("Load pte from " ADDRX " => " ADDRX " " ADDRX
- " %d %d %d " ADDRX "\n",
- base + (i * 16), pte0, pte1,
- (int)(pte0 & 1), h, (int)((pte0 >> 1) & 1),
- ctx->ptem);
+ LOG_MMU("Load pte from " TARGET_FMT_lx " => " TARGET_FMT_lx " "
+ TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n",
+ base + (i * 16), pte0, pte1, (int)(pte0 & 1), h,
+ (int)((pte0 >> 1) & 1), ctx->ptem);
} else
#endif
{
pte0 = ldl_phys(base + (i * 8));
pte1 = ldl_phys(base + (i * 8) + 4);
r = pte32_check(ctx, pte0, pte1, h, rw, type);
- LOG_MMU("Load pte from " ADDRX " => " ADDRX " " ADDRX
- " %d %d %d " ADDRX "\n",
- base + (i * 8), pte0, pte1,
- (int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1),
- ctx->ptem);
+ LOG_MMU("Load pte from " TARGET_FMT_lx " => " TARGET_FMT_lx " "
+ TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n",
+ base + (i * 8), pte0, pte1, (int)(pte0 >> 31), h,
+ (int)((pte0 >> 6) & 1), ctx->ptem);
}
switch (r) {
case -3:
@@ -646,8 +635,8 @@ static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h,
}
if (good != -1) {
done:
- LOG_MMU("found PTE at addr " PADDRX " prot=%01x ret=%d\n",
- ctx->raddr, ctx->prot, ret);
+ LOG_MMU("found PTE at addr " TARGET_FMT_lx " prot=%01x ret=%d\n",
+ ctx->raddr, ctx->prot, ret);
/* Update page flags */
pte1 = ctx->raddr;
if (pte_update_flags(ctx, &pte1, ret, rw) == 1) {
@@ -665,23 +654,22 @@ static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h,
return ret;
}
-static always_inline int find_pte32 (mmu_ctx_t *ctx, int h, int rw,
- int type, int target_page_bits)
+static inline int find_pte32(mmu_ctx_t *ctx, int h, int rw, int type,
+ int target_page_bits)
{
return _find_pte(ctx, 0, h, rw, type, target_page_bits);
}
#if defined(TARGET_PPC64)
-static always_inline int find_pte64 (mmu_ctx_t *ctx, int h, int rw,
- int type, int target_page_bits)
+static inline int find_pte64(mmu_ctx_t *ctx, int h, int rw, int type,
+ int target_page_bits)
{
return _find_pte(ctx, 1, h, rw, type, target_page_bits);
}
#endif
-static always_inline int find_pte (CPUState *env, mmu_ctx_t *ctx,
- int h, int rw, int type,
- int target_page_bits)
+static inline int find_pte(CPUState *env, mmu_ctx_t *ctx, int h, int rw,
+ int type, int target_page_bits)
{
#if defined(TARGET_PPC64)
if (env->mmu_model & POWERPC_MMU_64)
@@ -722,26 +710,25 @@ static void slb_set_entry(CPUPPCState *env, int nr, ppc_slb_t *slb)
entry->tmp = slb->tmp;
}
-static always_inline int slb_is_valid (ppc_slb_t *slb)
+static inline int slb_is_valid(ppc_slb_t *slb)
{
return (int)(slb->tmp64 & 0x0000000008000000ULL);
}
-static always_inline void slb_invalidate (ppc_slb_t *slb)
+static inline void slb_invalidate(ppc_slb_t *slb)
{
slb->tmp64 &= ~0x0000000008000000ULL;
}
-static always_inline int slb_lookup (CPUPPCState *env, target_ulong eaddr,
- target_ulong *vsid,
- target_ulong *page_mask, int *attr,
- int *target_page_bits)
+static inline int slb_lookup(CPUPPCState *env, target_ulong eaddr,
+ target_ulong *vsid, target_ulong *page_mask,
+ int *attr, int *target_page_bits)
{
target_ulong mask;
int n, ret;
ret = -5;
- LOG_SLB("%s: eaddr " ADDRX "\n", __func__, eaddr);
+ LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);
mask = 0x0000000000000000ULL; /* Avoid gcc warning */
for (n = 0; n < env->slb_nr; n++) {
ppc_slb_t *slb = slb_get_entry(env, n);
@@ -836,7 +823,7 @@ target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr)
rt = 0;
}
LOG_SLB("%s: %016" PRIx64 " %08" PRIx32 " => %d "
- ADDRX "\n", __func__, slb->tmp64, slb->tmp, slb_nr, rt);
+ TARGET_FMT_lx "\n", __func__, slb->tmp64, slb->tmp, slb_nr, rt);
return rt;
}
@@ -860,25 +847,25 @@ void ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs)
slb->tmp64 = (esid << 28) | valid | (vsid >> 24);
slb->tmp = (vsid << 8) | (flags << 3);
- LOG_SLB("%s: %d " ADDRX " - " ADDRX " => %016" PRIx64
- " %08" PRIx32 "\n", __func__,
- slb_nr, rb, rs, slb->tmp64, slb->tmp);
+ LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64
+ " %08" PRIx32 "\n", __func__, slb_nr, rb, rs, slb->tmp64,
+ slb->tmp);
slb_set_entry(env, slb_nr, slb);
}
#endif /* defined(TARGET_PPC64) */
/* Perform segment based translation */
-static always_inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
- int sdr_sh,
- target_phys_addr_t hash,
- target_phys_addr_t mask)
+static inline target_phys_addr_t get_pgaddr(target_phys_addr_t sdr1,
+ int sdr_sh,
+ target_phys_addr_t hash,
+ target_phys_addr_t mask)
{
return (sdr1 & ((target_phys_addr_t)(-1ULL) << sdr_sh)) | (hash & mask);
}
-static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx,
- target_ulong eaddr, int rw, int type)
+static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
+ target_ulong eaddr, int rw, int type)
{
target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask;
target_ulong sr, vsid, vsid_mask, pgidx, page_mask;
@@ -920,14 +907,14 @@ static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx,
sdr_sh = 16;
sdr_mask = 0xFFC0;
target_page_bits = TARGET_PAGE_BITS;
- LOG_MMU("Check segment v=" ADDRX " %d " ADDRX
- " nip=" ADDRX " lr=" ADDRX " ir=%d dr=%d pr=%d %d t=%d\n",
- eaddr, (int)(eaddr >> 28), sr, env->nip,
- env->lr, (int)msr_ir, (int)msr_dr, pr != 0 ? 1 : 0,
- rw, type);
+ LOG_MMU("Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx " nip="
+ TARGET_FMT_lx " lr=" TARGET_FMT_lx
+ " ir=%d dr=%d pr=%d %d t=%d\n",
+ eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir,
+ (int)msr_dr, pr != 0 ? 1 : 0, rw, type);
}
- LOG_MMU("pte segment: key=%d ds %d nx %d vsid " ADDRX "\n",
- ctx->key, ds, ctx->nx, vsid);
+ LOG_MMU("pte segment: key=%d ds %d nx %d vsid " TARGET_FMT_lx "\n",
+ ctx->key, ds, ctx->nx, vsid);
ret = -1;
if (!ds) {
/* Check if instruction fetch is allowed, if needed */
@@ -948,15 +935,14 @@ static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx,
hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
}
mask = (htab_mask << sdr_sh) | sdr_mask;
- LOG_MMU("sdr " PADDRX " sh %d hash " PADDRX
- " mask " PADDRX " " ADDRX "\n",
- sdr, sdr_sh, hash, mask, page_mask);
+ LOG_MMU("sdr " TARGET_FMT_plx " sh %d hash " TARGET_FMT_plx
+ " mask " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
+ sdr, sdr_sh, hash, mask, page_mask);
ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
/* Secondary table address */
hash = (~hash) & vsid_mask;
- LOG_MMU("sdr " PADDRX " sh %d hash " PADDRX
- " mask " PADDRX "\n",
- sdr, sdr_sh, hash, mask);
+ LOG_MMU("sdr " TARGET_FMT_plx " sh %d hash " TARGET_FMT_plx
+ " mask " TARGET_FMT_plx "\n", sdr, sdr_sh, hash, mask);
ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
#if defined(TARGET_PPC64)
if (env->mmu_model & POWERPC_MMU_64) {
@@ -979,19 +965,19 @@ static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx,
/* Software TLB search */
ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
} else {
- LOG_MMU("0 sdr1=" PADDRX " vsid=" ADDRX " "
- "api=" ADDRX " hash=" PADDRX
- " pg_addr=" PADDRX "\n",
- sdr, vsid, pgidx, hash, ctx->pg_addr[0]);
+ LOG_MMU("0 sdr1=" TARGET_FMT_plx " vsid=" TARGET_FMT_lx " "
+ "api=" TARGET_FMT_lx " hash=" TARGET_FMT_plx
+ " pg_addr=" TARGET_FMT_plx "\n",
+ sdr, vsid, pgidx, hash, ctx->pg_addr[0]);
/* Primary table lookup */
ret = find_pte(env, ctx, 0, rw, type, target_page_bits);
if (ret < 0) {
/* Secondary table lookup */
if (eaddr != 0xEFFFFFFF)
- LOG_MMU("1 sdr1=" PADDRX " vsid=" ADDRX " "
- "api=" ADDRX " hash=" PADDRX
- " pg_addr=" PADDRX "\n",
- sdr, vsid, pgidx, hash, ctx->pg_addr[1]);
+ LOG_MMU("1 sdr1=" TARGET_FMT_plx " vsid=" TARGET_FMT_lx " "
+ "api=" TARGET_FMT_lx " hash=" TARGET_FMT_plx
+ " pg_addr=" TARGET_FMT_plx "\n", sdr, vsid,
+ pgidx, hash, ctx->pg_addr[1]);
ret2 = find_pte(env, ctx, 1, rw, type,
target_page_bits);
if (ret2 != -1)
@@ -1002,8 +988,8 @@ static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx,
if (qemu_log_enabled()) {
target_phys_addr_t curaddr;
uint32_t a0, a1, a2, a3;
- qemu_log("Page table: " PADDRX " len " PADDRX "\n",
- sdr, mask + 0x80);
+ qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx
+ "\n", sdr, mask + 0x80);
for (curaddr = sdr; curaddr < (sdr + mask + 0x80);
curaddr += 16) {
a0 = ldl_phys(curaddr);
@@ -1011,8 +997,8 @@ static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx,
a2 = ldl_phys(curaddr + 8);
a3 = ldl_phys(curaddr + 12);
if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) {
- qemu_log(PADDRX ": %08x %08x %08x %08x\n",
- curaddr, a0, a1, a2, a3);
+ qemu_log(TARGET_FMT_plx ": %08x %08x %08x %08x\n",
+ curaddr, a0, a1, a2, a3);
}
}
}
@@ -1064,10 +1050,10 @@ static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx,
}
/* Generic TLB check function for embedded PowerPC implementations */
-static always_inline int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb,
- target_phys_addr_t *raddrp,
- target_ulong address,
- uint32_t pid, int ext, int i)
+static inline int ppcemb_tlb_check(CPUState *env, ppcemb_tlb_t *tlb,
+ target_phys_addr_t *raddrp,
+ target_ulong address, uint32_t pid, int ext,
+ int i)
{
target_ulong mask;
@@ -1077,9 +1063,9 @@ static always_inline int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb,
return -1;
}
mask = ~(tlb->size - 1);
- LOG_SWTLB("%s: TLB %d address " ADDRX " PID %u <=> " ADDRX
- " " ADDRX " %u\n",
- __func__, i, address, pid, tlb->EPN, mask, (uint32_t)tlb->PID);
+ LOG_SWTLB("%s: TLB %d address " TARGET_FMT_lx " PID %u <=> " TARGET_FMT_lx
+ " " TARGET_FMT_lx " %u\n", __func__, i, address, pid, tlb->EPN,
+ mask, (uint32_t)tlb->PID);
/* Check PID */
if (tlb->PID != 0 && tlb->PID != pid)
return -1;
@@ -1118,7 +1104,7 @@ int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
}
/* Helpers specific to PowerPC 40x implementations */
-static always_inline void ppc4xx_tlb_invalidate_all (CPUState *env)
+static inline void ppc4xx_tlb_invalidate_all(CPUState *env)
{
ppcemb_tlb_t *tlb;
int i;
@@ -1130,9 +1116,8 @@ static always_inline void ppc4xx_tlb_invalidate_all (CPUState *env)
tlb_flush(env, 1);
}
-static always_inline void ppc4xx_tlb_invalidate_virt (CPUState *env,
- target_ulong eaddr,
- uint32_t pid)
+static inline void ppc4xx_tlb_invalidate_virt(CPUState *env,
+ target_ulong eaddr, uint32_t pid)
{
#if !defined(FLUSH_ALL_TLBS)
ppcemb_tlb_t *tlb;
@@ -1203,15 +1188,14 @@ static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
}
if (ret >= 0) {
ctx->raddr = raddr;
- LOG_SWTLB("%s: access granted " ADDRX " => " PADDRX
- " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
- ret);
+ LOG_SWTLB("%s: access granted " TARGET_FMT_lx " => " TARGET_FMT_plx
+ " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
+ ret);
return 0;
}
}
- LOG_SWTLB("%s: access refused " ADDRX " => " PADDRX
- " %d %d\n", __func__, address, raddr, ctx->prot,
- ret);
+ LOG_SWTLB("%s: access refused " TARGET_FMT_lx " => " TARGET_FMT_plx
+ " %d %d\n", __func__, address, raddr, ctx->prot, ret);
return ret;
}
@@ -1271,8 +1255,8 @@ static int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
return ret;
}
-static always_inline int check_physical (CPUState *env, mmu_ctx_t *ctx,
- target_ulong eaddr, int rw)
+static inline int check_physical(CPUState *env, mmu_ctx_t *ctx,
+ target_ulong eaddr, int rw)
{
int in_plb, ret;
@@ -1394,8 +1378,8 @@ int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
}
}
#if 0
- qemu_log("%s address " ADDRX " => %d " PADDRX "\n",
- __func__, eaddr, ret, ctx->raddr);
+ qemu_log("%s address " TARGET_FMT_lx " => %d " TARGET_FMT_plx "\n",
+ __func__, eaddr, ret, ctx->raddr);
#endif
return ret;
@@ -1675,27 +1659,26 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
/*****************************************************************************/
/* BATs management */
#if !defined(FLUSH_ALL_TLBS)
-static always_inline void do_invalidate_BAT (CPUPPCState *env,
- target_ulong BATu,
- target_ulong mask)
+static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu,
+ target_ulong mask)
{
target_ulong base, end, page;
base = BATu & ~0x0001FFFF;
end = base + mask + 0x00020000;
- LOG_BATS("Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n",
- base, end, mask);
+ LOG_BATS("Flush BAT from " TARGET_FMT_lx " to " TARGET_FMT_lx " ("
+ TARGET_FMT_lx ")\n", base, end, mask);
for (page = base; page != end; page += TARGET_PAGE_SIZE)
tlb_flush_page(env, page);
LOG_BATS("Flush done\n");
}
#endif
-static always_inline void dump_store_bat (CPUPPCState *env, char ID,
- int ul, int nr, target_ulong value)
+static inline void dump_store_bat(CPUPPCState *env, char ID, int ul, int nr,
+ target_ulong value)
{
- LOG_BATS("Set %cBAT%d%c to " ADDRX " (" ADDRX ")\n",
- ID, nr, ul == 0 ? 'u' : 'l', value, env->nip);
+ LOG_BATS("Set %cBAT%d%c to " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", ID,
+ nr, ul == 0 ? 'u' : 'l', value, env->nip);
}
void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
@@ -1965,7 +1948,7 @@ void ppc_store_asr (CPUPPCState *env, target_ulong value)
void ppc_store_sdr1 (CPUPPCState *env, target_ulong value)
{
- LOG_MMU("%s: " ADDRX "\n", __func__, value);
+ LOG_MMU("%s: " TARGET_FMT_lx "\n", __func__, value);
if (env->sdr1 != value) {
/* XXX: for PowerPC 64, should check that the HTABSIZE value
* is <= 28
@@ -1985,8 +1968,8 @@ target_ulong ppc_load_sr (CPUPPCState *env, int slb_nr)
void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value)
{
- LOG_MMU("%s: reg=%d " ADDRX " " ADDRX "\n",
- __func__, srnum, value, env->sr[srnum]);
+ LOG_MMU("%s: reg=%d " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__,
+ srnum, value, env->sr[srnum]);
#if defined(TARGET_PPC64)
if (env->mmu_model & POWERPC_MMU_64) {
uint64_t rb = 0, rs = 0;
@@ -2047,19 +2030,20 @@ void ppc_hw_interrupt (CPUState *env)
env->error_code = 0;
}
#else /* defined (CONFIG_USER_ONLY) */
-static always_inline void dump_syscall (CPUState *env)
+static inline void dump_syscall(CPUState *env)
{
- qemu_log_mask(CPU_LOG_INT, "syscall r0=" REGX " r3=" REGX " r4=" REGX
- " r5=" REGX " r6=" REGX " nip=" ADDRX "\n",
- ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3), ppc_dump_gpr(env, 4),
- ppc_dump_gpr(env, 5), ppc_dump_gpr(env, 6), env->nip);
+ qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64 " r3=%016" PRIx64
+ " r4=%016" PRIx64 " r5=%016" PRIx64 " r6=%016" PRIx64
+ " nip=" TARGET_FMT_lx "\n",
+ ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3),
+ ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5),
+ ppc_dump_gpr(env, 6), env->nip);
}
/* Note that this function should be greatly optimized
* when called with a constant excp, from ppc_hw_interrupt
*/
-static always_inline void powerpc_excp (CPUState *env,
- int excp_model, int excp)
+static inline void powerpc_excp(CPUState *env, int excp_model, int excp)
{
target_ulong msr, new_msr, vector;
int srr0, srr1, asrr0, asrr1;
@@ -2075,8 +2059,8 @@ static always_inline void powerpc_excp (CPUState *env,
lpes1 = 1;
}
- qemu_log_mask(CPU_LOG_INT, "Raise exception at " ADDRX " => %08x (%02x)\n",
- env->nip, excp, env->error_code);
+ qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
+ " => %08x (%02x)\n", env->nip, excp, env->error_code);
msr = env->msr;
new_msr = msr;
srr0 = SPR_SRR0;
@@ -2143,15 +2127,15 @@ static always_inline void powerpc_excp (CPUState *env,
}
goto store_next;
case POWERPC_EXCP_DSI: /* Data storage exception */
- LOG_EXCP("DSI exception: DSISR=" ADDRX" DAR=" ADDRX "\n",
- env->spr[SPR_DSISR], env->spr[SPR_DAR]);
+ LOG_EXCP("DSI exception: DSISR=" TARGET_FMT_lx" DAR=" TARGET_FMT_lx
+ "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
new_msr &= ~((target_ulong)1 << MSR_RI);
if (lpes1 == 0)
new_msr |= (target_ulong)MSR_HVB;
goto store_next;
case POWERPC_EXCP_ISI: /* Instruction storage exception */
- LOG_EXCP("ISI exception: msr=" ADDRX ", nip=" ADDRX "\n",
- msr, env->nip);
+ LOG_EXCP("ISI exception: msr=" TARGET_FMT_lx ", nip=" TARGET_FMT_lx
+ "\n", msr, env->nip);
new_msr &= ~((target_ulong)1 << MSR_RI);
if (lpes1 == 0)
new_msr |= (target_ulong)MSR_HVB;
@@ -2188,8 +2172,7 @@ static always_inline void powerpc_excp (CPUState *env,
msr |= 0x00010000;
break;
case POWERPC_EXCP_INVAL:
- LOG_EXCP("Invalid instruction at " ADDRX "\n",
- env->nip);
+ LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n", env->nip);
new_msr &= ~((target_ulong)1 << MSR_RI);
if (lpes1 == 0)
new_msr |= (target_ulong)MSR_HVB;
@@ -2463,11 +2446,11 @@ static always_inline void powerpc_excp (CPUState *env,
miss = &env->spr[SPR_DMISS];
cmp = &env->spr[SPR_DCMP];
}
- qemu_log("6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
- " H1 " ADDRX " H2 " ADDRX " %08x\n",
- es, en, *miss, en, *cmp,
- env->spr[SPR_HASH1], env->spr[SPR_HASH2],
- env->error_code);
+ qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
+ TARGET_FMT_lx " H1 " TARGET_FMT_lx " H2 "
+ TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
+ env->spr[SPR_HASH1], env->spr[SPR_HASH2],
+ env->error_code);
}
#endif
msr |= env->crf[0] << 28;
@@ -2496,9 +2479,9 @@ static always_inline void powerpc_excp (CPUState *env,
miss = &env->spr[SPR_TLBMISS];
cmp = &env->spr[SPR_PTEHI];
}
- qemu_log("74xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
- " %08x\n",
- es, en, *miss, en, *cmp, env->error_code);
+ qemu_log("74xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
+ TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
+ env->error_code);
}
#endif
msr |= env->error_code; /* key bit */
@@ -2762,8 +2745,8 @@ void ppc_hw_interrupt (CPUPPCState *env)
void cpu_dump_rfi (target_ulong RA, target_ulong msr)
{
- qemu_log("Return from exception at " ADDRX " with flags " ADDRX "\n",
- RA, msr);
+ qemu_log("Return from exception at " TARGET_FMT_lx " with flags "
+ TARGET_FMT_lx "\n", RA, msr);
}
void cpu_ppc_reset (void *opaque)
diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h
index 2a1f541d1..3c988502e 100644
--- a/target-ppc/helper_regs.h
+++ b/target-ppc/helper_regs.h
@@ -21,7 +21,7 @@
#define __HELPER_REGS_H__
/* Swap temporary saved registers with GPRs */
-static always_inline void hreg_swap_gpr_tgpr (CPUPPCState *env)
+static inline void hreg_swap_gpr_tgpr(CPUPPCState *env)
{
target_ulong tmp;
@@ -39,7 +39,7 @@ static always_inline void hreg_swap_gpr_tgpr (CPUPPCState *env)
env->tgpr[3] = tmp;
}
-static always_inline void hreg_compute_mem_idx (CPUPPCState *env)
+static inline void hreg_compute_mem_idx(CPUPPCState *env)
{
/* Precompute MMU index */
if (msr_pr == 0 && msr_hv != 0) {
@@ -49,7 +49,7 @@ static always_inline void hreg_compute_mem_idx (CPUPPCState *env)
}
}
-static always_inline void hreg_compute_hflags (CPUPPCState *env)
+static inline void hreg_compute_hflags(CPUPPCState *env)
{
target_ulong hflags_mask;
@@ -64,8 +64,8 @@ static always_inline void hreg_compute_hflags (CPUPPCState *env)
env->hflags |= env->hflags_nmsr;
}
-static always_inline int hreg_store_msr (CPUPPCState *env, target_ulong value,
- int alter_hv)
+static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,
+ int alter_hv)
{
int excp;
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 812282c74..e3bd29cc1 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -56,14 +56,14 @@ void helper_raise_exception (uint32_t exception)
/* SPR accesses */
void helper_load_dump_spr (uint32_t sprn)
{
- qemu_log("Read SPR %d %03x => " ADDRX "\n",
- sprn, sprn, env->spr[sprn]);
+ qemu_log("Read SPR %d %03x => " TARGET_FMT_lx "\n", sprn, sprn,
+ env->spr[sprn]);
}
void helper_store_dump_spr (uint32_t sprn)
{
- qemu_log("Write SPR %d %03x <= " ADDRX "\n",
- sprn, sprn, env->spr[sprn]);
+ qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn,
+ env->spr[sprn]);
}
target_ulong helper_load_tbl (void)
@@ -160,8 +160,8 @@ void helper_store_hid0_601 (target_ulong val)
env->hflags_nmsr &= ~(1 << MSR_LE);
env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
env->hflags |= env->hflags_nmsr;
- qemu_log("%s: set endianness to %c => " ADDRX "\n",
- __func__, val & 0x8 ? 'l' : 'b', env->hflags);
+ qemu_log("%s: set endianness to %c => " TARGET_FMT_lx "\n", __func__,
+ val & 0x8 ? 'l' : 'b', env->hflags);
}
env->spr[SPR_HID0] = (uint32_t)val;
}
@@ -239,7 +239,7 @@ void helper_store_601_batu (uint32_t nr, target_ulong val)
/*****************************************************************************/
/* Memory load and stores */
-static always_inline target_ulong addr_add(target_ulong addr, target_long arg)
+static inline target_ulong addr_add(target_ulong addr, target_long arg)
{
#if defined(TARGET_PPC64)
if (!msr_sf)
@@ -532,7 +532,7 @@ uint32_t helper_float64_to_float32(uint64_t arg)
return f.l;
}
-static always_inline int isden (float64 d)
+static inline int isden(float64 d)
{
CPU_DoubleU u;
@@ -594,7 +594,7 @@ uint32_t helper_compute_fprf (uint64_t arg, uint32_t set_fprf)
}
/* Floating-point invalid operations exception */
-static always_inline uint64_t fload_invalid_op_excp (int op)
+static inline uint64_t fload_invalid_op_excp(int op)
{
uint64_t ret = 0;
int ve;
@@ -675,7 +675,7 @@ static always_inline uint64_t fload_invalid_op_excp (int op)
return ret;
}
-static always_inline void float_zero_divide_excp (void)
+static inline void float_zero_divide_excp(void)
{
env->fpscr |= 1 << FPSCR_ZX;
env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
@@ -691,7 +691,7 @@ static always_inline void float_zero_divide_excp (void)
}
}
-static always_inline void float_overflow_excp (void)
+static inline void float_overflow_excp(void)
{
env->fpscr |= 1 << FPSCR_OX;
/* Update the floating-point exception summary */
@@ -709,7 +709,7 @@ static always_inline void float_overflow_excp (void)
}
}
-static always_inline void float_underflow_excp (void)
+static inline void float_underflow_excp(void)
{
env->fpscr |= 1 << FPSCR_UX;
/* Update the floating-point exception summary */
@@ -724,7 +724,7 @@ static always_inline void float_underflow_excp (void)
}
}
-static always_inline void float_inexact_excp (void)
+static inline void float_inexact_excp(void)
{
env->fpscr |= 1 << FPSCR_XX;
/* Update the floating-point exception summary */
@@ -738,7 +738,7 @@ static always_inline void float_inexact_excp (void)
}
}
-static always_inline void fpscr_set_rounding_mode (void)
+static inline void fpscr_set_rounding_mode(void)
{
int rnd_type;
@@ -1199,7 +1199,7 @@ uint64_t helper_fctidz (uint64_t arg)
#endif
-static always_inline uint64_t do_fri (uint64_t arg, int rounding_mode)
+static inline uint64_t do_fri(uint64_t arg, int rounding_mode)
{
CPU_DoubleU farg;
farg.ll = arg;
@@ -1614,8 +1614,8 @@ void helper_store_msr (target_ulong val)
}
}
-static always_inline void do_rfi (target_ulong nip, target_ulong msr,
- target_ulong msrm, int keep_msrh)
+static inline void do_rfi(target_ulong nip, target_ulong msr,
+ target_ulong msrm, int keep_msrh)
{
#if defined(TARGET_PPC64)
if (msr & (1ULL << MSR_SF)) {
@@ -1956,7 +1956,7 @@ target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_
/* Saturating arithmetic helpers. */
#define SATCVT(from, to, from_type, to_type, min, max, use_min, use_max) \
- static always_inline to_type cvt##from##to (from_type x, int *sat) \
+ static inline to_type cvt##from##to(from_type x, int *sat) \
{ \
to_type r; \
if (use_min && x < min) { \
@@ -1975,7 +1975,7 @@ SATCVT(sw, sh, int32_t, int16_t, INT16_MIN, INT16_MAX, 1, 1)
SATCVT(sd, sw, int64_t, int32_t, INT32_MIN, INT32_MAX, 1, 1)
/* Work around gcc problems with the macro version */
-static always_inline uint8_t cvtuhub(uint16_t x, int *sat)
+static inline uint8_t cvtuhub(uint16_t x, int *sat)
{
uint8_t r;
@@ -2243,8 +2243,8 @@ VCMPFP(gtfp, ==, float_relation_greater)
#undef VCMPFP_DO
#undef VCMPFP
-static always_inline void vcmpbfp_internal (ppc_avr_t *r, ppc_avr_t *a,
- ppc_avr_t *b, int record)
+static inline void vcmpbfp_internal(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b,
+ int record)
{
int i;
int all_in = 0;
@@ -3063,12 +3063,12 @@ static uint8_t hbrev[16] = {
0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
};
-static always_inline uint8_t byte_reverse (uint8_t val)
+static inline uint8_t byte_reverse(uint8_t val)
{
return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
}
-static always_inline uint32_t word_reverse (uint32_t val)
+static inline uint32_t word_reverse(uint32_t val)
{
return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
(byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
@@ -3100,7 +3100,7 @@ uint32_t helper_cntlzw32 (uint32_t val)
}
/* Single-precision floating-point conversions */
-static always_inline uint32_t efscfsi (uint32_t val)
+static inline uint32_t efscfsi(uint32_t val)
{
CPU_FloatU u;
@@ -3109,7 +3109,7 @@ static always_inline uint32_t efscfsi (uint32_t val)
return u.l;
}
-static always_inline uint32_t efscfui (uint32_t val)
+static inline uint32_t efscfui(uint32_t val)
{
CPU_FloatU u;
@@ -3118,7 +3118,7 @@ static always_inline uint32_t efscfui (uint32_t val)
return u.l;
}
-static always_inline int32_t efsctsi (uint32_t val)
+static inline int32_t efsctsi(uint32_t val)
{
CPU_FloatU u;
@@ -3130,7 +3130,7 @@ static always_inline int32_t efsctsi (uint32_t val)
return float32_to_int32(u.f, &env->vec_status);
}
-static always_inline uint32_t efsctui (uint32_t val)
+static inline uint32_t efsctui(uint32_t val)
{
CPU_FloatU u;
@@ -3142,7 +3142,7 @@ static always_inline uint32_t efsctui (uint32_t val)
return float32_to_uint32(u.f, &env->vec_status);
}
-static always_inline uint32_t efsctsiz (uint32_t val)
+static inline uint32_t efsctsiz(uint32_t val)
{
CPU_FloatU u;
@@ -3154,7 +3154,7 @@ static always_inline uint32_t efsctsiz (uint32_t val)
return float32_to_int32_round_to_zero(u.f, &env->vec_status);
}
-static always_inline uint32_t efsctuiz (uint32_t val)
+static inline uint32_t efsctuiz(uint32_t val)
{
CPU_FloatU u;
@@ -3166,7 +3166,7 @@ static always_inline uint32_t efsctuiz (uint32_t val)
return float32_to_uint32_round_to_zero(u.f, &env->vec_status);
}
-static always_inline uint32_t efscfsf (uint32_t val)
+static inline uint32_t efscfsf(uint32_t val)
{
CPU_FloatU u;
float32 tmp;
@@ -3178,7 +3178,7 @@ static always_inline uint32_t efscfsf (uint32_t val)
return u.l;
}
-static always_inline uint32_t efscfuf (uint32_t val)
+static inline uint32_t efscfuf(uint32_t val)
{
CPU_FloatU u;
float32 tmp;
@@ -3190,7 +3190,7 @@ static always_inline uint32_t efscfuf (uint32_t val)
return u.l;
}
-static always_inline uint32_t efsctsf (uint32_t val)
+static inline uint32_t efsctsf(uint32_t val)
{
CPU_FloatU u;
float32 tmp;
@@ -3205,7 +3205,7 @@ static always_inline uint32_t efsctsf (uint32_t val)
return float32_to_int32(u.f, &env->vec_status);
}
-static always_inline uint32_t efsctuf (uint32_t val)
+static inline uint32_t efsctuf(uint32_t val)
{
CPU_FloatU u;
float32 tmp;
@@ -3274,7 +3274,7 @@ HELPER_SPE_VECTOR_CONV(fsctsf);
HELPER_SPE_VECTOR_CONV(fsctuf);
/* Single-precision floating-point arithmetic */
-static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2)
+static inline uint32_t efsadd(uint32_t op1, uint32_t op2)
{
CPU_FloatU u1, u2;
u1.l = op1;
@@ -3283,7 +3283,7 @@ static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2)
return u1.l;
}
-static always_inline uint32_t efssub (uint32_t op1, uint32_t op2)
+static inline uint32_t efssub(uint32_t op1, uint32_t op2)
{
CPU_FloatU u1, u2;
u1.l = op1;
@@ -3292,7 +3292,7 @@ static always_inline uint32_t efssub (uint32_t op1, uint32_t op2)
return u1.l;
}
-static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2)
+static inline uint32_t efsmul(uint32_t op1, uint32_t op2)
{
CPU_FloatU u1, u2;
u1.l = op1;
@@ -3301,7 +3301,7 @@ static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2)
return u1.l;
}
-static always_inline uint32_t efsdiv (uint32_t op1, uint32_t op2)
+static inline uint32_t efsdiv(uint32_t op1, uint32_t op2)
{
CPU_FloatU u1, u2;
u1.l = op1;
@@ -3340,7 +3340,7 @@ HELPER_SPE_VECTOR_ARITH(fsmul);
HELPER_SPE_VECTOR_ARITH(fsdiv);
/* Single-precision floating-point comparisons */
-static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2)
+static inline uint32_t efststlt(uint32_t op1, uint32_t op2)
{
CPU_FloatU u1, u2;
u1.l = op1;
@@ -3348,7 +3348,7 @@ static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2)
return float32_lt(u1.f, u2.f, &env->vec_status) ? 4 : 0;
}
-static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
+static inline uint32_t efststgt(uint32_t op1, uint32_t op2)
{
CPU_FloatU u1, u2;
u1.l = op1;
@@ -3356,7 +3356,7 @@ static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
return float32_le(u1.f, u2.f, &env->vec_status) ? 0 : 4;
}
-static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
+static inline uint32_t efststeq(uint32_t op1, uint32_t op2)
{
CPU_FloatU u1, u2;
u1.l = op1;
@@ -3364,19 +3364,19 @@ static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
return float32_eq(u1.f, u2.f, &env->vec_status) ? 4 : 0;
}
-static always_inline uint32_t efscmplt (uint32_t op1, uint32_t op2)
+static inline uint32_t efscmplt(uint32_t op1, uint32_t op2)
{
/* XXX: TODO: test special values (NaN, infinites, ...) */
return efststlt(op1, op2);
}
-static always_inline uint32_t efscmpgt (uint32_t op1, uint32_t op2)
+static inline uint32_t efscmpgt(uint32_t op1, uint32_t op2)
{
/* XXX: TODO: test special values (NaN, infinites, ...) */
return efststgt(op1, op2);
}
-static always_inline uint32_t efscmpeq (uint32_t op1, uint32_t op2)
+static inline uint32_t efscmpeq(uint32_t op1, uint32_t op2)
{
/* XXX: TODO: test special values (NaN, infinites, ...) */
return efststeq(op1, op2);
@@ -3400,7 +3400,7 @@ HELPER_SINGLE_SPE_CMP(fscmpgt);
/* efscmpeq */
HELPER_SINGLE_SPE_CMP(fscmpeq);
-static always_inline uint32_t evcmp_merge (int t0, int t1)
+static inline uint32_t evcmp_merge(int t0, int t1)
{
return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
}
@@ -3804,9 +3804,9 @@ static void do_6xx_tlb (target_ulong new_EPN, int is_code)
EPN = env->spr[SPR_DMISS];
}
way = (env->spr[SPR_SRR1] >> 17) & 1;
- LOG_SWTLB("%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
- " PTE1 " ADDRX " way %d\n",
- __func__, new_EPN, EPN, CMP, RPN, way);
+ LOG_SWTLB("%s: EPN " TARGET_FMT_lx " " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx
+ " PTE1 " TARGET_FMT_lx " way %d\n", __func__, new_EPN, EPN, CMP,
+ RPN, way);
/* Store this TLB */
ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
way, is_code, CMP, RPN);
@@ -3832,9 +3832,9 @@ static void do_74xx_tlb (target_ulong new_EPN, int is_code)
CMP = env->spr[SPR_PTEHI];
EPN = env->spr[SPR_TLBMISS] & ~0x3;
way = env->spr[SPR_TLBMISS] & 0x3;
- LOG_SWTLB("%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
- " PTE1 " ADDRX " way %d\n",
- __func__, new_EPN, EPN, CMP, RPN, way);
+ LOG_SWTLB("%s: EPN " TARGET_FMT_lx " " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx
+ " PTE1 " TARGET_FMT_lx " way %d\n", __func__, new_EPN, EPN, CMP,
+ RPN, way);
/* Store this TLB */
ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
way, is_code, CMP, RPN);
@@ -3850,12 +3850,12 @@ void helper_74xx_tlbi (target_ulong EPN)
do_74xx_tlb(EPN, 1);
}
-static always_inline target_ulong booke_tlb_to_page_size (int size)
+static inline target_ulong booke_tlb_to_page_size(int size)
{
return 1024 << (2 * size);
}
-static always_inline int booke_page_size_to_tlb (target_ulong page_size)
+static inline int booke_page_size_to_tlb(target_ulong page_size)
{
int size;
@@ -3958,14 +3958,15 @@ void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val)
ppcemb_tlb_t *tlb;
target_ulong page, end;
- LOG_SWTLB("%s entry %d val " ADDRX "\n", __func__, (int)entry, val);
+ LOG_SWTLB("%s entry %d val " TARGET_FMT_lx "\n", __func__, (int)entry,
+ val);
entry &= 0x3F;
tlb = &env->tlb[entry].tlbe;
/* Invalidate previous TLB (if it's valid) */
if (tlb->prot & PAGE_VALID) {
end = tlb->EPN + tlb->size;
- LOG_SWTLB("%s: invalidate old TLB %d start " ADDRX
- " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
+ LOG_SWTLB("%s: invalidate old TLB %d start " TARGET_FMT_lx " end "
+ TARGET_FMT_lx "\n", __func__, (int)entry, tlb->EPN, end);
for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
tlb_flush_page(env, page);
}
@@ -3990,18 +3991,18 @@ void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val)
}
tlb->PID = env->spr[SPR_40x_PID]; /* PID */
tlb->attr = val & 0xFF;
- LOG_SWTLB("%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
- " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
- (int)entry, tlb->RPN, tlb->EPN, tlb->size,
- tlb->prot & PAGE_READ ? 'r' : '-',
- tlb->prot & PAGE_WRITE ? 'w' : '-',
- tlb->prot & PAGE_EXEC ? 'x' : '-',
- tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
+ LOG_SWTLB("%s: set up TLB %d RPN " TARGET_FMT_plx " EPN " TARGET_FMT_lx
+ " size " TARGET_FMT_lx " prot %c%c%c%c PID %d\n", __func__,
+ (int)entry, tlb->RPN, tlb->EPN, tlb->size,
+ tlb->prot & PAGE_READ ? 'r' : '-',
+ tlb->prot & PAGE_WRITE ? 'w' : '-',
+ tlb->prot & PAGE_EXEC ? 'x' : '-',
+ tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
/* Invalidate new TLB (if valid) */
if (tlb->prot & PAGE_VALID) {
end = tlb->EPN + tlb->size;
- LOG_SWTLB("%s: invalidate TLB %d start " ADDRX
- " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
+ LOG_SWTLB("%s: invalidate TLB %d start " TARGET_FMT_lx " end "
+ TARGET_FMT_lx "\n", __func__, (int)entry, tlb->EPN, end);
for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
tlb_flush_page(env, page);
}
@@ -4011,7 +4012,8 @@ void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val)
{
ppcemb_tlb_t *tlb;
- LOG_SWTLB("%s entry %i val " ADDRX "\n", __func__, (int)entry, val);
+ LOG_SWTLB("%s entry %i val " TARGET_FMT_lx "\n", __func__, (int)entry,
+ val);
entry &= 0x3F;
tlb = &env->tlb[entry].tlbe;
tlb->RPN = val & 0xFFFFFC00;
@@ -4020,13 +4022,13 @@ void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val)
tlb->prot |= PAGE_EXEC;
if (val & 0x100)
tlb->prot |= PAGE_WRITE;
- LOG_SWTLB("%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
- " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
- (int)entry, tlb->RPN, tlb->EPN, tlb->size,
- tlb->prot & PAGE_READ ? 'r' : '-',
- tlb->prot & PAGE_WRITE ? 'w' : '-',
- tlb->prot & PAGE_EXEC ? 'x' : '-',
- tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
+ LOG_SWTLB("%s: set up TLB %d RPN " TARGET_FMT_plx " EPN " TARGET_FMT_lx
+ " size " TARGET_FMT_lx " prot %c%c%c%c PID %d\n", __func__,
+ (int)entry, tlb->RPN, tlb->EPN, tlb->size,
+ tlb->prot & PAGE_READ ? 'r' : '-',
+ tlb->prot & PAGE_WRITE ? 'w' : '-',
+ tlb->prot & PAGE_EXEC ? 'x' : '-',
+ tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
}
target_ulong helper_4xx_tlbsx (target_ulong address)
@@ -4041,8 +4043,8 @@ void helper_440_tlbwe (uint32_t word, target_ulong entry, target_ulong value)
target_ulong EPN, RPN, size;
int do_flush_tlbs;
- LOG_SWTLB("%s word %d entry %d value " ADDRX "\n",
- __func__, word, (int)entry, value);
+ LOG_SWTLB("%s word %d entry %d value " TARGET_FMT_lx "\n",
+ __func__, word, (int)entry, value);
do_flush_tlbs = 0;
entry &= 0x3F;
tlb = &env->tlb[entry].tlbe;
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index f82c6e5ba..1c54fa7d8 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -210,14 +210,14 @@ struct opc_handler_t {
#endif
};
-static always_inline void gen_reset_fpstatus (void)
+static inline void gen_reset_fpstatus(void)
{
#ifdef CONFIG_SOFTFLOAT
gen_helper_reset_fpstatus();
#endif
}
-static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
+static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
{
TCGv_i32 t0 = tcg_temp_new_i32();
@@ -239,7 +239,7 @@ static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_
tcg_temp_free_i32(t0);
}
-static always_inline void gen_set_access_type (DisasContext *ctx, int access_type)
+static inline void gen_set_access_type(DisasContext *ctx, int access_type)
{
if (ctx->access_type != access_type) {
tcg_gen_movi_i32(cpu_access_type, access_type);
@@ -247,7 +247,7 @@ static always_inline void gen_set_access_type (DisasContext *ctx, int access_typ
}
}
-static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
+static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
{
#if defined(TARGET_PPC64)
if (ctx->sf_mode)
@@ -257,7 +257,7 @@ static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
}
-static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, uint32_t error)
+static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
{
TCGv_i32 t0, t1;
if (ctx->exception == POWERPC_EXCP_NONE) {
@@ -271,7 +271,7 @@ static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, u
ctx->exception = (excp);
}
-static always_inline void gen_exception (DisasContext *ctx, uint32_t excp)
+static inline void gen_exception(DisasContext *ctx, uint32_t excp)
{
TCGv_i32 t0;
if (ctx->exception == POWERPC_EXCP_NONE) {
@@ -283,7 +283,7 @@ static always_inline void gen_exception (DisasContext *ctx, uint32_t excp)
ctx->exception = (excp);
}
-static always_inline void gen_debug_exception (DisasContext *ctx)
+static inline void gen_debug_exception(DisasContext *ctx)
{
TCGv_i32 t0;
@@ -294,20 +294,20 @@ static always_inline void gen_debug_exception (DisasContext *ctx)
tcg_temp_free_i32(t0);
}
-static always_inline void gen_inval_exception (DisasContext *ctx, uint32_t error)
+static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
{
gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
}
/* Stop translation */
-static always_inline void gen_stop_exception (DisasContext *ctx)
+static inline void gen_stop_exception(DisasContext *ctx)
{
gen_update_nip(ctx, ctx->nip);
ctx->exception = POWERPC_EXCP_STOP;
}
/* No need to update nip here, as execution flow will change */
-static always_inline void gen_sync_exception (DisasContext *ctx)
+static inline void gen_sync_exception(DisasContext *ctx)
{
ctx->exception = POWERPC_EXCP_SYNC;
}
@@ -332,13 +332,13 @@ typedef struct opcode_t {
/*****************************************************************************/
/*** Instruction decoding ***/
#define EXTRACT_HELPER(name, shift, nb) \
-static always_inline uint32_t name (uint32_t opcode) \
+static inline uint32_t name(uint32_t opcode) \
{ \
return (opcode >> (shift)) & ((1 << (nb)) - 1); \
}
#define EXTRACT_SHELPER(name, shift, nb) \
-static always_inline int32_t name (uint32_t opcode) \
+static inline int32_t name(uint32_t opcode) \
{ \
return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
}
@@ -369,7 +369,7 @@ EXTRACT_HELPER(crbA, 16, 5);
EXTRACT_HELPER(crbB, 11, 5);
/* SPR / TBL */
EXTRACT_HELPER(_SPR, 11, 10);
-static always_inline uint32_t SPR (uint32_t opcode)
+static inline uint32_t SPR(uint32_t opcode)
{
uint32_t sprn = _SPR(opcode);
@@ -407,12 +407,12 @@ EXTRACT_HELPER(FPIMM, 12, 4);
/* Displacement */
EXTRACT_SHELPER(d, 0, 16);
/* Immediate address */
-static always_inline target_ulong LI (uint32_t opcode)
+static inline target_ulong LI(uint32_t opcode)
{
return (opcode >> 0) & 0x03FFFFFC;
}
-static always_inline uint32_t BD (uint32_t opcode)
+static inline uint32_t BD(uint32_t opcode)
{
return (opcode >> 0) & 0xFFFC;
}
@@ -425,7 +425,7 @@ EXTRACT_HELPER(AA, 1, 1);
EXTRACT_HELPER(LK, 0, 1);
/* Create a mask between <start> and <end> bits */
-static always_inline target_ulong MASK (uint32_t start, uint32_t end)
+static inline target_ulong MASK(uint32_t start, uint32_t end)
{
target_ulong ret;
@@ -514,12 +514,12 @@ static always_inline target_ulong MASK (uint32_t start, uint32_t end)
#endif
/* SPR load/store helpers */
-static always_inline void gen_load_spr(TCGv t, int reg)
+static inline void gen_load_spr(TCGv t, int reg)
{
tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
}
-static always_inline void gen_store_spr(int reg, TCGv t)
+static inline void gen_store_spr(int reg, TCGv t)
{
tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
}
@@ -538,7 +538,7 @@ static opc_handler_t invalid_handler = {
/*** Integer comparison ***/
-static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
+static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
{
int l1, l2, l3;
@@ -566,7 +566,7 @@ static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
gen_set_label(l3);
}
-static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
+static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
{
TCGv t0 = tcg_const_local_tl(arg1);
gen_op_cmp(arg0, t0, s, crf);
@@ -574,7 +574,7 @@ static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int c
}
#if defined(TARGET_PPC64)
-static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
+static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
{
TCGv t0, t1;
t0 = tcg_temp_local_new();
@@ -591,7 +591,7 @@ static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
tcg_temp_free(t0);
}
-static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
+static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
{
TCGv t0 = tcg_const_local_tl(arg1);
gen_op_cmp32(arg0, t0, s, crf);
@@ -599,7 +599,7 @@ static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int
}
#endif
-static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
+static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
{
#if defined(TARGET_PPC64)
if (!(ctx->sf_mode))
@@ -689,7 +689,8 @@ static void gen_isel(DisasContext *ctx)
/*** Integer arithmetic ***/
-static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
+static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
+ TCGv arg1, TCGv arg2, int sub)
{
int l1;
TCGv t0;
@@ -721,7 +722,8 @@ static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
tcg_temp_free(t0);
}
-static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
+static inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1,
+ TCGv arg2, int sub)
{
int l1 = gen_new_label();
@@ -756,8 +758,9 @@ static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1,
}
/* Common add function */
-static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
- int add_ca, int compute_ca, int compute_ov)
+static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
+ TCGv arg2, int add_ca, int compute_ca,
+ int compute_ov)
{
TCGv t0, t1;
@@ -857,8 +860,8 @@ static void gen_addi(DisasContext *ctx)
}
}
/* addic addic.*/
-static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
- int compute_Rc0)
+static inline void gen_op_addic(DisasContext *ctx, TCGv ret, TCGv arg1,
+ int compute_Rc0)
{
target_long simm = SIMM(ctx->opcode);
@@ -902,8 +905,8 @@ static void gen_addis(DisasContext *ctx)
}
}
-static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
- int sign, int compute_ov)
+static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
+ TCGv arg2, int sign, int compute_ov)
{
int l1 = gen_new_label();
int l2 = gen_new_label();
@@ -957,8 +960,8 @@ GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
#if defined(TARGET_PPC64)
-static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
- int sign, int compute_ov)
+static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
+ TCGv arg2, int sign, int compute_ov)
{
int l1 = gen_new_label();
int l2 = gen_new_label();
@@ -1133,7 +1136,8 @@ GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
#endif
/* neg neg. nego nego. */
-static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
+static inline void gen_op_arith_neg(DisasContext *ctx, TCGv ret, TCGv arg1,
+ int ov_check)
{
int l1 = gen_new_label();
int l2 = gen_new_label();
@@ -1175,8 +1179,9 @@ static void gen_nego(DisasContext *ctx)
}
/* Common subf function */
-static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
- int add_ca, int compute_ca, int compute_ov)
+static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
+ TCGv arg2, int add_ca, int compute_ca,
+ int compute_ov)
{
TCGv t0, t1;
@@ -1658,8 +1663,8 @@ static void glue(gen_, name##3)(DisasContext *ctx) \
gen_##name(ctx, 1, 1); \
}
-static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
- uint32_t me, uint32_t sh)
+static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
+ uint32_t sh)
{
if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
@@ -1679,7 +1684,7 @@ static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
}
/* rldicl - rldicl. */
-static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
+static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
{
uint32_t sh, mb;
@@ -1689,7 +1694,7 @@ static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
}
GEN_PPC64_R4(rldicl, 0x1E, 0x00);
/* rldicr - rldicr. */
-static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
+static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
{
uint32_t sh, me;
@@ -1699,7 +1704,7 @@ static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
}
GEN_PPC64_R4(rldicr, 0x1E, 0x02);
/* rldic - rldic. */
-static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
+static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
{
uint32_t sh, mb;
@@ -1709,8 +1714,7 @@ static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
}
GEN_PPC64_R4(rldic, 0x1E, 0x04);
-static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
- uint32_t me)
+static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
{
TCGv t0;
@@ -1730,7 +1734,7 @@ static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
}
/* rldcl - rldcl. */
-static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
+static inline void gen_rldcl(DisasContext *ctx, int mbn)
{
uint32_t mb;
@@ -1739,7 +1743,7 @@ static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
}
GEN_PPC64_R2(rldcl, 0x1E, 0x08);
/* rldcr - rldcr. */
-static always_inline void gen_rldcr (DisasContext *ctx, int men)
+static inline void gen_rldcr(DisasContext *ctx, int men)
{
uint32_t me;
@@ -1748,7 +1752,7 @@ static always_inline void gen_rldcr (DisasContext *ctx, int men)
}
GEN_PPC64_R2(rldcr, 0x1E, 0x09);
/* rldimi - rldimi. */
-static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
+static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
{
uint32_t sh, mb, me;
@@ -1895,7 +1899,7 @@ static void gen_srad(DisasContext *ctx)
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
}
/* sradi & sradi. */
-static always_inline void gen_sradi (DisasContext *ctx, int n)
+static inline void gen_sradi(DisasContext *ctx, int n)
{
int sh = SH(ctx->opcode) + (n << 5);
if (sh != 0) {
@@ -2348,7 +2352,8 @@ static void gen_mtfsfi(DisasContext *ctx)
/*** Addressing modes ***/
/* Register indirect with immediate index : EA = (rA|0) + SIMM */
-static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target_long maskl)
+static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
+ target_long maskl)
{
target_long simm = SIMM(ctx->opcode);
@@ -2377,7 +2382,7 @@ static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target
}
}
-static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA)
+static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
{
if (rA(ctx->opcode) == 0) {
#if defined(TARGET_PPC64)
@@ -2396,7 +2401,7 @@ static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA)
}
}
-static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA)
+static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
{
if (rA(ctx->opcode) == 0) {
tcg_gen_movi_tl(EA, 0);
@@ -2410,7 +2415,8 @@ static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA)
}
}
-static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1, target_long val)
+static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
+ target_long val)
{
tcg_gen_addi_tl(ret, arg1, val);
#if defined(TARGET_PPC64)
@@ -2420,7 +2426,7 @@ static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1,
#endif
}
-static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
+static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
{
int l1 = gen_new_label();
TCGv t0 = tcg_temp_new();
@@ -2439,17 +2445,17 @@ static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
}
/*** Integer load ***/
-static always_inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
+static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
}
-static always_inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
+static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
}
-static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
+static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
if (unlikely(ctx->le_mode)) {
@@ -2457,7 +2463,7 @@ static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2
}
}
-static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
+static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
if (unlikely(ctx->le_mode)) {
tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
@@ -2468,7 +2474,7 @@ static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2
}
}
-static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
+static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
if (unlikely(ctx->le_mode)) {
@@ -2477,7 +2483,7 @@ static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2
}
#if defined(TARGET_PPC64)
-static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
+static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
if (unlikely(ctx->le_mode)) {
tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
@@ -2488,7 +2494,7 @@ static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2
}
#endif
-static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
+static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
{
tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
if (unlikely(ctx->le_mode)) {
@@ -2496,12 +2502,12 @@ static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv a
}
}
-static always_inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
+static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
}
-static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
+static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
if (unlikely(ctx->le_mode)) {
TCGv t0 = tcg_temp_new();
@@ -2514,7 +2520,7 @@ static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
}
}
-static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
+static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
if (unlikely(ctx->le_mode)) {
TCGv t0 = tcg_temp_new();
@@ -2527,7 +2533,7 @@ static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
}
}
-static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
+static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
{
if (unlikely(ctx->le_mode)) {
TCGv_i64 t0 = tcg_temp_new_i64();
@@ -2808,7 +2814,7 @@ static void gen_std(DisasContext *ctx)
#endif
/*** Integer load and store with byte reverse ***/
/* lhbrx */
-static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
+static void inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
if (likely(!ctx->le_mode)) {
@@ -2818,7 +2824,7 @@ static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg
GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
/* lwbrx */
-static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
+static void inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
if (likely(!ctx->le_mode)) {
@@ -2828,7 +2834,7 @@ static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg
GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
/* sthbrx */
-static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
+static void inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
if (likely(!ctx->le_mode)) {
TCGv t0 = tcg_temp_new();
@@ -2843,7 +2849,7 @@ static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2
GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
/* stwbrx */
-static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
+static void inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
if (likely(!ctx->le_mode)) {
TCGv t0 = tcg_temp_new();
@@ -3200,7 +3206,7 @@ GEN_LDUF(name, ldop, op | 0x21, type); \
GEN_LDUXF(name, ldop, op | 0x01, type); \
GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
-static always_inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
+static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
{
TCGv t0 = tcg_temp_new();
TCGv_i32 t1 = tcg_temp_new_i32();
@@ -3293,7 +3299,7 @@ GEN_STUF(name, stop, op | 0x21, type); \
GEN_STUXF(name, stop, op | 0x01, type); \
GEN_STXF(name, stop, 0x17, op | 0x00, type)
-static always_inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
+static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
{
TCGv_i32 t0 = tcg_temp_new_i32();
TCGv t1 = tcg_temp_new();
@@ -3310,7 +3316,7 @@ GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
/* Optional: */
-static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
+static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
{
TCGv t0 = tcg_temp_new();
tcg_gen_trunc_i64_tl(t0, arg1),
@@ -3321,8 +3327,7 @@ static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCG
GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
/*** Branch ***/
-static always_inline void gen_goto_tb (DisasContext *ctx, int n,
- target_ulong dest)
+static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
{
TranslationBlock *tb;
tb = ctx->tb;
@@ -3354,7 +3359,7 @@ static always_inline void gen_goto_tb (DisasContext *ctx, int n,
}
}
-static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
+static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
{
#if defined(TARGET_PPC64)
if (ctx->sf_mode == 0)
@@ -3390,7 +3395,7 @@ static void gen_b(DisasContext *ctx)
#define BCOND_LR 1
#define BCOND_CTR 2
-static always_inline void gen_bcond (DisasContext *ctx, int type)
+static inline void gen_bcond(DisasContext *ctx, int type)
{
uint32_t bo = BO(ctx->opcode);
int l1 = gen_new_label();
@@ -3726,7 +3731,7 @@ static void spr_noaccess (void *opaque, int sprn)
#endif
/* mfspr */
-static always_inline void gen_op_mfspr (DisasContext *ctx)
+static inline void gen_op_mfspr(DisasContext *ctx)
{
void (*read_cb)(void *opaque, int gprn, int sprn);
uint32_t sprn = SPR(ctx->opcode);
@@ -3750,17 +3755,17 @@ static always_inline void gen_op_mfspr (DisasContext *ctx)
*/
if (sprn != SPR_PVR) {
qemu_log("Trying to read privileged spr %d %03x at "
- ADDRX "\n", sprn, sprn, ctx->nip);
- printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
- sprn, sprn, ctx->nip);
+ TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
+ printf("Trying to read privileged spr %d %03x at "
+ TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
}
gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
}
} else {
/* Not defined */
qemu_log("Trying to read invalid spr %d %03x at "
- ADDRX "\n", sprn, sprn, ctx->nip);
- printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
+ TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
+ printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n",
sprn, sprn, ctx->nip);
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
}
@@ -3900,16 +3905,16 @@ static void gen_mtspr(DisasContext *ctx)
} else {
/* Privilege exception */
qemu_log("Trying to write privileged spr %d %03x at "
- ADDRX "\n", sprn, sprn, ctx->nip);
- printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
- sprn, sprn, ctx->nip);
+ TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
+ printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
+ "\n", sprn, sprn, ctx->nip);
gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
}
} else {
/* Not defined */
qemu_log("Trying to write invalid spr %d %03x at "
- ADDRX "\n", sprn, sprn, ctx->nip);
- printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
+ TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
+ printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n",
sprn, sprn, ctx->nip);
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
}
@@ -5333,9 +5338,8 @@ static void gen_tlbiva(DisasContext *ctx)
}
/* All 405 MAC instructions are translated here */
-static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
- int opc2, int opc3,
- int ra, int rb, int rt, int Rc)
+static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
+ int ra, int rb, int rt, int Rc)
{
TCGv t0, t1;
@@ -6015,7 +6019,7 @@ static void gen_icbt_440(DisasContext *ctx)
/*** Altivec vector extension ***/
/* Altivec registers moves */
-static always_inline TCGv_ptr gen_avr_ptr(int reg)
+static inline TCGv_ptr gen_avr_ptr(int reg)
{
TCGv_ptr r = tcg_temp_new_ptr();
tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
@@ -6499,7 +6503,8 @@ GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
/*** SPE extension ***/
/* Register moves */
-static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
+static inline void gen_load_gpr64(TCGv_i64 t, int reg)
+{
#if defined(TARGET_PPC64)
tcg_gen_mov_i64(t, cpu_gpr[reg]);
#else
@@ -6507,7 +6512,8 @@ static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
#endif
}
-static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
+static inline void gen_store_gpr64(int reg, TCGv_i64 t)
+{
#if defined(TARGET_PPC64)
tcg_gen_mov_i64(cpu_gpr[reg], t);
#else
@@ -6529,7 +6535,7 @@ static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
}
/* Handler for undefined SPE opcodes */
-static always_inline void gen_speundef (DisasContext *ctx)
+static inline void gen_speundef(DisasContext *ctx)
{
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
}
@@ -6537,7 +6543,7 @@ static always_inline void gen_speundef (DisasContext *ctx)
/* SPE logic */
#if defined(TARGET_PPC64)
#define GEN_SPEOP_LOGIC2(name, tcg_op) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
@@ -6548,7 +6554,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
}
#else
#define GEN_SPEOP_LOGIC2(name, tcg_op) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
@@ -6573,7 +6579,7 @@ GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
/* SPE logic immediate */
#if defined(TARGET_PPC64)
#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
@@ -6594,7 +6600,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
}
#else
#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
@@ -6614,7 +6620,7 @@ GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
/* SPE arithmetic */
#if defined(TARGET_PPC64)
#define GEN_SPEOP_ARITH1(name, tcg_op) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
@@ -6635,7 +6641,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
}
#else
#define GEN_SPEOP_ARITH1(name, tcg_op) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
@@ -6646,7 +6652,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
}
#endif
-static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
+static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
{
int l1 = gen_new_label();
int l2 = gen_new_label();
@@ -6662,7 +6668,7 @@ GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
-static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
+static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
{
tcg_gen_addi_i32(ret, arg1, 0x8000);
tcg_gen_ext16u_i32(ret, ret);
@@ -6673,7 +6679,7 @@ GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
#if defined(TARGET_PPC64)
#define GEN_SPEOP_ARITH2(name, tcg_op) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
@@ -6699,7 +6705,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
}
#else
#define GEN_SPEOP_ARITH2(name, tcg_op) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
@@ -6712,7 +6718,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
}
#endif
-static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
+static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
TCGv_i32 t0;
int l1, l2;
@@ -6731,7 +6737,7 @@ static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 a
tcg_temp_free_i32(t0);
}
GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
-static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
+static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
TCGv_i32 t0;
int l1, l2;
@@ -6750,7 +6756,7 @@ static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 a
tcg_temp_free_i32(t0);
}
GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
-static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
+static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
TCGv_i32 t0;
int l1, l2;
@@ -6769,7 +6775,7 @@ static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 ar
tcg_temp_free_i32(t0);
}
GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
-static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
+static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
TCGv_i32 t0 = tcg_temp_new_i32();
tcg_gen_andi_i32(t0, arg2, 0x1F);
@@ -6777,7 +6783,7 @@ static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 ar
tcg_temp_free_i32(t0);
}
GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
-static always_inline void gen_evmergehi (DisasContext *ctx)
+static inline void gen_evmergehi(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU);
@@ -6797,7 +6803,7 @@ static always_inline void gen_evmergehi (DisasContext *ctx)
#endif
}
GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
-static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
+static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
tcg_gen_sub_i32(ret, arg2, arg1);
}
@@ -6806,7 +6812,7 @@ GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
/* SPE arithmetic immediate */
#if defined(TARGET_PPC64)
#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
@@ -6827,7 +6833,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
}
#else
#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
@@ -6845,7 +6851,7 @@ GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
/* SPE comparison */
#if defined(TARGET_PPC64)
#define GEN_SPEOP_COMP(name, tcg_cond) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
@@ -6885,7 +6891,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
}
#else
#define GEN_SPEOP_COMP(name, tcg_cond) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
@@ -6922,13 +6928,13 @@ GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
/* SPE misc */
-static always_inline void gen_brinc (DisasContext *ctx)
+static inline void gen_brinc(DisasContext *ctx)
{
/* Note: brinc is usable even if SPE is disabled */
gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
}
-static always_inline void gen_evmergelo (DisasContext *ctx)
+static inline void gen_evmergelo(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU);
@@ -6947,7 +6953,7 @@ static always_inline void gen_evmergelo (DisasContext *ctx)
tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
#endif
}
-static always_inline void gen_evmergehilo (DisasContext *ctx)
+static inline void gen_evmergehilo(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU);
@@ -6966,7 +6972,7 @@ static always_inline void gen_evmergehilo (DisasContext *ctx)
tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
#endif
}
-static always_inline void gen_evmergelohi (DisasContext *ctx)
+static inline void gen_evmergelohi(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU);
@@ -6993,7 +6999,7 @@ static always_inline void gen_evmergelohi (DisasContext *ctx)
}
#endif
}
-static always_inline void gen_evsplati (DisasContext *ctx)
+static inline void gen_evsplati(DisasContext *ctx)
{
uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
@@ -7004,7 +7010,7 @@ static always_inline void gen_evsplati (DisasContext *ctx)
tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
#endif
}
-static always_inline void gen_evsplatfi (DisasContext *ctx)
+static inline void gen_evsplatfi(DisasContext *ctx)
{
uint64_t imm = rA(ctx->opcode) << 11;
@@ -7016,7 +7022,7 @@ static always_inline void gen_evsplatfi (DisasContext *ctx)
#endif
}
-static always_inline void gen_evsel (DisasContext *ctx)
+static inline void gen_evsel(DisasContext *ctx)
{
int l1 = gen_new_label();
int l2 = gen_new_label();
@@ -7112,7 +7118,7 @@ GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
/* SPE load and stores */
-static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, TCGv EA, int sh)
+static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
{
target_ulong uimm = rB(ctx->opcode);
@@ -7128,7 +7134,7 @@ static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, TCGv EA, in
}
}
-static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
{
#if defined(TARGET_PPC64)
gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
@@ -7142,7 +7148,7 @@ static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
#endif
}
-static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
{
#if defined(TARGET_PPC64)
TCGv t0 = tcg_temp_new();
@@ -7159,7 +7165,7 @@ static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
#endif
}
-static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
{
TCGv t0 = tcg_temp_new();
#if defined(TARGET_PPC64)
@@ -7192,7 +7198,7 @@ static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
tcg_temp_free(t0);
}
-static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
{
TCGv t0 = tcg_temp_new();
gen_qemu_ld16u(ctx, t0, addr);
@@ -7208,7 +7214,7 @@ static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
tcg_temp_free(t0);
}
-static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
{
TCGv t0 = tcg_temp_new();
gen_qemu_ld16u(ctx, t0, addr);
@@ -7222,7 +7228,7 @@ static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
tcg_temp_free(t0);
}
-static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
{
TCGv t0 = tcg_temp_new();
gen_qemu_ld16s(ctx, t0, addr);
@@ -7237,7 +7243,7 @@ static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
tcg_temp_free(t0);
}
-static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
{
TCGv t0 = tcg_temp_new();
#if defined(TARGET_PPC64)
@@ -7257,7 +7263,7 @@ static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
tcg_temp_free(t0);
}
-static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
{
#if defined(TARGET_PPC64)
TCGv t0 = tcg_temp_new();
@@ -7274,7 +7280,7 @@ static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
#endif
}
-static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
{
#if defined(TARGET_PPC64)
TCGv t0 = tcg_temp_new();
@@ -7292,7 +7298,7 @@ static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
#endif
}
-static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
{
TCGv t0 = tcg_temp_new();
gen_qemu_ld32u(ctx, t0, addr);
@@ -7306,7 +7312,7 @@ static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
tcg_temp_free(t0);
}
-static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
{
TCGv t0 = tcg_temp_new();
#if defined(TARGET_PPC64)
@@ -7331,7 +7337,7 @@ static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
tcg_temp_free(t0);
}
-static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
{
#if defined(TARGET_PPC64)
gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
@@ -7343,7 +7349,7 @@ static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
#endif
}
-static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
{
#if defined(TARGET_PPC64)
TCGv t0 = tcg_temp_new();
@@ -7357,7 +7363,7 @@ static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
}
-static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
{
TCGv t0 = tcg_temp_new();
#if defined(TARGET_PPC64)
@@ -7381,7 +7387,7 @@ static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
}
-static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
{
TCGv t0 = tcg_temp_new();
#if defined(TARGET_PPC64)
@@ -7396,7 +7402,7 @@ static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
tcg_temp_free(t0);
}
-static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
{
#if defined(TARGET_PPC64)
TCGv t0 = tcg_temp_new();
@@ -7410,7 +7416,7 @@ static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
}
-static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
{
#if defined(TARGET_PPC64)
TCGv t0 = tcg_temp_new();
@@ -7422,7 +7428,7 @@ static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
#endif
}
-static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
{
gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
}
@@ -7545,7 +7551,7 @@ GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
/*** SPE floating-point extension ***/
#if defined(TARGET_PPC64)
#define GEN_SPEFPUOP_CONV_32_32(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
TCGv_i32 t0; \
TCGv t1; \
@@ -7561,7 +7567,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
tcg_temp_free(t1); \
}
#define GEN_SPEFPUOP_CONV_32_64(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
TCGv_i32 t0; \
TCGv t1; \
@@ -7576,7 +7582,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
tcg_temp_free(t1); \
}
#define GEN_SPEFPUOP_CONV_64_32(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
TCGv_i32 t0 = tcg_temp_new_i32(); \
tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
@@ -7584,12 +7590,12 @@ static always_inline void gen_##name (DisasContext *ctx) \
tcg_temp_free_i32(t0); \
}
#define GEN_SPEFPUOP_CONV_64_64(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
}
#define GEN_SPEFPUOP_ARITH2_32_32(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
TCGv_i32 t0, t1; \
TCGv_i64 t2; \
@@ -7612,7 +7618,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
tcg_temp_free(t2); \
}
#define GEN_SPEFPUOP_ARITH2_64_64(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
@@ -7622,7 +7628,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
cpu_gpr[rB(ctx->opcode)]); \
}
#define GEN_SPEFPUOP_COMP_32(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
TCGv_i32 t0, t1; \
if (unlikely(!ctx->spe_enabled)) { \
@@ -7638,7 +7644,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
tcg_temp_free_i32(t1); \
}
#define GEN_SPEFPUOP_COMP_64(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
@@ -7649,12 +7655,12 @@ static always_inline void gen_##name (DisasContext *ctx) \
}
#else
#define GEN_SPEFPUOP_CONV_32_32(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
}
#define GEN_SPEFPUOP_CONV_32_64(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
TCGv_i64 t0 = tcg_temp_new_i64(); \
gen_load_gpr64(t0, rB(ctx->opcode)); \
@@ -7662,7 +7668,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
tcg_temp_free_i64(t0); \
}
#define GEN_SPEFPUOP_CONV_64_32(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
TCGv_i64 t0 = tcg_temp_new_i64(); \
gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
@@ -7670,7 +7676,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
tcg_temp_free_i64(t0); \
}
#define GEN_SPEFPUOP_CONV_64_64(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
TCGv_i64 t0 = tcg_temp_new_i64(); \
gen_load_gpr64(t0, rB(ctx->opcode)); \
@@ -7679,7 +7685,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
tcg_temp_free_i64(t0); \
}
#define GEN_SPEFPUOP_ARITH2_32_32(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
@@ -7689,7 +7695,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
}
#define GEN_SPEFPUOP_ARITH2_64_64(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
TCGv_i64 t0, t1; \
if (unlikely(!ctx->spe_enabled)) { \
@@ -7706,7 +7712,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
tcg_temp_free_i64(t1); \
}
#define GEN_SPEFPUOP_COMP_32(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
@@ -7716,7 +7722,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
}
#define GEN_SPEFPUOP_COMP_64(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
TCGv_i64 t0, t1; \
if (unlikely(!ctx->spe_enabled)) { \
@@ -7739,7 +7745,7 @@ GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
GEN_SPEFPUOP_ARITH2_64_64(evfssub);
GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
-static always_inline void gen_evfsabs (DisasContext *ctx)
+static inline void gen_evfsabs(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU);
@@ -7752,7 +7758,7 @@ static always_inline void gen_evfsabs (DisasContext *ctx)
tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
#endif
}
-static always_inline void gen_evfsnabs (DisasContext *ctx)
+static inline void gen_evfsnabs(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU);
@@ -7765,7 +7771,7 @@ static always_inline void gen_evfsnabs (DisasContext *ctx)
tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
#endif
}
-static always_inline void gen_evfsneg (DisasContext *ctx)
+static inline void gen_evfsneg(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU);
@@ -7821,7 +7827,7 @@ GEN_SPEFPUOP_ARITH2_32_32(efsadd);
GEN_SPEFPUOP_ARITH2_32_32(efssub);
GEN_SPEFPUOP_ARITH2_32_32(efsmul);
GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
-static always_inline void gen_efsabs (DisasContext *ctx)
+static inline void gen_efsabs(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU);
@@ -7829,7 +7835,7 @@ static always_inline void gen_efsabs (DisasContext *ctx)
}
tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
}
-static always_inline void gen_efsnabs (DisasContext *ctx)
+static inline void gen_efsnabs(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU);
@@ -7837,7 +7843,7 @@ static always_inline void gen_efsnabs (DisasContext *ctx)
}
tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
}
-static always_inline void gen_efsneg (DisasContext *ctx)
+static inline void gen_efsneg(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU);
@@ -7889,7 +7895,7 @@ GEN_SPEFPUOP_ARITH2_64_64(efdadd);
GEN_SPEFPUOP_ARITH2_64_64(efdsub);
GEN_SPEFPUOP_ARITH2_64_64(efdmul);
GEN_SPEFPUOP_ARITH2_64_64(efddiv);
-static always_inline void gen_efdabs (DisasContext *ctx)
+static inline void gen_efdabs(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU);
@@ -7901,7 +7907,7 @@ static always_inline void gen_efdabs (DisasContext *ctx)
tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
#endif
}
-static always_inline void gen_efdnabs (DisasContext *ctx)
+static inline void gen_efdnabs(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU);
@@ -7913,7 +7919,7 @@ static always_inline void gen_efdnabs (DisasContext *ctx)
tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
#endif
}
-static always_inline void gen_efdneg (DisasContext *ctx)
+static inline void gen_efdneg(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU);
@@ -8833,10 +8839,12 @@ void cpu_dump_state (CPUState *env, FILE *f,
int i;
- cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
- env->nip, env->lr, env->ctr, env->xer);
- cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
- env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
+ cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
+ TARGET_FMT_lx " XER %08x\n", env->nip, env->lr, env->ctr,
+ env->xer);
+ cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
+ TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
+ env->hflags, env->mmu_idx);
#if !defined(NO_TIMER_DUMP)
cpu_fprintf(f, "TB %08x %08x "
#if !defined(CONFIG_USER_ONLY)
@@ -8852,7 +8860,7 @@ void cpu_dump_state (CPUState *env, FILE *f,
for (i = 0; i < 32; i++) {
if ((i & (RGPL - 1)) == 0)
cpu_fprintf(f, "GPR%02d", i);
- cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
+ cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
if ((i & (RGPL - 1)) == (RGPL - 1))
cpu_fprintf(f, "\n");
}
@@ -8870,7 +8878,8 @@ void cpu_dump_state (CPUState *env, FILE *f,
a = 'E';
cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
}
- cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve_addr);
+ cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
+ env->reserve_addr);
for (i = 0; i < 32; i++) {
if ((i & (RFPL - 1)) == 0)
cpu_fprintf(f, "FPR%02d", i);
@@ -8880,8 +8889,9 @@ void cpu_dump_state (CPUState *env, FILE *f,
}
cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
#if !defined(CONFIG_USER_ONLY)
- cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
- env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
+ cpu_fprintf(f, "SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx " SDR1 "
+ TARGET_FMT_lx "\n", env->spr[SPR_SRR0], env->spr[SPR_SRR1],
+ env->sdr1);
#endif
#undef RGPL
@@ -8936,9 +8946,9 @@ void cpu_dump_statistics (CPUState *env, FILE*f,
}
/*****************************************************************************/
-static always_inline void gen_intermediate_code_internal (CPUState *env,
- TranslationBlock *tb,
- int search_pc)
+static inline void gen_intermediate_code_internal(CPUState *env,
+ TranslationBlock *tb,
+ int search_pc)
{
DisasContext ctx, *ctxp = &ctx;
opc_handler_t **table, *handler;
@@ -9010,7 +9020,7 @@ static always_inline void gen_intermediate_code_internal (CPUState *env,
gen_opc_icount[lj] = num_insns;
}
LOG_DISAS("----------------\n");
- LOG_DISAS("nip=" ADDRX " super=%d ir=%d\n",
+ LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
ctx.nip, ctx.mem_idx, (int)msr_ir);
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
gen_io_start();
@@ -9038,12 +9048,12 @@ static always_inline void gen_intermediate_code_internal (CPUState *env,
if (unlikely(handler->handler == &gen_invalid)) {
if (qemu_log_enabled()) {
qemu_log("invalid/unsupported opcode: "
- "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
- opc1(ctx.opcode), opc2(ctx.opcode),
- opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
+ "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
+ opc1(ctx.opcode), opc2(ctx.opcode),
+ opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
} else {
printf("invalid/unsupported opcode: "
- "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
+ "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
opc1(ctx.opcode), opc2(ctx.opcode),
opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
}
@@ -9051,13 +9061,13 @@ static always_inline void gen_intermediate_code_internal (CPUState *env,
if (unlikely((ctx.opcode & handler->inval) != 0)) {
if (qemu_log_enabled()) {
qemu_log("invalid bits: %08x for opcode: "
- "%02x - %02x - %02x (%08x) " ADDRX "\n",
- ctx.opcode & handler->inval, opc1(ctx.opcode),
- opc2(ctx.opcode), opc3(ctx.opcode),
- ctx.opcode, ctx.nip - 4);
+ "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
+ ctx.opcode & handler->inval, opc1(ctx.opcode),
+ opc2(ctx.opcode), opc3(ctx.opcode),
+ ctx.opcode, ctx.nip - 4);
} else {
printf("invalid bits: %08x for opcode: "
- "%02x - %02x - %02x (%08x) " ADDRX "\n",
+ "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
ctx.opcode & handler->inval, opc1(ctx.opcode),
opc2(ctx.opcode), opc3(ctx.opcode),
ctx.opcode, ctx.nip - 4);
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 1731d12ed..79d3b4ca9 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -543,8 +543,8 @@ static inline void spr_register (CPUPPCState *env, int num,
exit(1);
}
#if defined(PPC_DEBUG_SPR)
- printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
- initial_value);
+ printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
+ name, initial_value);
#endif
spr->name = name;
spr->uea_read = uea_read;
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 2428bb292..6654eca49 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -439,6 +439,22 @@ int cpu_sparc_exec(CPUSPARCState *s);
#endif
#ifndef NO_CPU_IO_DEFS
+
+static inline int cpu_cwp_inc(CPUSPARCState *env1, int cwp)
+{
+ if (unlikely(cwp >= env1->nwindows))
+ cwp -= env1->nwindows;
+ return cwp;
+}
+
+static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp)
+{
+ if (unlikely(cwp < 0))
+ cwp += env1->nwindows;
+ return cwp;
+}
+#endif
+
static inline void memcpy32(target_ulong *dst, const target_ulong *src)
{
dst[0] = src[0];
@@ -463,43 +479,25 @@ static inline void cpu_set_cwp(CPUSPARCState *env1, int new_cwp)
env1->regwptr = env1->regbase + (new_cwp * 16);
}
-static inline int cpu_cwp_inc(CPUSPARCState *env1, int cwp)
-{
- if (unlikely(cwp >= env1->nwindows))
- cwp -= env1->nwindows;
- return cwp;
-}
+/* sun4m.c, sun4u.c */
+void cpu_check_irqs(CPUSPARCState *env);
-static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp)
+static inline void PUT_PSR(CPUSPARCState *env1, target_ulong val)
{
- if (unlikely(cwp < 0))
- cwp += env1->nwindows;
- return cwp;
-}
+ env1->psr = val & PSR_ICC;
+ env1->psref = (val & PSR_EF)? 1 : 0;
+ env1->psrpil = (val & PSR_PIL) >> 8;
+#if ((!defined (TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
+ cpu_check_irqs(env1);
#endif
-
+ env1->psrs = (val & PSR_S)? 1 : 0;
+ env1->psrps = (val & PSR_PS)? 1 : 0;
#if !defined (TARGET_SPARC64)
-#define PUT_PSR(env, val) do { int _tmp = val; \
- env->psr = _tmp & PSR_ICC; \
- env->psref = (_tmp & PSR_EF)? 1 : 0; \
- env->psrpil = (_tmp & PSR_PIL) >> 8; \
- env->psrs = (_tmp & PSR_S)? 1 : 0; \
- env->psrps = (_tmp & PSR_PS)? 1 : 0; \
- env->psret = (_tmp & PSR_ET)? 1 : 0; \
- cpu_set_cwp(env, _tmp & PSR_CWP); \
- CC_OP = CC_OP_FLAGS; \
- } while (0)
-#else
-#define PUT_PSR(env, val) do { int _tmp = val; \
- env->psr = _tmp & PSR_ICC; \
- env->psref = (_tmp & PSR_EF)? 1 : 0; \
- env->psrpil = (_tmp & PSR_PIL) >> 8; \
- env->psrs = (_tmp & PSR_S)? 1 : 0; \
- env->psrps = (_tmp & PSR_PS)? 1 : 0; \
- cpu_set_cwp(env, _tmp & PSR_CWP); \
- CC_OP = CC_OP_FLAGS; \
- } while (0)
+ env1->psret = (val & PSR_ET)? 1 : 0;
#endif
+ cpu_set_cwp(env1, val & PSR_CWP);
+ env1->cc_op = CC_OP_FLAGS;
+}
#ifdef TARGET_SPARC64
#define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20))
@@ -585,9 +583,6 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
#include "cpu-all.h"
#include "exec-all.h"
-/* sum4m.c, sun4u.c */
-void cpu_check_irqs(CPUSPARCState *env);
-
#ifdef TARGET_SPARC64
/* sun4u.c */
void cpu_tick_set_count(void *opaque, uint64_t count);
diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index 31b61bc42..920432cb1 100644
--- a/target-sparc/helper.c
+++ b/target-sparc/helper.c
@@ -684,6 +684,7 @@ void cpu_reset(CPUSPARCState *env)
env->wim = 1;
#endif
env->regwptr = env->regbase + (env->cwp * 16);
+ CC_OP = CC_OP_FLAGS;
#if defined(CONFIG_USER_ONLY)
#ifdef TARGET_SPARC64
env->cleanwin = env->nwindows - 2;
@@ -697,7 +698,6 @@ void cpu_reset(CPUSPARCState *env)
#endif
env->psrs = 1;
env->psrps = 1;
- CC_OP = CC_OP_FLAGS;
#ifdef TARGET_SPARC64
env->pstate = PS_PRIV|PS_RED|PS_PEF|PS_AG;
env->hpstate = HS_PRIV;
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 9bbfd3cd2..61578ecc3 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -1134,6 +1134,7 @@ static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
} else {
dc->pc = dc->npc;
dc->npc = target;
+ tcg_gen_mov_tl(cpu_pc, cpu_npc);
}
} else {
flush_cond(dc, r_cond);
@@ -1174,6 +1175,7 @@ static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
} else {
dc->pc = dc->npc;
dc->npc = target;
+ tcg_gen_mov_tl(cpu_pc, cpu_npc);
}
} else {
flush_cond(dc, r_cond);
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 672373d3e..525994c9c 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -179,11 +179,36 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
return 0;
}
+static inline uint32_t rotl(uint32_t val, int n)
+{
+ return (val << n) | (val >> (32 - n));
+}
+
+/* ARM immediates for ALU instructions are made of an unsigned 8-bit
+ right-rotated by an even amount between 0 and 30. */
+static inline int encode_imm(uint32_t imm)
+{
+ /* simple case, only lower bits */
+ if ((imm & ~0xff) == 0)
+ return 0;
+ /* then try a simple even shift */
+ shift = ctz32(imm) & ~1;
+ if (((imm >> shift) & ~0xff) == 0)
+ return 32 - shift;
+ /* now try harder with rotations */
+ if ((rotl(imm, 2) & ~0xff) == 0)
+ return 2;
+ if ((rotl(imm, 4) & ~0xff) == 0)
+ return 4;
+ if ((rotl(imm, 6) & ~0xff) == 0)
+ return 6;
+ /* imm can't be encoded */
+ return -1;
+}
static inline int check_fit_imm(uint32_t imm)
{
- /* XXX: use rotation */
- return (imm & ~0xff) == 0;
+ return encode_imm(imm) >= 0;
}
/* Test if a constant matches the constraint.
@@ -1407,10 +1432,12 @@ static inline void tcg_out_op(TCGContext *s, int opc,
c = ARITH_EOR;
/* Fall through. */
gen_arith:
- if (const_args[2])
+ if (const_args[2]) {
+ int rot;
+ rot = encode_imm(args[2]);
tcg_out_dat_imm(s, COND_AL, c,
- args[0], args[1], args[2]);
- else
+ args[0], args[1], rotl(args[2], rot) | (rot << 7));
+ } else
tcg_out_dat_reg(s, COND_AL, c,
args[0], args[1], args[2], SHIFT_IMM_LSL(0));
break;
@@ -1427,6 +1454,10 @@ static inline void tcg_out_op(TCGContext *s, int opc,
case INDEX_op_neg_i32:
tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0);
break;
+ case INDEX_op_not_i32:
+ tcg_out_dat_reg(s, COND_AL,
+ ARITH_MVN, args[0], 0, args[1], SHIFT_IMM_LSL(0));
+ break;
case INDEX_op_mul_i32:
tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]);
break;
@@ -1561,6 +1592,7 @@ static const TCGTargetOpDef arm_op_defs[] = {
{ INDEX_op_or_i32, { "r", "r", "rI" } },
{ INDEX_op_xor_i32, { "r", "r", "rI" } },
{ INDEX_op_neg_i32, { "r", "r" } },
+ { INDEX_op_not_i32, { "r", "r" } },
{ INDEX_op_shl_i32, { "r", "r", "ri" } },
{ INDEX_op_shr_i32, { "r", "r", "ri" } },
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 7ff29281b..71e1ec550 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -33,6 +33,7 @@
#define TCG_TARGET_HAS_ext16s_i32
#define TCG_TARGET_HAS_neg_i32
#undef TCG_TARGET_HAS_neg_i64
+#define TCG_TARGET_HAS_not_i32
#undef TCG_TARGET_STACK_GROWSUP
enum {
diff --git a/vl.c b/vl.c
index dc1a820df..6a56de642 100644
--- a/vl.c
+++ b/vl.c
@@ -194,10 +194,7 @@ int vm_running;
int autostart;
static int rtc_utc = 1;
static int rtc_date_offset = -1; /* -1 means no change */
-int cirrus_vga_enabled = 1;
-int std_vga_enabled = 0;
-int vmsvga_enabled = 0;
-int xenfb_enabled = 0;
+int vga_interface_type = VGA_CIRRUS;
#ifdef TARGET_SPARC
int graphic_width = 1024;
int graphic_height = 768;
@@ -4551,18 +4548,15 @@ static void select_vgahw (const char *p)
{
const char *opts;
- cirrus_vga_enabled = 0;
- std_vga_enabled = 0;
- vmsvga_enabled = 0;
- xenfb_enabled = 0;
+ vga_interface_type = VGA_NONE;
if (strstart(p, "std", &opts)) {
- std_vga_enabled = 1;
+ vga_interface_type = VGA_STD;
} else if (strstart(p, "cirrus", &opts)) {
- cirrus_vga_enabled = 1;
+ vga_interface_type = VGA_CIRRUS;
} else if (strstart(p, "vmware", &opts)) {
- vmsvga_enabled = 1;
+ vga_interface_type = VGA_VMWARE;
} else if (strstart(p, "xenfb", &opts)) {
- xenfb_enabled = 1;
+ vga_interface_type = VGA_XENFB;
} else if (!strstart(p, "none", &opts)) {
invalid_vga:
fprintf(stderr, "Unknown vga type: %s\n", p);
diff --git a/vnc.c b/vnc.c
index 4fde9aae5..5eaef6a3e 100644
--- a/vnc.c
+++ b/vnc.c
@@ -2263,6 +2263,10 @@ int vnc_display_password(DisplayState *ds, const char *password)
{
VncDisplay *vs = ds ? (VncDisplay *)ds->opaque : vnc_display;
+ if (!vs) {
+ return -1;
+ }
+
if (vs->password) {
qemu_free(vs->password);
vs->password = NULL;
@@ -2270,6 +2274,11 @@ int vnc_display_password(DisplayState *ds, const char *password)
if (password && password[0]) {
if (!(vs->password = qemu_strdup(password)))
return -1;
+ if (vs->auth == VNC_AUTH_NONE) {
+ vs->auth = VNC_AUTH_VNC;
+ }
+ } else {
+ vs->auth = VNC_AUTH_NONE;
}
return 0;