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* Hardware convenience libraryPaul Brook2009-05-191-3/+0
* Support for VR5432, and some of its special instructions. Original patchths2007-12-251-5/+9
* Larger physical address space for 32-bit MIPS.ths2007-12-021-0/+3
* Clean out the N32 macros from target-mips, and introduce MIPS ABI specificths2007-11-081-1/+1
* Use the standard ASE check for MIPS-3D and MT.ths2007-10-231-0/+2
* Code provision for n32/n64 mips userland emulation. Not functional yet.ths2007-09-301-1/+1
* Per-CPU instruction decoding implementation, by Aurelien Jarno.ths2007-09-241-0/+35
* MIPS TLB style selection at runtime, by Herve Poussineau.ths2007-05-131-2/+0
* Kill broken host register definitions, thanks to Paul Brook and Herveths2007-04-291-2/+0
* Update comment. We can't easily adhere to the architecture spec becauseths2007-04-191-3/+3
* Choose number of TLBs at runtime, by Herve Poussineau.ths2007-04-171-1/+0
* Throw RI for invalid MFMC0-class instructions. Introduce optionalths2007-04-111-0/+5
* Actually enable 64bit configuration.ths2007-04-011-4/+1
* Move mips CPU specific initialization to translate_init.c.ths2007-03-211-37/+0
* MIPS -cpu selection support, by Herve Poussineau.ths2007-03-181-26/+0
* MIPS FPU dynamic activation, part 1, by Herve Poussineau.ths2007-02-281-9/+4
* Preliminiary MIPS64 support, disabled by default due to performance impact.ths2006-12-211-3/+10
* Add MIPS32R2 instructions, and generally straighten out the instructionths2006-12-061-16/+34
* MIPS TLB performance improvements, by Daniel Jacobowitz.ths2006-12-061-0/+1
* mips config fixes (initial patch by Stefan Weil)bellard2006-06-141-11/+14
* MIPS FPU support (Marius Goeger)bellard2006-06-141-3/+9
* MIPS target (Jocelyn Mayer)bellard2005-07-021-0/+58