diff options
authorNathan Froyd <>2012-06-07 15:04:14 +0000
committerDoug Goldstein <>2012-11-21 15:25:09 -0600
commita9ff62518fd8c969636d20cd12f84a44f00a08df (patch)
parentusb-storage: fix SYNCHRONIZE_CACHE (diff)
MIPS: Correct FCR0 initialization
This change addresses a problem where QEMU incorrectly traps on floating-point MADD group instructions with SIGILL, at least while emulating MIPS32r2 processors. These instructions use the COP1X major opcode and include ones like: madd.d $f2,$f4,$f2,$f6 Here's Nathan's original analysis of the problem: "QEMU essentially does: d = find_cpu (cpu_string) // get CPU definition fpu_init (env, d) // initialize fpu state (init FCR0, basically) cpu_reset (env) ...and the cpu_reset call clears all interesting state that fpu_init setup, then proceeds to reinitialize all the CP0 registers...but not FCR0." I have verified this change with system emulation running the GDB test suite for the mips-sde-elf target (o32, big endian, 24Kf CPU emulated), there were 55 progressions and no regressions. Signed-off-by: Maciej W. Rozycki <> Reviewed-by: Richard Henderson <> Signed-off-by: Blue Swirl <> (cherry picked from commit f1cb0951c5298753652a73cfd8efc0b1a82f37de)
1 files changed, 1 insertions, 0 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 5ed58f65e..8ff1fabc4 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -12783,6 +12783,7 @@ void cpu_state_reset(CPUMIPSState *env)
env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3;
env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask;
env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4;
+ env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
env->insn_flags = env->cpu_model->insn_flags;
#if defined(CONFIG_USER_ONLY)