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authorAndre Przywara <andre.przywara@amd.com>2009-10-23 13:44:31 +0200
committerAurelien Jarno <aurelien@aurel32.net>2009-10-23 17:10:36 +0200
commit31501a714b7a99fd7b937a45558ed02aa1b57d58 (patch)
treeff6ad928f74dd654a02770cd90a799ae8d17a83e /target-arm
parenttarget-ppc: move often used CPU fields at the top of the structure (diff)
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target-i386: implement lzcnt emulation
lzcnt is a AMD Phenom/Barcelona added instruction returning the number of leading zero bits in a word. As this is similar to the "bsr" instruction, reuse the existing code. There need to be some more changes, though, as lzcnt always returns a valid value (in opposite to bsr, which has a special case when the operand is 0). lzcnt is guarded by the ABM CPUID bit (Fn8000_0001:ECX_5). Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-arm')
0 files changed, 0 insertions, 0 deletions